Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1597988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

250454

1

T1

20

T2

17

T3

218

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	627128	1			T1	42		T2	40		T3	503
values[0x0]	595726	1			T1	50		T2	39		T3	518
values[0x1]	625588	1			T1	41		T2	39		T3	475

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1237795	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

610647

1

T1

41

T2

39

T3

491

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8551	1			T4	4		T18	3		T14	1
valid_sources[0x01]	7091	1			T1	1		T2	1		T4	7
valid_sources[0x02]	7233	1			T4	4		T16	10		T21	1
valid_sources[0x03]	7173	1			T1	4		T2	1		T4	3
valid_sources[0x04]	6518	1			T1	7		T4	14		T18	3
valid_sources[0x05]	7408	1			T2	2		T4	14		T16	19
valid_sources[0x06]	6708	1			T4	8		T13	1		T21	1
valid_sources[0x07]	7702	1			T4	7		T22	3		T23	6
valid_sources[0x08]	6812	1			T1	1		T4	19		T21	1
valid_sources[0x09]	7656	1			T4	16		T12	1		T21	1
valid_sources[0x0a]	6967	1			T1	1		T4	8		T20	2
valid_sources[0x0b]	6467	1			T4	3		T5	1		T14	1
valid_sources[0x0c]	7364	1			T1	1		T2	3		T4	14
valid_sources[0x0d]	8216	1			T21	1		T22	23		T23	4
valid_sources[0x0e]	7416	1			T4	7		T17	1		T13	13
valid_sources[0x0f]	7346	1			T4	8		T5	63		T21	1
valid_sources[0x10]	7027	1			T4	9		T16	20		T21	1
valid_sources[0x11]	7857	1			T4	1		T19	4		T13	51
valid_sources[0x12]	6482	1			T1	1		T2	1		T4	19
valid_sources[0x13]	6668	1			T2	1		T4	12		T5	64
valid_sources[0x14]	6877	1			T1	2		T4	11		T12	3
valid_sources[0x15]	7317	1			T4	17		T13	6		T16	17
valid_sources[0x16]	7226	1			T2	1		T4	16		T13	31
valid_sources[0x17]	6609	1			T4	7		T13	34		T22	38
valid_sources[0x18]	7070	1			T1	1		T4	2		T20	1
valid_sources[0x19]	7048	1			T2	1		T4	29		T16	10
valid_sources[0x1a]	7055	1			T4	3		T22	36		T23	5
valid_sources[0x1b]	8187	1			T4	13		T17	1		T20	1
valid_sources[0x1c]	7648	1			T2	1		T4	5		T5	38
valid_sources[0x1d]	6834	1			T2	1		T4	16		T5	27
valid_sources[0x1e]	7893	1			T4	8		T20	2		T16	12
valid_sources[0x1f]	7510	1			T4	11		T5	19		T20	5
valid_sources[0x20]	7327	1			T2	2		T4	9		T19	4
valid_sources[0x21]	7274	1			T4	11		T12	1		T21	1
valid_sources[0x22]	8026	1			T1	1		T4	4		T19	6
valid_sources[0x23]	6659	1			T4	8		T20	1		T13	13
valid_sources[0x24]	7988	1			T1	2		T2	2		T4	12
valid_sources[0x25]	6648	1			T4	16		T18	5		T20	1
valid_sources[0x26]	8106	1			T1	1		T4	9		T17	1
valid_sources[0x27]	7243	1			T4	4		T5	5		T14	1
valid_sources[0x28]	6938	1			T4	3		T15	6		T21	1
valid_sources[0x29]	7167	1			T4	3		T12	1		T17	1
valid_sources[0x2a]	7652	1			T4	2		T22	4		T23	4
valid_sources[0x2b]	8210	1			T4	3		T17	1		T14	1
valid_sources[0x2c]	7427	1			T1	1		T2	2		T4	3
valid_sources[0x2d]	6675	1			T1	3		T4	10		T21	1
valid_sources[0x2e]	6522	1			T4	4		T18	2		T14	1
valid_sources[0x2f]	6829	1			T1	2		T4	3		T12	4
valid_sources[0x30]	6288	1			T2	1		T4	8		T21	1
valid_sources[0x31]	7009	1			T4	6		T13	1		T21	1
valid_sources[0x32]	6487	1			T2	2		T4	9		T13	28
valid_sources[0x33]	7654	1			T4	17		T5	140		T20	9
valid_sources[0x34]	7806	1			T4	6		T13	73		T16	30
valid_sources[0x35]	8286	1			T1	1		T2	1		T13	5
valid_sources[0x36]	7133	1			T4	9		T5	1		T13	8
valid_sources[0x37]	6353	1			T2	2		T4	6		T5	13
valid_sources[0x38]	6877	1			T2	2		T4	8		T5	1
valid_sources[0x39]	7888	1			T3	270		T4	6		T13	27
valid_sources[0x3a]	6999	1			T2	2		T4	7		T18	4
valid_sources[0x3b]	6793	1			T1	1		T4	5		T14	1
valid_sources[0x3c]	7159	1			T2	2		T4	15		T20	5
valid_sources[0x3d]	6555	1			T4	7		T13	21		T22	3
valid_sources[0x3e]	6440	1			T4	5		T5	97		T19	2
valid_sources[0x3f]	7002	1			T4	17		T5	17		T21	1
valid_sources[0x40]	7139	1			T2	1		T4	6		T12	2
valid_sources[0x41]	6868	1			T4	11		T5	134		T20	2
valid_sources[0x42]	6982	1			T4	13		T21	1		T22	4
valid_sources[0x43]	6541	1			T4	2		T14	1		T13	14
valid_sources[0x44]	7837	1			T2	1		T4	6		T19	1
valid_sources[0x45]	7925	1			T4	4		T12	7		T18	1
valid_sources[0x46]	7171	1			T2	2		T4	6		T12	4
valid_sources[0x47]	6749	1			T4	11		T13	82		T16	12
valid_sources[0x48]	8040	1			T4	9		T5	3		T12	2
valid_sources[0x49]	6187	1			T4	10		T13	4		T16	15
valid_sources[0x4a]	8343	1			T1	1		T2	1		T4	19
valid_sources[0x4b]	7119	1			T2	2		T4	3		T16	6
valid_sources[0x4c]	6843	1			T2	1		T4	16		T20	1
valid_sources[0x4d]	7723	1			T1	1		T4	14		T16	18
valid_sources[0x4e]	6893	1			T1	1		T4	9		T15	2
valid_sources[0x4f]	7328	1			T4	5		T12	1		T14	1
valid_sources[0x50]	6780	1			T2	1		T4	9		T18	2
valid_sources[0x51]	6945	1			T4	20		T13	43		T16	13
valid_sources[0x52]	6840	1			T4	16		T19	3		T20	4
valid_sources[0x53]	7338	1			T4	13		T22	30		T26	1
valid_sources[0x54]	6391	1			T1	1		T4	10		T12	8
valid_sources[0x55]	6113	1			T1	1		T4	15		T5	16
valid_sources[0x56]	8150	1			T1	3		T4	1		T5	55
valid_sources[0x57]	7089	1			T4	4		T16	13		T22	15
valid_sources[0x58]	7149	1			T2	1		T4	3		T12	5
valid_sources[0x59]	6852	1			T2	1		T4	10		T22	9
valid_sources[0x5a]	8558	1			T4	11		T18	9		T13	31
valid_sources[0x5b]	7677	1			T4	7		T19	12		T21	1
valid_sources[0x5c]	7229	1			T1	3		T4	7		T13	65
valid_sources[0x5d]	6254	1			T1	2		T4	4		T5	1
valid_sources[0x5e]	7489	1			T1	2		T3	376		T4	13
valid_sources[0x5f]	6919	1			T4	18		T18	4		T13	16
valid_sources[0x60]	7143	1			T4	3		T20	1		T16	19
valid_sources[0x61]	7493	1			T2	1		T4	8		T20	3
valid_sources[0x62]	7401	1			T4	3		T5	7		T12	3
valid_sources[0x63]	6686	1			T4	23		T13	32		T22	29
valid_sources[0x64]	6606	1			T4	4		T13	54		T21	1
valid_sources[0x65]	6793	1			T1	1		T4	6		T5	17
valid_sources[0x66]	6763	1			T4	3		T20	3		T21	1
valid_sources[0x67]	7007	1			T1	1		T2	2		T4	18
valid_sources[0x68]	6956	1			T1	1		T2	1		T4	10
valid_sources[0x69]	7027	1			T4	1		T13	50		T16	7
valid_sources[0x6a]	6217	1			T4	4		T17	1		T16	32
valid_sources[0x6b]	7435	1			T4	17		T20	3		T13	2
valid_sources[0x6c]	7569	1			T1	2		T4	5		T12	1
valid_sources[0x6d]	7815	1			T4	7		T17	1		T13	7
valid_sources[0x6e]	7303	1			T1	2		T4	9		T21	1
valid_sources[0x6f]	8081	1			T4	3		T13	10		T21	1
valid_sources[0x70]	7852	1			T2	1		T4	3		T12	5
valid_sources[0x71]	6966	1			T1	1		T4	2		T20	7
valid_sources[0x72]	7801	1			T1	1		T3	376		T4	1
valid_sources[0x73]	7204	1			T4	7		T13	6		T21	1
valid_sources[0x74]	6895	1			T4	6		T13	32		T16	9
valid_sources[0x75]	6552	1			T4	6		T16	26		T21	1
valid_sources[0x76]	6886	1			T2	1		T4	3		T5	6
valid_sources[0x77]	7008	1			T4	12		T14	2		T16	18
valid_sources[0x78]	7216	1			T4	5		T5	44		T14	1
valid_sources[0x79]	7013	1			T4	6		T14	1		T16	33
valid_sources[0x7a]	7763	1			T2	1		T4	1		T14	1
valid_sources[0x7b]	7043	1			T4	11		T5	3		T18	10
valid_sources[0x7c]	6922	1			T1	1		T2	1		T4	2
valid_sources[0x7d]	7839	1			T1	2		T2	1		T4	8
valid_sources[0x7e]	6928	1			T2	1		T4	2		T13	20
valid_sources[0x7f]	7513	1			T4	5		T5	6		T13	26
valid_sources[0x80]	7968	1			T4	14		T12	3		T16	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26691

1

T1

1

T2

1

T3

27

values[0x0]

all_enables

biggest_size

197003

1

T1

19

T2

15

T3

173

values[0x1]

all_enables

biggest_size

26760

1

T2

1

T3

18

T4

32