Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	322684178	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	322684178
T1	237496	5517
T2	16296	580
T3	89152	5984
T4	252168	10344
T5	1769264	37159
T12	9185008	192270
T13	0	884
T14	1128400	16866
T17	33208	922
T18	6918184	216453
T19	35280	707
T20	0	1447

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	237496	235928
T2	16296	15848
T3	89152	88592
T4	252168	249480
T5	1769264	1766296
T12	9185008	9183888
T14	1128400	1125992
T17	33208	31304
T18	6918184	6914656
T19	35280	32872

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	237496	235928
T2	16296	15848
T3	89152	88592
T4	252168	249480
T5	1769264	1766296
T12	9185008	9183888
T14	1128400	1125992
T17	33208	31304
T18	6918184	6914656
T19	35280	32872

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	237496	235928
T2	16296	15848
T3	89152	88592
T4	252168	249480
T5	1769264	1766296
T12	9185008	9183888
T14	1128400	1125992
T17	33208	31304
T18	6918184	6914656
T19	35280	32872

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T12	56	56
T14	56	56
T17	56	56
T18	56	56
T19	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	123252666	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	123252666
T1	4241	2246
T2	291	226
T3	1592	1496
T4	4503	4038
T5	31594	16446
T12	164018	85373
T14	20150	7505
T17	593	358
T18	123539	120799
T19	630	275

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	79865640	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	79865640
T1	4241	1152
T2	291	118
T3	1592	1496
T4	4503	2102
T5	31594	4901
T12	164018	31212
T14	20150	2718
T17	593	188
T18	123539	47535
T19	630	144

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1489948	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1489948
T1	4241	94
T2	291	9
T3	1592	0
T4	4503	73
T5	31594	368
T12	164018	1880
T14	20150	194
T17	593	8
T18	123539	51
T19	630	10
T20	0	54

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2479682	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2479682
T1	4241	78
T2	291	9
T3	1592	0
T4	4503	73
T5	31594	211
T12	164018	1583
T14	20150	77
T17	593	8
T18	123539	2961
T19	630	10
T20	0	60

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1510152	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1510152
T1	4241	18
T2	291	4
T3	1592	0
T4	4503	72
T5	31594	375
T12	164018	1261
T14	20150	152
T17	593	3
T18	123539	7
T19	630	9
T20	0	37

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2851962	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2851962
T1	4241	21
T2	291	4
T3	1592	0
T4	4503	72
T5	31594	159
T12	164018	1070
T14	20150	39
T17	593	3
T18	123539	972
T19	630	9
T20	0	32

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1493025	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1493025
T1	4241	65
T2	291	5
T3	1592	0
T4	4503	93
T5	31594	386
T12	164018	2359
T14	20150	133
T17	593	6
T18	123539	8
T19	630	3
T20	0	26

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2960977	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2960977
T1	4241	55
T2	291	5
T3	1592	0
T4	4503	93
T5	31594	192
T12	164018	2757
T14	20150	71
T17	593	6
T18	123539	361
T19	630	3
T20	0	11

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1523933	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1523933
T1	4241	16
T2	291	1
T3	1592	0
T4	4503	86
T5	31594	397
T12	164018	1534
T14	20150	207
T17	593	6
T18	123539	21
T19	630	1
T20	0	22

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3060095	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3060095
T1	4241	36
T2	291	1
T3	1592	0
T4	4503	86
T5	31594	202
T12	164018	1136
T14	20150	78
T17	593	6
T18	123539	2309
T19	630	1
T20	0	28

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1539083	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1539083
T1	4241	47
T2	291	4
T3	1592	268
T4	4503	87
T5	31594	482
T12	164018	1674
T14	20150	189
T17	593	9
T18	123539	13
T19	630	3

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3109567	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3109567
T1	4241	32
T2	291	4
T3	1592	268
T4	4503	87
T5	31594	219
T12	164018	962
T14	20150	81
T17	593	9
T18	123539	1050
T19	630	3

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1504989	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1504989
T1	4241	16
T2	291	4
T3	1592	0
T4	4503	74
T5	31594	340
T12	164018	498
T14	20150	151
T17	593	3
T18	123539	13
T19	630	7
T20	0	66

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3294961	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3294961
T1	4241	24
T2	291	4
T3	1592	0
T4	4503	74
T5	31594	149
T12	164018	618
T14	20150	102
T17	593	3
T18	123539	1363
T19	630	7
T20	0	93

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1507155	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1507155
T1	4241	11
T2	291	6
T3	1592	0
T4	4503	80
T5	31594	384
T12	164018	1298
T14	20150	206
T17	593	7
T18	123539	12
T19	630	6
T20	0	14

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2687936	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2687936
T1	4241	20
T2	291	6
T3	1592	0
T4	4503	80
T5	31594	219
T12	164018	1858
T14	20150	79
T17	593	7
T18	123539	821
T19	630	6
T20	0	24

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1440082	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1440082
T1	4241	27
T2	291	2
T3	1592	290
T4	4503	76
T5	31594	263
T12	164018	726
T14	20150	103
T17	593	5
T18	123539	10
T19	630	4

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2661227	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2661227
T1	4241	46
T2	291	2
T3	1592	290
T4	4503	76
T5	31594	81
T12	164018	162
T14	20150	38
T17	593	5
T18	123539	2119
T19	630	4

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1540695	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1540695
T1	4241	14
T2	291	4
T3	1592	455
T4	4503	74
T5	31594	489
T12	164018	1494
T14	20150	231
T17	593	7
T18	123539	12
T19	630	5

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3432268	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3432268
T1	4241	14
T2	291	4
T3	1592	455
T4	4503	74
T5	31594	219
T12	164018	1052
T14	20150	122
T17	593	7
T18	123539	1479
T19	630	5

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1541139	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1541139
T1	4241	33
T2	291	6
T3	1592	227
T4	4503	84
T5	31594	516
T12	164018	2193
T14	20150	166
T17	593	6
T18	123539	36
T19	630	8

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2698358	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2698358
T1	4241	27
T2	291	6
T3	1592	227
T4	4503	84
T5	31594	209
T12	164018	2118
T14	20150	55
T17	593	6
T18	123539	3078
T19	630	8

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1489228	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1489228
T1	4241	51
T2	291	6
T3	1592	0
T4	4503	63
T5	31594	371
T12	164018	2401
T14	20150	139
T17	593	7
T18	123539	32
T19	630	6
T20	0	13

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2458787	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2458787
T1	4241	112
T2	291	6
T3	1592	0
T4	4503	63
T5	31594	188
T12	164018	2122
T14	20150	71
T17	593	7
T18	123539	2797
T19	630	6
T20	0	10

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1545729	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1545729
T1	4241	52
T2	291	0
T3	1592	0
T4	4503	66
T5	31594	522
T12	164018	1197
T13	0	414
T14	20150	111
T17	593	9
T18	123539	27
T19	630	5
T20	0	24

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T4 T5 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3059663	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3059663
T1	4241	55
T2	291	0
T3	1592	0
T4	4503	66
T5	31594	207
T12	164018	821
T13	0	470
T14	20150	68
T17	593	9
T18	123539	3121
T19	630	5
T20	0	29

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1517156	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1517156
T1	4241	46
T2	291	5
T3	1592	0
T4	4503	76
T5	31594	485
T12	164018	1854
T14	20150	134
T17	593	11
T18	123539	20
T19	630	10
T20	0	41

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2852286	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2852286
T1	4241	44
T2	291	5
T3	1592	0
T4	4503	76
T5	31594	176
T12	164018	760
T14	20150	49
T17	593	11
T18	123539	1556
T19	630	10
T20	0	28

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1514774	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1514774
T1	4241	36
T2	291	4
T3	1592	0
T4	4503	80
T5	31594	387
T12	164018	907
T14	20150	135
T17	593	7
T18	123539	14
T19	630	5
T20	0	16

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2325846	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2325846
T1	4241	55
T2	291	4
T3	1592	0
T4	4503	80
T5	31594	150
T12	164018	712
T14	20150	107
T17	593	7
T18	123539	1718
T19	630	5
T20	0	35

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1536985	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1536985
T1	4241	45
T2	291	5
T3	1592	0
T4	4503	73
T5	31594	500
T12	164018	165
T14	20150	206
T17	593	5
T18	123539	39
T19	630	4
T20	0	16

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3189818	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3189818
T1	4241	31
T2	291	5
T3	1592	0
T4	4503	73
T5	31594	198
T12	164018	25
T14	20150	117
T17	593	5
T18	123539	1788
T19	630	4
T20	0	7

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1519553	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1519553
T1	4241	47
T2	291	2
T3	1592	0
T4	4503	82
T5	31594	409
T12	164018	2444
T14	20150	174
T17	593	7
T18	123539	29
T19	630	7
T20	0	21

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2565149	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2565149
T1	4241	38
T2	291	2
T3	1592	0
T4	4503	82
T5	31594	152
T12	164018	795
T14	20150	106
T17	593	7
T18	123539	3405
T19	630	7
T20	0	13

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1523069	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1523069
T1	4241	46
T2	291	3
T3	1592	0
T4	4503	88
T5	31594	349
T12	164018	3281
T14	20150	237
T17	593	14
T18	123539	33
T19	630	8
T20	0	33

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2352059	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2352059
T1	4241	66
T2	291	3
T3	1592	0
T4	4503	88
T5	31594	168
T12	164018	1931
T14	20150	88
T17	593	14
T18	123539	966
T19	630	8
T20	0	23

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1547209	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1547209
T1	4241	24
T2	291	1
T3	1592	0
T4	4503	66
T5	31594	310
T12	164018	2490
T14	20150	198
T17	593	12
T18	123539	14
T19	630	2
T20	0	33

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3488721	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3488721
T1	4241	13
T2	291	1
T3	1592	0
T4	4503	66
T5	31594	192
T12	164018	1474
T14	20150	106
T17	593	12
T18	123539	1781
T19	630	2
T20	0	31

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1483044	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1483044
T1	4241	32
T2	291	3
T3	1592	0
T4	4503	72
T5	31594	331
T12	164018	1270
T14	20150	173
T17	593	3
T18	123539	20
T19	630	9
T20	0	9

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3363939	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3363939
T1	4241	28
T2	291	3
T3	1592	0
T4	4503	72
T5	31594	146
T12	164018	2062
T14	20150	92
T17	593	3
T18	123539	263
T19	630	9
T20	0	28

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1519661	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1519661
T1	4241	15
T2	291	6
T3	1592	0
T4	4503	79
T5	31594	290
T12	164018	1373
T14	20150	164
T17	593	7
T18	123539	8
T19	630	6
T20	0	19

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3256289	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3256289
T1	4241	5
T2	291	6
T3	1592	0
T4	4503	79
T5	31594	152
T12	164018	371
T14	20150	71
T17	593	7
T18	123539	1005
T19	630	6
T20	0	28

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1475306	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1475306
T1	4241	38
T2	291	2
T3	1592	0
T4	4503	76
T5	31594	404
T12	164018	1930
T14	20150	154
T17	593	5
T18	123539	27
T19	630	3
T20	0	41

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3298540	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3298540
T1	4241	23
T2	291	2
T3	1592	0
T4	4503	76
T5	31594	146
T12	164018	1564
T14	20150	61
T17	593	5
T18	123539	2430
T19	630	3
T20	0	57

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1473405	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1473405
T1	4241	34
T2	291	8
T3	1592	0
T4	4503	82
T5	31594	354
T12	164018	2088
T14	20150	151
T17	593	13
T18	123539	39
T19	630	2
T20	0	42

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2891674	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2891674
T1	4241	85
T2	291	8
T3	1592	0
T4	4503	82
T5	31594	191
T12	164018	574
T14	20150	89
T17	593	13
T18	123539	2624
T19	630	2
T20	0	84

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1522011	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1522011
T1	4241	24
T2	291	4
T3	1592	0
T4	4503	87
T5	31594	552
T12	164018	2488
T14	20150	163
T17	593	8
T18	123539	32
T19	630	1
T20	0	37

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2917744	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2917744
T1	4241	50
T2	291	4
T3	1592	0
T4	4503	87
T5	31594	251
T12	164018	1220
T14	20150	49
T17	593	8
T18	123539	1719
T19	630	1
T20	0	40

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1508174	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1508174
T1	4241	7
T2	291	5
T3	1592	0
T4	4503	88
T5	31594	446
T12	164018	804
T14	20150	167
T17	593	7
T18	123539	12
T19	630	7
T20	0	24

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	3024463	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	3024463
T1	4241	13
T2	291	5
T3	1592	0
T4	4503	88
T5	31594	186
T12	164018	309
T14	20150	53
T17	593	7
T18	123539	698
T19	630	7
T20	0	11

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1457831	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1457831
T1	4241	49
T2	291	4
T3	1592	256
T4	4503	71
T5	31594	416
T12	164018	1778
T14	20150	116
T17	593	3
T18	123539	18
T19	630	5

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2770293	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2770293
T1	4241	54
T2	291	4
T3	1592	256
T4	4503	71
T5	31594	180
T12	164018	1616
T14	20150	52
T17	593	3
T18	123539	1055
T19	630	5

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1514089	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1514089
T1	4241	32
T2	291	9
T3	1592	0
T4	4503	73
T5	31594	444
T12	164018	1685
T14	20150	171
T17	593	3
T18	123539	19
T19	630	4
T20	0	89

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2904719	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2904719
T1	4241	45
T2	291	9
T3	1592	0
T4	4503	73
T5	31594	193
T12	164018	1000
T14	20150	93
T17	593	3
T18	123539	1969
T19	630	4
T20	0	63

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	1534980	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	1534980
T1	4241	48
T2	291	6
T3	1592	0
T4	4503	81
T5	31594	341
T12	164018	1401
T14	20150	204
T17	593	7
T18	123539	18
T19	630	4
T20	0	26

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294496038	2836444	0	0
DepthKnown_A	294496038	294378706	0	0
RvalidKnown_A	294496038	294378706	0	0
WreadyKnown_A	294496038	294378706	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294496038	2836444
T1	4241	82
T2	291	6
T3	1592	0
T4	4503	81
T5	31594	165
T12	164018	540
T14	20150	100
T17	593	7
T18	123539	2127
T19	630	4
T20	0	9

DepthKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

RvalidKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

WreadyKnown_A

Name	Attempts	Real Successes
Total	294496038	294378706
T1	4241	4213
T2	291	283
T3	1592	1582
T4	4503	4455
T5	31594	31541
T12	164018	163998
T14	20150	20107
T17	593	559
T18	123539	123476
T19	630	587

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T12	1	1
T14	1	1
T17	1	1
T18	1	1
T19	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children