Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1646840	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

258995

1

T1

20

T2

16

T3

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	645471	1			T1	61		T2	56		T3	163
values[0x0]	614993	1			T1	46		T2	45		T3	146
values[0x1]	645371	1			T1	43		T2	46		T3	139

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1276484	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

629351

1

T1

49

T2

45

T3

150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6987	1			T2	1		T4	1		T15	2
valid_sources[0x01]	6817	1			T1	1		T4	1		T16	1
valid_sources[0x02]	8299	1			T1	1		T17	5		T18	13
valid_sources[0x03]	6733	1			T4	4		T16	1		T17	9
valid_sources[0x04]	8436	1			T15	1		T17	4		T18	7
valid_sources[0x05]	6864	1			T2	2		T4	2		T17	7
valid_sources[0x06]	7106	1			T1	1		T15	1		T17	4
valid_sources[0x07]	6598	1			T1	1		T2	8		T4	3
valid_sources[0x08]	6886	1			T1	3		T4	1		T15	4
valid_sources[0x09]	8332	1			T2	2		T16	1		T17	6
valid_sources[0x0a]	7920	1			T4	6		T17	6		T19	2
valid_sources[0x0b]	7015	1			T4	1		T15	2		T17	2
valid_sources[0x0c]	7244	1			T1	1		T4	2		T17	3
valid_sources[0x0d]	7232	1			T15	1		T16	2		T17	3
valid_sources[0x0e]	7326	1			T4	1		T15	3		T16	2
valid_sources[0x0f]	7650	1			T2	2		T16	1		T17	8
valid_sources[0x10]	7074	1			T4	2		T17	4		T23	15
valid_sources[0x11]	6991	1			T16	1		T17	8		T23	20
valid_sources[0x12]	6980	1			T16	1		T17	4		T23	18
valid_sources[0x13]	7176	1			T4	2		T17	7		T21	38
valid_sources[0x14]	7710	1			T1	4		T2	1		T15	1
valid_sources[0x15]	6948	1			T17	6		T20	2		T23	9
valid_sources[0x16]	6663	1			T1	1		T17	6		T23	15
valid_sources[0x17]	7993	1			T2	1		T15	1		T17	7
valid_sources[0x18]	7072	1			T1	3		T17	6		T23	10
valid_sources[0x19]	7139	1			T4	2		T17	1		T19	2
valid_sources[0x1a]	7565	1			T4	1		T16	1		T17	5
valid_sources[0x1b]	7684	1			T17	4		T20	1		T23	13
valid_sources[0x1c]	8375	1			T4	5		T15	1		T17	4
valid_sources[0x1d]	8183	1			T2	2		T4	3		T15	1
valid_sources[0x1e]	6833	1			T4	1		T15	1		T17	6
valid_sources[0x1f]	7195	1			T1	2		T4	3		T17	3
valid_sources[0x20]	7761	1			T4	2		T17	4		T19	2
valid_sources[0x21]	6712	1			T1	1		T4	1		T15	3
valid_sources[0x22]	7743	1			T15	2		T17	7		T23	12
valid_sources[0x23]	7549	1			T1	1		T4	1		T15	1
valid_sources[0x24]	7700	1			T1	1		T17	3		T23	8
valid_sources[0x25]	6674	1			T4	2		T15	2		T17	6
valid_sources[0x26]	6138	1			T1	1		T4	4		T17	5
valid_sources[0x27]	7268	1			T4	1		T17	6		T14	4
valid_sources[0x28]	8623	1			T1	4		T4	4		T15	1
valid_sources[0x29]	8211	1			T1	1		T17	3		T14	2
valid_sources[0x2a]	8262	1			T1	3		T2	3		T15	3
valid_sources[0x2b]	6872	1			T17	6		T20	1		T23	4
valid_sources[0x2c]	8494	1			T4	1		T17	4		T23	16
valid_sources[0x2d]	7798	1			T2	1		T4	1		T15	2
valid_sources[0x2e]	7930	1			T4	1		T15	3		T17	6
valid_sources[0x2f]	6870	1			T4	3		T17	2		T18	15
valid_sources[0x30]	6852	1			T17	3		T19	1		T23	10
valid_sources[0x31]	7416	1			T4	7		T17	4		T19	1
valid_sources[0x32]	7288	1			T1	1		T4	1		T17	5
valid_sources[0x33]	7629	1			T1	3		T2	3		T4	5
valid_sources[0x34]	7054	1			T2	2		T4	1		T15	2
valid_sources[0x35]	9014	1			T1	1		T2	2		T4	2
valid_sources[0x36]	7754	1			T15	2		T17	9		T23	1
valid_sources[0x37]	7651	1			T4	4		T17	7		T21	29
valid_sources[0x38]	6965	1			T17	6		T19	1		T20	1
valid_sources[0x39]	7257	1			T16	2		T17	7		T20	2
valid_sources[0x3a]	7770	1			T4	3		T6	20		T17	2
valid_sources[0x3b]	7449	1			T2	5		T16	2		T17	9
valid_sources[0x3c]	7238	1			T2	2		T4	2		T17	2
valid_sources[0x3d]	6914	1			T1	1		T15	2		T17	7
valid_sources[0x3e]	7301	1			T1	1		T2	1		T4	1
valid_sources[0x3f]	7051	1			T3	73		T15	3		T17	13
valid_sources[0x40]	7474	1			T1	1		T4	3		T17	7
valid_sources[0x41]	7728	1			T4	1		T17	3		T18	20
valid_sources[0x42]	6492	1			T4	3		T17	4		T23	14
valid_sources[0x43]	7965	1			T1	1		T4	2		T17	8
valid_sources[0x44]	7259	1			T1	3		T17	5		T22	7
valid_sources[0x45]	9387	1			T1	1		T2	2		T4	8
valid_sources[0x46]	7302	1			T4	2		T15	2		T17	6
valid_sources[0x47]	7091	1			T17	9		T18	7		T20	1
valid_sources[0x48]	7017	1			T4	3		T16	1		T17	2
valid_sources[0x49]	7783	1			T1	1		T2	3		T4	2
valid_sources[0x4a]	7809	1			T1	3		T2	1		T15	1
valid_sources[0x4b]	8601	1			T4	2		T15	4		T16	1
valid_sources[0x4c]	7860	1			T17	5		T19	1		T23	9
valid_sources[0x4d]	6653	1			T4	5		T16	1		T17	2
valid_sources[0x4e]	7726	1			T4	2		T15	1		T17	10
valid_sources[0x4f]	7685	1			T1	1		T17	3		T23	11
valid_sources[0x50]	6929	1			T2	3		T4	3		T15	2
valid_sources[0x51]	6265	1			T4	4		T15	1		T17	3
valid_sources[0x52]	7359	1			T4	4		T16	2		T17	5
valid_sources[0x53]	7716	1			T1	4		T4	1		T17	1
valid_sources[0x54]	6750	1			T3	177		T15	5		T17	7
valid_sources[0x55]	8415	1			T1	2		T4	1		T17	4
valid_sources[0x56]	8477	1			T4	2		T17	5		T19	1
valid_sources[0x57]	7004	1			T1	1		T4	6		T17	7
valid_sources[0x58]	8611	1			T1	2		T17	3		T23	18
valid_sources[0x59]	6466	1			T1	1		T15	5		T17	5
valid_sources[0x5a]	7337	1			T4	7		T17	6		T18	7
valid_sources[0x5b]	7719	1			T1	1		T2	2		T4	2
valid_sources[0x5c]	7811	1			T2	1		T17	5		T13	1
valid_sources[0x5d]	7280	1			T1	4		T16	1		T17	7
valid_sources[0x5e]	7841	1			T2	1		T17	4		T23	8
valid_sources[0x5f]	8984	1			T1	4		T2	5		T4	1
valid_sources[0x60]	8949	1			T1	1		T6	9		T17	3
valid_sources[0x61]	7614	1			T4	1		T15	3		T17	1
valid_sources[0x62]	7473	1			T2	4		T16	1		T17	6
valid_sources[0x63]	7698	1			T1	1		T4	1		T15	3
valid_sources[0x64]	8231	1			T4	1		T15	1		T17	4
valid_sources[0x65]	7473	1			T1	3		T2	1		T17	5
valid_sources[0x66]	7528	1			T16	2		T17	8		T23	14
valid_sources[0x67]	7683	1			T2	1		T4	5		T17	5
valid_sources[0x68]	7101	1			T2	1		T3	14		T17	3
valid_sources[0x69]	7219	1			T15	2		T16	1		T6	9
valid_sources[0x6a]	7121	1			T1	1		T4	1		T15	2
valid_sources[0x6b]	7345	1			T16	1		T17	2		T19	1
valid_sources[0x6c]	8017	1			T1	4		T2	3		T4	2
valid_sources[0x6d]	6767	1			T2	3		T4	5		T17	7
valid_sources[0x6e]	8149	1			T2	2		T4	1		T17	3
valid_sources[0x6f]	7468	1			T4	4		T15	1		T16	1
valid_sources[0x70]	8298	1			T2	1		T4	1		T17	3
valid_sources[0x71]	6779	1			T2	1		T3	4		T17	4
valid_sources[0x72]	7441	1			T4	2		T16	2		T17	6
valid_sources[0x73]	8307	1			T4	6		T6	39		T17	2
valid_sources[0x74]	7297	1			T17	7		T13	1		T19	2
valid_sources[0x75]	7880	1			T2	2		T4	1		T6	1
valid_sources[0x76]	7245	1			T4	2		T16	2		T17	3
valid_sources[0x77]	7159	1			T2	1		T4	3		T15	2
valid_sources[0x78]	7860	1			T2	2		T4	2		T17	7
valid_sources[0x79]	8284	1			T4	7		T15	3		T16	1
valid_sources[0x7a]	6678	1			T17	4		T13	2		T23	5
valid_sources[0x7b]	7256	1			T15	3		T16	1		T17	7
valid_sources[0x7c]	7658	1			T17	2		T13	1		T19	2
valid_sources[0x7d]	7525	1			T17	7		T19	2		T20	1
valid_sources[0x7e]	7804	1			T16	3		T17	3		T23	3
valid_sources[0x7f]	8094	1			T1	1		T4	3		T17	9
valid_sources[0x80]	9171	1			T1	2		T4	1		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27530

1

T1

2

T2

2

T3

4

values[0x0]

all_enables

biggest_size

204163

1

T1

14

T2

13

T3

53

values[0x1]

all_enables

biggest_size

27302

1

T1

4

T2

1

T3

1