Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	322351568	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	322351568
T1	21224	738
T2	33656	719
T3	57736	2198
T4	61152	1540
T5	21336	621
T6	5309192	95070
T13	1357552	31449
T15	37688	946
T16	200424	7927
T17	2045792	53088

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	21224	20664
T2	33656	31584
T3	57736	56616
T4	61152	59528
T5	21336	20216
T6	5309192	5308296
T13	1357552	1354752
T15	37688	35112
T16	200424	196952
T17	2045792	2043440

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	21224	20664
T2	33656	31584
T3	57736	56616
T4	61152	59528
T5	21336	20216
T6	5309192	5308296
T13	1357552	1354752
T15	37688	35112
T16	200424	196952
T17	2045792	2043440

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	21224	20664
T2	33656	31584
T3	57736	56616
T4	61152	59528
T5	21336	20216
T6	5309192	5308296
T13	1357552	1354752
T15	37688	35112
T16	200424	196952
T17	2045792	2043440

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T6	56	56
T13	56	56
T15	56	56
T16	56	56
T17	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	125143404	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	125143404
T1	379	288
T2	601	278
T3	1031	854
T4	1092	769
T5	381	240
T6	94807	91976
T13	24242	12460
T15	673	366
T16	3579	3090
T17	36532	22484

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	79388460	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	79388460
T1	379	150
T2	601	147
T3	1031	448
T4	1092	393
T5	381	127
T6	94807	1172
T13	24242	10625
T15	673	194
T16	3579	1613
T17	36532	10413

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1487388	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1487388
T1	379	5
T2	601	7
T3	1031	23
T4	1092	6
T5	381	3
T6	94807	24
T13	24242	174
T15	673	6
T16	3579	55
T17	36532	533

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3506750	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3506750
T1	379	5
T2	601	7
T3	1031	23
T4	1092	6
T5	381	3
T6	94807	6
T13	24242	160
T15	673	6
T16	3579	55
T17	36532	428

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1459240	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1459240
T1	379	4
T2	601	6
T3	1031	17
T4	1092	3
T5	381	4
T6	94807	37
T13	24242	143
T15	673	3
T16	3579	51
T17	36532	310

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2511555	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2511555
T1	379	4
T2	601	6
T3	1031	17
T4	1092	3
T5	381	4
T6	94807	8
T13	24242	216
T15	673	3
T16	3579	51
T17	36532	321

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1448996	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1448996
T1	379	8
T2	601	1
T3	1031	20
T4	1092	2
T5	381	8
T6	94807	28
T13	24242	180
T15	673	3
T16	3579	64
T17	36532	314

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3434994	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3434994
T1	379	8
T2	601	1
T3	1031	20
T4	1092	2
T5	381	8
T6	94807	9
T13	24242	185
T15	673	3
T16	3579	64
T17	36532	408

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1441825	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1441825
T1	379	7
T2	601	8
T3	1031	18
T4	1092	8
T5	381	5
T6	94807	26
T13	24242	179
T15	673	11
T16	3579	61
T17	36532	329

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2688352	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2688352
T1	379	7
T2	601	8
T3	1031	18
T4	1092	8
T5	381	5
T6	94807	7
T13	24242	161
T15	673	11
T16	3579	61
T17	36532	407

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1433475	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1433475
T1	379	1
T2	601	2
T3	1031	10
T4	1092	9
T5	381	9
T6	94807	30
T13	24242	119
T15	673	4
T16	3579	67
T17	36532	345

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3989577	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3989577
T1	379	1
T2	601	2
T3	1031	10
T4	1092	9
T5	381	9
T6	94807	7
T13	24242	91
T15	673	4
T16	3579	67
T17	36532	444

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1388615	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1388615
T1	379	3
T2	601	4
T3	1031	19
T4	1092	6
T5	381	5
T6	94807	9
T13	24242	120
T15	673	5
T16	3579	53
T17	36532	253

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2842508	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2842508
T1	379	3
T2	601	4
T3	1031	19
T4	1092	6
T5	381	5
T6	94807	3
T13	24242	115
T15	673	5
T16	3579	53
T17	36532	364

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1446796	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1446796
T1	379	4
T2	601	5
T3	1031	15
T4	1092	5
T5	381	10
T6	94807	27
T13	24242	99
T15	673	5
T16	3579	59
T17	36532	538

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2482231	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2482231
T1	379	4
T2	601	5
T3	1031	15
T4	1092	5
T5	381	10
T6	94807	8
T13	24242	90
T15	673	5
T16	3579	59
T17	36532	489

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1474024	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1474024
T1	379	7
T2	601	6
T3	1031	14
T4	1092	10
T5	381	3
T6	94807	38
T13	24242	185
T15	673	8
T16	3579	60
T17	36532	342

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3045926	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3045926
T1	379	7
T2	601	6
T3	1031	14
T4	1092	10
T5	381	3
T6	94807	10
T13	24242	214
T15	673	8
T16	3579	60
T17	36532	315

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1433304	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1433304
T1	379	2
T2	601	2
T3	1031	10
T4	1092	8
T5	381	6
T6	94807	36
T13	24242	119
T15	673	9
T16	3579	62
T17	36532	400

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2652646	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2652646
T1	379	2
T2	601	2
T3	1031	10
T4	1092	8
T5	381	6
T6	94807	10
T13	24242	121
T15	673	9
T16	3579	62
T17	36532	484

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1459330	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1459330
T1	379	2
T2	601	5
T3	1031	16
T4	1092	8
T5	381	5
T6	94807	29
T13	24242	154
T15	673	6
T16	3579	65
T17	36532	436

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2744525	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2744525
T1	379	2
T2	601	5
T3	1031	16
T4	1092	8
T5	381	5
T6	94807	5
T13	24242	153
T15	673	6
T16	3579	65
T17	36532	381

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1454718	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1454718
T1	379	6
T2	601	5
T3	1031	20
T4	1092	5
T5	381	9
T6	94807	47
T13	24242	130
T15	673	5
T16	3579	66
T17	36532	310

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3464607	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3464607
T1	379	6
T2	601	5
T3	1031	20
T4	1092	5
T5	381	9
T6	94807	11
T13	24242	94
T15	673	5
T16	3579	66
T17	36532	325

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1495589	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1495589
T1	379	7
T2	601	3
T3	1031	23
T4	1092	8
T5	381	2
T6	94807	14
T13	24242	152
T15	673	7
T16	3579	62
T17	36532	310

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2867020	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2867020
T1	379	7
T2	601	3
T3	1031	23
T4	1092	8
T5	381	2
T6	94807	3
T13	24242	159
T15	673	7
T16	3579	62
T17	36532	419

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1425867	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1425867
T1	379	9
T2	601	5
T3	1031	12
T4	1092	3
T5	381	6
T6	94807	9
T13	24242	155
T15	673	9
T16	3579	61
T17	36532	347

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2805446	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2805446
T1	379	9
T2	601	5
T3	1031	12
T4	1092	3
T5	381	6
T6	94807	5
T13	24242	193
T15	673	9
T16	3579	61
T17	36532	355

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1438539	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1438539
T1	379	4
T2	601	3
T3	1031	14
T4	1092	7
T5	381	3
T6	94807	39
T13	24242	199
T15	673	8
T16	3579	54
T17	36532	360

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3009661	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3009661
T1	379	4
T2	601	3
T3	1031	14
T4	1092	7
T5	381	3
T6	94807	11
T13	24242	155
T15	673	8
T16	3579	54
T17	36532	367

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1466160	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1466160
T1	379	11
T2	601	6
T3	1031	17
T4	1092	9
T5	381	7
T6	94807	28
T13	24242	114
T15	673	9
T16	3579	60
T17	36532	359

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2965869	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2965869
T1	379	11
T2	601	6
T3	1031	17
T4	1092	9
T5	381	7
T6	94807	6
T13	24242	203
T15	673	9
T16	3579	60
T17	36532	416

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1465819	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1465819
T1	379	6
T2	601	11
T3	1031	19
T4	1092	10
T5	381	2
T6	94807	17
T13	24242	120
T15	673	4
T16	3579	68
T17	36532	354

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2400605	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2400605
T1	379	6
T2	601	11
T3	1031	19
T4	1092	10
T5	381	2
T6	94807	3
T13	24242	147
T15	673	4
T16	3579	68
T17	36532	319

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1445924	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1445924
T1	379	6
T2	601	8
T3	1031	11
T4	1092	10
T5	381	2
T6	94807	32
T13	24242	140
T15	673	9
T16	3579	50
T17	36532	239

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2742146	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2742146
T1	379	6
T2	601	8
T3	1031	11
T4	1092	10
T5	381	2
T6	94807	8
T13	24242	167
T15	673	9
T16	3579	50
T17	36532	316

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1501771	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1501771
T1	379	4
T2	601	7
T3	1031	21
T4	1092	10
T5	381	3
T6	94807	35
T13	24242	219
T15	673	10
T16	3579	74
T17	36532	288

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2204969	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2204969
T1	379	4
T2	601	7
T3	1031	21
T4	1092	10
T5	381	3
T6	94807	9
T13	24242	198
T15	673	10
T16	3579	74
T17	36532	278

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1449305	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1449305
T1	379	4
T2	601	5
T3	1031	17
T4	1092	10
T5	381	4
T6	94807	22
T13	24242	117
T15	673	6
T16	3579	48
T17	36532	304

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3217774	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3217774
T1	379	4
T2	601	5
T3	1031	17
T4	1092	10
T5	381	4
T6	94807	6
T13	24242	150
T15	673	6
T16	3579	48
T17	36532	360

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1458983	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1458983
T1	379	2
T2	601	6
T3	1031	18
T4	1092	9
T5	381	4
T6	94807	15
T13	24242	251
T15	673	6
T16	3579	69
T17	36532	489

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2934326	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2934326
T1	379	2
T2	601	6
T3	1031	18
T4	1092	9
T5	381	4
T6	94807	4
T13	24242	322
T15	673	6
T16	3579	69
T17	36532	487

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1480840	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1480840
T1	379	5
T2	601	9
T3	1031	22
T4	1092	10
T5	381	4
T6	94807	33
T13	24242	152
T15	673	14
T16	3579	57
T17	36532	287

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2607156	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2607156
T1	379	5
T2	601	9
T3	1031	22
T4	1092	10
T5	381	4
T6	94807	6
T13	24242	134
T15	673	14
T16	3579	57
T17	36532	328

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1456159	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1456159
T1	379	6
T2	601	6
T3	1031	23
T4	1092	4
T5	381	2
T6	94807	29
T13	24242	136
T15	673	8
T16	3579	59
T17	36532	292

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2822233	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2822233
T1	379	6
T2	601	6
T3	1031	23
T4	1092	4
T5	381	2
T6	94807	17
T13	24242	115
T15	673	8
T16	3579	59
T17	36532	311

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1446295	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1446295
T1	379	3
T2	601	5
T3	1031	16
T4	1092	10
T5	381	6
T6	94807	25
T13	24242	142
T15	673	10
T16	3579	59
T17	36532	375

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3072133	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3072133
T1	379	3
T2	601	5
T3	1031	16
T4	1092	10
T5	381	6
T6	94807	5
T13	24242	187
T15	673	10
T16	3579	59
T17	36532	348

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1463369	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1463369
T1	379	10
T2	601	5
T3	1031	17
T4	1092	2
T5	381	6
T6	94807	24
T13	24242	187
T15	673	5
T16	3579	41
T17	36532	388

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2543959	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2543959
T1	379	10
T2	601	5
T3	1031	17
T4	1092	2
T5	381	6
T6	94807	984
T13	24242	169
T15	673	5
T16	3579	41
T17	36532	374

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1491596	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1491596
T1	379	10
T2	601	7
T3	1031	13
T4	1092	2
T5	381	3
T6	94807	21
T13	24242	102
T15	673	4
T16	3579	63
T17	36532	423

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	3270108	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	3270108
T1	379	10
T2	601	7
T3	1031	13
T4	1092	2
T5	381	3
T6	94807	5
T13	24242	127
T15	673	4
T16	3579	63
T17	36532	493

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1461449	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1461449
T1	379	7
T2	601	5
T3	1031	11
T4	1092	8
T5	381	3
T6	94807	54
T13	24242	168
T15	673	10
T16	3579	60
T17	36532	340

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2885642	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2885642
T1	379	7
T2	601	5
T3	1031	11
T4	1092	8
T5	381	3
T6	94807	11
T13	24242	141
T15	673	10
T16	3579	60
T17	36532	334

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	1512854	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	1512854
T1	379	7
T2	601	5
T3	1031	12
T4	1092	7
T5	381	3
T6	94807	22
T13	24242	117
T15	673	9
T16	3579	64
T17	36532	523

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	289296571	2718756	0	0
DepthKnown_A	289296571	289168523	0	0
RvalidKnown_A	289296571	289168523	0	0
WreadyKnown_A	289296571	289168523	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	289296571	2718756
T1	379	7
T2	601	5
T3	1031	12
T4	1092	7
T5	381	3
T6	94807	5
T13	24242	124
T15	673	9
T16	3579	64
T17	36532	532

DepthKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

RvalidKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

WreadyKnown_A

Name	Attempts	Real Successes
Total	289296571	289168523
T1	379	369
T2	601	564
T3	1031	1011
T4	1092	1063
T5	381	361
T6	94807	94791
T13	24242	24192
T15	673	627
T16	3579	3517
T17	36532	36490

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T13	1	1
T15	1	1
T16	1	1
T17	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children