Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1653860	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

260211

1

T1

21

T2

21

T3

90

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	647552	1			T1	38		T2	43		T3	256
values[0x0]	618495	1			T1	48		T2	42		T3	236
values[0x1]	648024	1			T1	29		T2	45		T3	268

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1281289	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632782

1

T1

43

T2

43

T3

254

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7285	1			T22	3		T17	6		T19	74
valid_sources[0x01]	7248	1			T3	1		T22	12		T23	1
valid_sources[0x02]	7162	1			T22	2		T23	2		T17	6
valid_sources[0x03]	8079	1			T3	4		T23	1		T17	6
valid_sources[0x04]	7028	1			T3	6		T23	1		T17	7
valid_sources[0x05]	8744	1			T1	1		T22	3		T23	1
valid_sources[0x06]	7467	1			T22	12		T23	1		T16	1
valid_sources[0x07]	7038	1			T3	4		T21	1		T23	1
valid_sources[0x08]	8392	1			T1	1		T3	3		T21	5
valid_sources[0x09]	7857	1			T22	3		T17	5		T28	9
valid_sources[0x0a]	7430	1			T22	8		T17	9		T25	1
valid_sources[0x0b]	7645	1			T1	1		T3	9		T22	3
valid_sources[0x0c]	7407	1			T1	1		T3	1		T4	7
valid_sources[0x0d]	7182	1			T1	1		T4	2		T22	1
valid_sources[0x0e]	7306	1			T17	2		T26	4		T28	11
valid_sources[0x0f]	7188	1			T22	5		T23	2		T17	5
valid_sources[0x10]	7558	1			T22	8		T16	1		T17	4
valid_sources[0x11]	6897	1			T4	1		T22	4		T17	4
valid_sources[0x12]	8558	1			T21	1		T22	5		T17	8
valid_sources[0x13]	7635	1			T1	1		T22	1		T17	4
valid_sources[0x14]	8590	1			T3	14		T21	2		T22	5
valid_sources[0x15]	7215	1			T21	3		T22	5		T24	1
valid_sources[0x16]	7835	1			T4	4		T22	3		T23	1
valid_sources[0x17]	7363	1			T1	4		T3	1		T21	1
valid_sources[0x18]	7609	1			T3	3		T21	1		T22	1
valid_sources[0x19]	7386	1			T22	2		T17	7		T19	23
valid_sources[0x1a]	7343	1			T3	7		T22	1		T28	6
valid_sources[0x1b]	6755	1			T3	6		T22	6		T23	2
valid_sources[0x1c]	8029	1			T3	1		T4	5		T22	12
valid_sources[0x1d]	7590	1			T3	9		T22	4		T17	2
valid_sources[0x1e]	8230	1			T3	2		T22	2		T23	2
valid_sources[0x1f]	6905	1			T3	13		T22	1		T23	2
valid_sources[0x20]	6865	1			T3	35		T22	7		T23	1
valid_sources[0x21]	7367	1			T3	11		T4	1		T22	5
valid_sources[0x22]	7123	1			T1	1		T22	4		T23	1
valid_sources[0x23]	7182	1			T23	1		T17	4		T25	1
valid_sources[0x24]	6960	1			T1	2		T3	2		T22	8
valid_sources[0x25]	7446	1			T3	2		T22	2		T23	1
valid_sources[0x26]	6916	1			T1	1		T22	6		T17	4
valid_sources[0x27]	7382	1			T21	2		T22	1		T17	6
valid_sources[0x28]	6661	1			T3	16		T24	8		T17	3
valid_sources[0x29]	7135	1			T17	5		T26	4		T20	1
valid_sources[0x2a]	7107	1			T22	2		T23	1		T17	3
valid_sources[0x2b]	7772	1			T1	3		T22	9		T24	1
valid_sources[0x2c]	7139	1			T3	2		T22	5		T24	1
valid_sources[0x2d]	7198	1			T21	1		T22	4		T17	4
valid_sources[0x2e]	6977	1			T22	4		T17	3		T25	1
valid_sources[0x2f]	7371	1			T22	5		T23	1		T24	1
valid_sources[0x30]	6796	1			T3	2		T24	3		T17	2
valid_sources[0x31]	7033	1			T3	13		T4	3		T22	5
valid_sources[0x32]	7014	1			T3	6		T23	1		T16	1
valid_sources[0x33]	7809	1			T3	26		T22	12		T24	1
valid_sources[0x34]	7241	1			T3	8		T21	1		T22	6
valid_sources[0x35]	7105	1			T1	4		T22	11		T23	1
valid_sources[0x36]	7255	1			T3	11		T24	1		T17	11
valid_sources[0x37]	8174	1			T4	1		T22	3		T23	1
valid_sources[0x38]	7661	1			T1	1		T3	8		T4	2
valid_sources[0x39]	7457	1			T22	1		T17	2		T26	2
valid_sources[0x3a]	6801	1			T3	3		T21	1		T24	4
valid_sources[0x3b]	7858	1			T1	1		T3	8		T17	9
valid_sources[0x3c]	9380	1			T22	1		T17	6		T28	8
valid_sources[0x3d]	7669	1			T1	2		T3	3		T22	10
valid_sources[0x3e]	7117	1			T1	1		T4	2		T21	2
valid_sources[0x3f]	8035	1			T22	1		T23	2		T16	1
valid_sources[0x40]	8134	1			T3	5		T22	5		T23	1
valid_sources[0x41]	7540	1			T16	1		T17	2		T27	99
valid_sources[0x42]	7781	1			T1	1		T3	3		T22	2
valid_sources[0x43]	6938	1			T1	2		T4	4		T22	3
valid_sources[0x44]	8888	1			T4	14		T22	2		T24	1
valid_sources[0x45]	6747	1			T3	4		T22	1		T23	1
valid_sources[0x46]	7193	1			T1	1		T3	12		T22	5
valid_sources[0x47]	8398	1			T3	5		T22	4		T17	6
valid_sources[0x48]	7637	1			T3	8		T4	4		T21	3
valid_sources[0x49]	7894	1			T23	1		T17	2		T19	3
valid_sources[0x4a]	6637	1			T23	1		T17	7		T28	19
valid_sources[0x4b]	7090	1			T4	1		T22	9		T17	4
valid_sources[0x4c]	7412	1			T24	2		T17	8		T26	5
valid_sources[0x4d]	7421	1			T1	1		T3	4		T22	6
valid_sources[0x4e]	6741	1			T3	13		T23	1		T28	9
valid_sources[0x4f]	7412	1			T24	1		T17	7		T28	10
valid_sources[0x50]	6599	1			T3	3		T22	2		T16	1
valid_sources[0x51]	6933	1			T3	20		T21	3		T17	7
valid_sources[0x52]	8101	1			T22	4		T17	5		T28	10
valid_sources[0x53]	7222	1			T3	3		T22	4		T24	1
valid_sources[0x54]	7624	1			T1	1		T3	10		T22	7
valid_sources[0x55]	7038	1			T4	1		T22	1		T16	1
valid_sources[0x56]	7640	1			T3	4		T23	1		T17	9
valid_sources[0x57]	6800	1			T1	1		T3	5		T22	1
valid_sources[0x58]	7493	1			T1	2		T22	2		T17	8
valid_sources[0x59]	7457	1			T1	1		T3	1		T22	1
valid_sources[0x5a]	8247	1			T17	3		T25	1		T27	78
valid_sources[0x5b]	7702	1			T22	3		T24	1		T17	7
valid_sources[0x5c]	7958	1			T4	1		T22	9		T23	2
valid_sources[0x5d]	7229	1			T22	18		T23	1		T17	6
valid_sources[0x5e]	7220	1			T3	3		T22	1		T17	7
valid_sources[0x5f]	7420	1			T21	2		T22	3		T17	3
valid_sources[0x60]	7322	1			T22	3		T23	1		T17	2
valid_sources[0x61]	6828	1			T22	1		T17	9		T20	1
valid_sources[0x62]	7613	1			T2	22		T22	4		T17	3
valid_sources[0x63]	7334	1			T1	2		T3	5		T21	4
valid_sources[0x64]	7026	1			T3	1		T21	2		T22	3
valid_sources[0x65]	7703	1			T3	4		T21	2		T17	2
valid_sources[0x66]	6963	1			T3	4		T22	4		T23	1
valid_sources[0x67]	7073	1			T4	3		T22	8		T17	5
valid_sources[0x68]	6587	1			T4	6		T22	3		T17	6
valid_sources[0x69]	8092	1			T3	2		T21	2		T24	3
valid_sources[0x6a]	6858	1			T22	5		T16	1		T17	3
valid_sources[0x6b]	7849	1			T3	6		T22	4		T17	1
valid_sources[0x6c]	8193	1			T1	1		T17	6		T20	1
valid_sources[0x6d]	7438	1			T3	9		T22	6		T23	1
valid_sources[0x6e]	6847	1			T3	2		T22	5		T24	2
valid_sources[0x6f]	7888	1			T1	1		T2	27		T3	22
valid_sources[0x70]	8039	1			T3	1		T17	3		T25	1
valid_sources[0x71]	8232	1			T21	6		T16	1		T17	5
valid_sources[0x72]	7870	1			T1	1		T3	1		T22	8
valid_sources[0x73]	7448	1			T1	3		T3	3		T22	4
valid_sources[0x74]	7807	1			T1	1		T3	2		T4	11
valid_sources[0x75]	6886	1			T3	2		T4	1		T22	5
valid_sources[0x76]	8121	1			T22	6		T23	1		T16	1
valid_sources[0x77]	8923	1			T1	1		T3	4		T21	3
valid_sources[0x78]	8332	1			T1	5		T22	6		T17	2
valid_sources[0x79]	7411	1			T1	1		T3	6		T4	1
valid_sources[0x7a]	7878	1			T3	1		T23	1		T16	2
valid_sources[0x7b]	6820	1			T4	10		T22	6		T17	10
valid_sources[0x7c]	7240	1			T22	6		T23	1		T17	8
valid_sources[0x7d]	8289	1			T3	3		T23	1		T17	1
valid_sources[0x7e]	7520	1			T3	12		T22	2		T17	3
valid_sources[0x7f]	7045	1			T3	4		T22	6		T17	4
valid_sources[0x80]	6764	1			T22	5		T16	2		T24	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27558

1

T1

3

T2

1

T3

10

values[0x0]

all_enables

biggest_size

204863

1

T1

17

T2

17

T3

68

values[0x1]

all_enables

biggest_size

27790

1

T1

1

T2

3

T3

12