Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	366245487	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	366245487
T1	40392	570
T2	200872	3645
T3	1101968	20914
T4	3802400	68075
T16	115976	4954
T17	159712	6133
T18	33616	5144
T21	29624	552
T22	65632	3540
T23	174888	3115
T24	10882648	199114
T25	0	24

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	41888	37576
T2	200872	199192
T3	1101968	1099896
T4	3802400	3798368
T16	115976	115304
T17	159712	156520
T21	29624	27944
T22	65632	63784
T23	174888	171864
T24	10882648	10881976

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	41888	37576
T2	200872	199192
T3	1101968	1099896
T4	3802400	3798368
T16	115976	115304
T17	159712	156520
T21	29624	27944
T22	65632	63784
T23	174888	171864
T24	10882648	10881976

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	41888	37576
T2	200872	199192
T3	1101968	1099896
T4	3802400	3798368
T16	115976	115304
T17	159712	156520
T21	29624	27944
T22	65632	63784
T23	174888	171864
T24	10882648	10881976

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T16	56	56
T17	56	56
T21	56	56
T22	56	56
T23	56	56
T24	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	127294265	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	127294265
T1	748	225
T2	3587	1612
T3	19678	9262
T4	67900	65829
T16	2071	1933
T17	2852	2389
T21	529	213
T22	1172	885
T23	3123	1454
T24	194333	89657

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	98488260	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	98488260
T1	748	115
T2	3587	449
T3	19678	2787
T4	67900	840
T16	2071	1007
T17	2852	1248
T21	529	113
T22	1172	885
T23	3123	374
T24	194333	24214

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1572605	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1572605
T1	748	5
T2	3587	24
T3	19678	199
T4	67900	46
T16	2071	34
T17	2852	59
T18	0	44
T21	529	4
T22	1172	0
T23	3123	7
T24	194333	1839

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	4099330	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	4099330
T1	748	5
T2	3587	10
T3	19678	125
T4	67900	9
T16	2071	34
T17	2852	59
T18	0	78
T21	529	4
T22	1172	0
T23	3123	2
T24	194333	283

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1642155	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1642155
T1	748	6
T2	3587	16
T3	19678	269
T4	67900	5
T16	2071	35
T17	2852	37
T21	529	2
T22	1172	208
T23	3123	16
T24	194333	2810

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3568598	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3568598
T1	748	6
T2	3587	1
T3	19678	106
T4	67900	1
T16	2071	35
T17	2852	37
T21	529	2
T22	1172	208
T23	3123	1
T24	194333	2050

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1613350	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1613350
T1	748	2
T2	3587	37
T3	19678	320
T4	67900	34
T16	2071	38
T17	2852	47
T21	529	5
T22	1172	208
T23	3123	6
T24	194333	2575

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	4234521	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	4234521
T1	748	2
T2	3587	28
T3	19678	131
T4	67900	7
T16	2071	38
T17	2852	47
T21	529	5
T22	1172	208
T23	3123	1
T24	194333	1622

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1613860	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1613860
T1	748	6
T2	3587	9
T3	19678	265
T4	67900	30
T16	2071	39
T17	2852	35
T18	0	167
T21	529	0
T22	1172	0
T23	3123	42
T24	194333	2725
T25	0	8

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3759292	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3759292
T1	748	6
T2	3587	4
T3	19678	121
T4	67900	7
T16	2071	39
T17	2852	35
T18	0	119
T21	529	0
T22	1172	0
T23	3123	10
T24	194333	1137
T25	0	1

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1564238	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1564238
T1	748	1
T2	3587	86
T3	19678	197
T4	67900	17
T16	2071	38
T17	2852	45
T18	0	133
T21	529	3
T22	1172	0
T23	3123	7
T24	194333	131

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3483590	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3483590
T1	748	1
T2	3587	28
T3	19678	96
T4	67900	3
T16	2071	38
T17	2852	45
T18	0	133
T21	529	3
T22	1172	0
T23	3123	3
T24	194333	268

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1590060	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1590060
T1	748	6
T2	3587	23
T3	19678	299
T4	67900	23
T16	2071	29
T17	2852	51
T18	0	153
T21	529	3
T22	1172	0
T23	3123	13
T24	194333	3160

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3553174	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3553174
T1	748	6
T2	3587	18
T3	19678	81
T4	67900	7
T16	2071	29
T17	2852	51
T18	0	124
T21	529	3
T22	1172	0
T23	3123	7
T24	194333	354

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1583428	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1583428
T1	748	3
T2	3587	69
T3	19678	201
T4	67900	22
T16	2071	54
T17	2852	50
T18	0	78
T21	529	6
T22	1172	0
T23	3123	45
T24	194333	1830

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3271913	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3271913
T1	748	3
T2	3587	17
T3	19678	138
T4	67900	4
T16	2071	54
T17	2852	50
T18	0	92
T21	529	6
T22	1172	0
T23	3123	25
T24	194333	516

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1572861	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1572861
T1	748	5
T2	3587	48
T3	19678	231
T4	67900	11
T16	2071	32
T17	2852	47
T18	0	68
T21	529	6
T22	1172	0
T23	3123	38
T24	194333	2100

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	4279617	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	4279617
T1	748	5
T2	3587	20
T3	19678	119
T4	67900	4
T16	2071	32
T17	2852	47
T18	0	79
T21	529	6
T22	1172	0
T23	3123	16
T24	194333	674

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1557608	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1557608
T1	748	5
T2	3587	38
T3	19678	182
T4	67900	23
T16	2071	32
T17	2852	46
T18	0	110
T21	529	3
T22	1172	0
T23	3123	7
T24	194333	1592

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	4406831	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	4406831
T1	748	5
T2	3587	21
T3	19678	81
T4	67900	6
T16	2071	32
T17	2852	46
T18	0	142
T21	529	3
T22	1172	0
T23	3123	2
T24	194333	1019

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1557409	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1557409
T1	748	6
T2	3587	62
T3	19678	203
T4	67900	8
T16	2071	44
T17	2852	45
T18	0	142
T21	529	6
T22	1172	0
T23	3123	38
T24	194333	1769

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3348071	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3348071
T1	748	6
T2	3587	32
T3	19678	82
T4	67900	2
T16	2071	44
T17	2852	45
T18	0	160
T21	529	6
T22	1172	0
T23	3123	8
T24	194333	898

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1581924	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1581924
T1	748	1
T2	3587	19
T3	19678	334
T4	67900	21
T16	2071	34
T17	2852	56
T18	0	84
T21	529	6
T22	1172	0
T23	3123	13
T24	194333	2443

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3784145	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3784145
T1	748	1
T2	3587	12
T3	19678	119
T4	67900	7
T16	2071	34
T17	2852	56
T18	0	104
T21	529	6
T22	1172	0
T23	3123	6
T24	194333	1433

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1580067	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1580067
T1	748	3
T2	3587	51
T3	19678	141
T4	67900	13
T16	2071	26
T17	2852	44
T18	0	148
T21	529	8
T22	1172	0
T23	3123	37
T24	194333	2233

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3512009	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3512009
T1	748	3
T2	3587	6
T3	19678	50
T4	67900	5
T16	2071	26
T17	2852	44
T18	0	145
T21	529	8
T22	1172	0
T23	3123	9
T24	194333	1041

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1535770	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1535770
T1	748	3
T2	3587	48
T3	19678	164
T4	67900	24
T16	2071	46
T17	2852	52
T18	0	53
T21	529	5
T22	1172	0
T23	3123	115
T24	194333	3928

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	2858468	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	2858468
T1	748	3
T2	3587	29
T3	19678	53
T4	67900	5
T16	2071	46
T17	2852	52
T18	0	45
T21	529	5
T22	1172	0
T23	3123	30
T24	194333	913

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1614278	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1614278
T1	748	6
T2	3587	44
T3	19678	221
T4	67900	24
T16	2071	38
T17	2852	49
T18	0	67
T21	529	2
T22	1172	0
T23	3123	14
T24	194333	2396

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3931121	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3931121
T1	748	6
T2	3587	19
T3	19678	79
T4	67900	5
T16	2071	38
T17	2852	49
T18	0	54
T21	529	2
T22	1172	0
T23	3123	2
T24	194333	317

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1609955	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1609955
T1	748	3
T2	3587	1
T3	19678	267
T4	67900	28
T16	2071	35
T17	2852	49
T18	0	136
T21	529	2
T22	1172	0
T23	3123	27
T24	194333	1698

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3713911	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3713911
T1	748	3
T2	3587	1
T3	19678	101
T4	67900	5
T16	2071	35
T17	2852	49
T18	0	143
T21	529	2
T22	1172	0
T23	3123	27
T24	194333	260

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1553873	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1553873
T1	748	4
T2	3587	29
T3	19678	255
T4	67900	20
T16	2071	44
T17	2852	43
T18	0	144
T21	529	5
T22	1172	0
T23	3123	60
T24	194333	2531

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3578380	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3578380
T1	748	4
T2	3587	24
T3	19678	103
T4	67900	4
T16	2071	44
T17	2852	43
T18	0	111
T21	529	5
T22	1172	0
T23	3123	10
T24	194333	1048

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1555155	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1555155
T1	748	5
T2	3587	15
T3	19678	188
T4	67900	19
T16	2071	45
T17	2852	48
T21	529	3
T22	1172	239
T23	3123	20
T24	194333	2825

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3902473	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3902473
T1	748	5
T2	3587	4
T3	19678	104
T4	67900	3
T16	2071	45
T17	2852	48
T21	529	3
T22	1172	239
T23	3123	19
T24	194333	1655

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1604060	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1604060
T1	748	7
T2	3587	47
T3	19678	168
T4	67900	11
T16	2071	32
T17	2852	54
T18	0	197
T21	529	9
T22	1172	0
T23	3123	46
T24	194333	2666

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	2944289	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	2944289
T1	748	7
T2	3587	27
T3	19678	81
T4	67900	710
T16	2071	32
T17	2852	54
T18	0	177
T21	529	9
T22	1172	0
T23	3123	39
T24	194333	1615

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1599321	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1599321
T1	748	9
T2	3587	68
T3	19678	252
T4	67900	20
T16	2071	38
T17	2852	38
T18	0	77
T21	529	5
T22	1172	0
T23	3123	49
T24	194333	1853

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3814823	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3814823
T1	748	9
T2	3587	18
T3	19678	123
T4	67900	3
T16	2071	38
T17	2852	38
T18	0	83
T21	529	5
T22	1172	0
T23	3123	11
T24	194333	354

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1621887	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1621887
T1	748	2
T2	3587	15
T3	19678	254
T4	67900	21
T16	2071	39
T17	2852	46
T21	529	6
T22	1172	230
T23	3123	32
T24	194333	729

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3569406	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3569406
T1	748	2
T2	3587	15
T3	19678	166
T4	67900	3
T16	2071	39
T17	2852	46
T21	529	6
T22	1172	230
T23	3123	32
T24	194333	4

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1566373	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1566373
T1	748	4
T2	3587	64
T3	19678	209
T4	67900	13
T16	2071	39
T17	2852	41
T18	0	77
T21	529	4
T22	1172	0
T23	3123	59
T24	194333	2906

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3105462	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3105462
T1	748	4
T2	3587	19
T3	19678	110
T4	67900	4
T16	2071	39
T17	2852	41
T18	0	88
T21	529	4
T22	1172	0
T23	3123	16
T24	194333	1811

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1553186	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1553186
T1	748	3
T2	3587	78
T3	19678	171
T4	67900	25
T16	2071	30
T17	2852	58
T18	0	119
T21	529	6
T22	1172	0
T23	3123	79
T24	194333	920

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	4020595	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	4020595
T1	748	3
T2	3587	16
T3	19678	95
T4	67900	6
T16	2071	30
T17	2852	58
T18	0	143
T21	529	6
T22	1172	0
T23	3123	11
T24	194333	475

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1633084	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1633084
T1	748	5
T2	3587	55
T3	19678	342
T4	67900	31
T16	2071	38
T17	2852	36
T18	0	122
T21	529	4
T22	1172	0
T23	3123	11
T24	194333	2800

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3212004	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3212004
T1	748	5
T2	3587	26
T3	19678	136
T4	67900	7
T16	2071	38
T17	2852	36
T18	0	111
T21	529	4
T22	1172	0
T23	3123	4
T24	194333	854

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1594283	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1594283
T1	748	5
T2	3587	23
T3	19678	160
T4	67900	23
T16	2071	39
T17	2852	35
T18	0	178
T21	529	2
T22	1172	0
T23	3123	11
T24	194333	2675

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3720456	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3720456
T1	748	5
T2	3587	22
T3	19678	107
T4	67900	6
T16	2071	39
T17	2852	35
T18	0	123
T21	529	2
T22	1172	0
T23	3123	8
T24	194333	1103

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1591524	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1591524
T1	748	5
T2	3587	98
T3	19678	256
T4	67900	4
T16	2071	32
T17	2852	46
T18	0	62
T21	529	2
T22	1172	0
T23	3123	44
T24	194333	843

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3602104	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3602104
T1	748	5
T2	3587	17
T3	19678	121
T4	67900	3
T16	2071	32
T17	2852	46
T18	0	70
T21	529	2
T22	1172	0
T23	3123	21
T24	194333	526

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1584517	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1584517
T2	3587	37
T3	19678	176
T4	67900	17
T16	2071	37
T17	2852	45
T18	16808	126
T21	529	2
T22	1172	0
T23	3123	57
T24	194333	4161
T25	0	11

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3033386	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3033386
T2	3587	8
T3	19678	84
T4	67900	5
T16	2071	37
T17	2852	45
T18	16808	123
T21	529	2
T22	1172	0
T23	3123	28
T24	194333	1552
T25	0	4

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	1598023	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	1598023
T1	748	5
T2	3587	31
T3	19678	154
T4	67900	33
T16	2071	40
T17	2852	46
T18	0	99
T21	529	4
T22	1172	0
T23	3123	20
T24	194333	2891

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	336559648	3310139	0	0
DepthKnown_A	336559648	336430810	0	0
RvalidKnown_A	336559648	336430810	0	0
WreadyKnown_A	336559648	336430810	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	336559648	3310139
T1	748	5
T2	3587	7
T3	19678	75
T4	67900	9
T16	2071	40
T17	2852	46
T18	0	113
T21	529	4
T22	1172	0
T23	3123	26
T24	194333	432

DepthKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

RvalidKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

WreadyKnown_A

Name	Attempts	Real Successes
Total	336559648	336430810
T1	748	671
T2	3587	3557
T3	19678	19641
T4	67900	67828
T16	2071	2059
T17	2852	2795
T21	529	499
T22	1172	1139
T23	3123	3069
T24	194333	194321

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T22	1	1
T23	1	1
T24	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children