Module Definition
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Module Instance : tb.dut.u_s1n_28.gen_err_resp.err_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.49 100.00 93.97 100.00 100.00 u_s1n_28


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
TOTAL2121100.00
ALWAYS341414100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6511100.00

33 always_ff @(posedge clk_i or negedge rst_ni) begin 34 1/1 if (!rst_ni) begin Tests: T1 T2 T3  35 1/1 err_rsp_pending <= 1'b0; Tests: T1 T2 T3  36 1/1 err_source <= {top_pkg::TL_AIW{1'b0}}; Tests: T1 T2 T3  37 1/1 err_opcode <= Get; Tests: T1 T2 T3  38 1/1 err_size <= '0; Tests: T1 T2 T3  39 1/1 err_instr_type <= MuBi4False; Tests: T1 T2 T3  40 1/1 end else if (err_rsp_pending && tl_h_i.d_ready) begin Tests: T1 T2 T3  41 1/1 err_rsp_pending <= 1'b0; Tests: T18 T19 T20  42 1/1 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin Tests: T1 T2 T3  43 1/1 err_rsp_pending <= 1'b1; Tests: T18 T19 T20  44 1/1 err_source <= tl_h_i.a_source; Tests: T18 T19 T20  45 1/1 err_opcode <= tl_h_i.a_opcode; Tests: T18 T19 T20  46 1/1 err_size <= tl_h_i.a_size; Tests: T18 T19 T20  47 1/1 err_instr_type <= tl_h_i.a_user.instr_type; Tests: T18 T19 T20  48 end MISSING_ELSE 49 end 50 51 1/1 assign tl_h_o_int.a_ready = ~err_rsp_pending; Tests: T1 T2 T3  52 1/1 assign tl_h_o_int.d_valid = err_rsp_pending; Tests: T1 T2 T3  53 1/1 assign tl_h_o_int.d_data = (mubi4_test_true_strict(err_instr_type)) ? DataWhenInstrError : Tests: T1 T2 T3  54 DataWhenError; 55 1/1 assign tl_h_o_int.d_source = err_source; Tests: T1 T2 T3  56 assign tl_h_o_int.d_sink = '0; 57 assign tl_h_o_int.d_param = '0; 58 1/1 assign tl_h_o_int.d_size = err_size; Tests: T1 T2 T3  59 1/1 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck; Tests: T1 T2 T3  60 assign tl_h_o_int.d_user = '0; 61 assign tl_h_o_int.d_error = 1'b1; 62 63 // Waive unused bits of tl_h_i 64 logic unused_tl_h; 65 1/1 assign unused_tl_h = ^tl_h_i; Tests: T1 T2 T3 

Cond Coverage for Module : tlul_err_resp
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T31
11CoveredT18,T19,T20

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT18,T20,T70
11CoveredT18,T19,T20

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0CoveredT18,T19,T20
1CoveredT1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 59 2 2 100.00
IF 34 4 4 100.00


59 assign tl_h_o_int.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T18,T19,T20


34 if (!rst_ni) begin -1- 35 err_rsp_pending <= 1'b0; ==> 36 err_source <= {top_pkg::TL_AIW{1'b0}}; 37 err_opcode <= Get; 38 err_size <= '0; 39 err_instr_type <= MuBi4False; 40 end else if (err_rsp_pending && tl_h_i.d_ready) begin -2- 41 err_rsp_pending <= 1'b0; ==> 42 end else if (tl_h_i.a_valid && tl_h_o_int.a_ready) begin -3- 43 err_rsp_pending <= 1'b1; ==> 44 err_source <= tl_h_i.a_source; 45 err_opcode <= tl_h_i.a_opcode; 46 err_size <= tl_h_i.a_size; 47 err_instr_type <= tl_h_i.a_user.instr_type; 48 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T18,T19,T20
0 0 1 Covered T18,T19,T20
0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%