Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1793384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

282330

1

T1

203

T2

21

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	701608	1			T1	481		T2	51		T3	42
values[0x0]	673143	1			T1	481		T2	57		T3	36
values[0x1]	700963	1			T1	477		T2	59		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1390358	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

685356

1

T1

489

T2

52

T3

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8454	1			T1	4		T20	6		T17	1
valid_sources[0x01]	7739	1			T1	8		T2	2		T19	1
valid_sources[0x02]	8627	1			T1	2		T3	14		T19	1
valid_sources[0x03]	8442	1			T1	4		T2	1		T4	3
valid_sources[0x04]	8755	1			T1	4		T3	4		T20	3
valid_sources[0x05]	8712	1			T1	5		T4	4		T16	3
valid_sources[0x06]	8659	1			T1	8		T20	7		T17	2
valid_sources[0x07]	7779	1			T1	1		T3	3		T20	3
valid_sources[0x08]	7665	1			T1	7		T2	1		T19	2
valid_sources[0x09]	7703	1			T1	13		T20	3		T24	1
valid_sources[0x0a]	8524	1			T1	8		T19	1		T20	3
valid_sources[0x0b]	8021	1			T1	6		T20	6		T17	13
valid_sources[0x0c]	7448	1			T1	3		T19	1		T20	5
valid_sources[0x0d]	8054	1			T1	7		T3	3		T4	1
valid_sources[0x0e]	7793	1			T1	5		T4	1		T20	1
valid_sources[0x0f]	8034	1			T1	6		T20	1		T21	1
valid_sources[0x10]	7749	1			T1	5		T20	4		T43	1
valid_sources[0x11]	8178	1			T1	5		T14	32		T20	3
valid_sources[0x12]	7902	1			T1	5		T20	3		T17	1
valid_sources[0x13]	8167	1			T1	4		T2	1		T20	4
valid_sources[0x14]	8088	1			T1	5		T2	3		T19	1
valid_sources[0x15]	8298	1			T1	8		T3	5		T19	1
valid_sources[0x16]	7571	1			T1	5		T20	2		T21	1
valid_sources[0x17]	7585	1			T1	5		T19	1		T16	9
valid_sources[0x18]	8867	1			T1	5		T20	4		T46	12
valid_sources[0x19]	7769	1			T1	4		T20	3		T21	2
valid_sources[0x1a]	7812	1			T1	3		T20	4		T43	7
valid_sources[0x1b]	8464	1			T1	9		T2	2		T20	2
valid_sources[0x1c]	8314	1			T1	6		T2	5		T19	1
valid_sources[0x1d]	7912	1			T1	2		T4	1		T20	4
valid_sources[0x1e]	7471	1			T1	1		T19	1		T20	1
valid_sources[0x1f]	8778	1			T1	7		T19	2		T4	1
valid_sources[0x20]	8205	1			T1	3		T19	4		T20	5
valid_sources[0x21]	9483	1			T1	11		T2	6		T20	4
valid_sources[0x22]	8099	1			T1	8		T4	1		T21	2
valid_sources[0x23]	8555	1			T1	6		T4	2		T20	4
valid_sources[0x24]	7786	1			T1	7		T2	2		T19	2
valid_sources[0x25]	7767	1			T1	6		T19	1		T20	6
valid_sources[0x26]	8104	1			T1	11		T4	2		T20	2
valid_sources[0x27]	7735	1			T1	10		T4	4		T14	16
valid_sources[0x28]	7726	1			T1	7		T20	1		T21	1
valid_sources[0x29]	8455	1			T1	9		T19	1		T4	1
valid_sources[0x2a]	7621	1			T1	3		T2	3		T4	1
valid_sources[0x2b]	9107	1			T1	7		T3	2		T4	2
valid_sources[0x2c]	8058	1			T1	5		T19	2		T20	3
valid_sources[0x2d]	7922	1			T1	5		T19	1		T4	5
valid_sources[0x2e]	7909	1			T1	1		T2	1		T20	2
valid_sources[0x2f]	8278	1			T1	9		T20	4		T21	1
valid_sources[0x30]	7974	1			T1	3		T19	1		T4	2
valid_sources[0x31]	8243	1			T1	7		T19	2		T4	1
valid_sources[0x32]	8443	1			T1	4		T3	1		T20	1
valid_sources[0x33]	8273	1			T1	3		T20	4		T21	1
valid_sources[0x34]	7724	1			T1	7		T2	2		T16	6
valid_sources[0x35]	7468	1			T1	6		T2	2		T20	1
valid_sources[0x36]	8481	1			T1	3		T20	4		T46	9
valid_sources[0x37]	8206	1			T1	6		T20	2		T17	12
valid_sources[0x38]	7747	1			T1	2		T20	2		T17	2
valid_sources[0x39]	8102	1			T1	9		T3	1		T4	3
valid_sources[0x3a]	8299	1			T1	5		T2	1		T15	52
valid_sources[0x3b]	7527	1			T1	4		T17	6		T46	13
valid_sources[0x3c]	7654	1			T1	7		T2	4		T3	1
valid_sources[0x3d]	7885	1			T1	6		T2	1		T3	7
valid_sources[0x3e]	8752	1			T1	9		T2	2		T4	5
valid_sources[0x3f]	8577	1			T1	7		T20	5		T23	6
valid_sources[0x40]	7614	1			T1	5		T20	6		T17	5
valid_sources[0x41]	8747	1			T1	6		T4	1		T20	3
valid_sources[0x42]	7880	1			T1	5		T16	2		T20	4
valid_sources[0x43]	8222	1			T1	2		T3	4		T19	1
valid_sources[0x44]	7609	1			T1	7		T2	3		T15	68
valid_sources[0x45]	7834	1			T1	2		T20	1		T17	5
valid_sources[0x46]	8253	1			T1	9		T20	2		T17	6
valid_sources[0x47]	7520	1			T1	4		T4	1		T20	3
valid_sources[0x48]	8271	1			T1	4		T4	1		T20	7
valid_sources[0x49]	8614	1			T1	5		T4	4		T20	2
valid_sources[0x4a]	9121	1			T1	3		T2	1		T20	1
valid_sources[0x4b]	8679	1			T1	5		T16	4		T20	1
valid_sources[0x4c]	8050	1			T1	12		T20	2		T21	2
valid_sources[0x4d]	7483	1			T1	8		T2	1		T20	2
valid_sources[0x4e]	7613	1			T1	9		T14	10		T20	5
valid_sources[0x4f]	8205	1			T1	5		T20	1		T43	1
valid_sources[0x50]	7822	1			T1	3		T3	8		T20	1
valid_sources[0x51]	7899	1			T1	5		T19	1		T4	1
valid_sources[0x52]	7572	1			T1	7		T19	1		T20	1
valid_sources[0x53]	7725	1			T1	4		T2	6		T15	58
valid_sources[0x54]	9549	1			T1	8		T19	2		T20	5
valid_sources[0x55]	8263	1			T1	5		T19	2		T20	3
valid_sources[0x56]	7573	1			T1	4		T4	1		T20	3
valid_sources[0x57]	9161	1			T1	6		T20	5		T17	2
valid_sources[0x58]	7886	1			T1	5		T20	1		T46	6
valid_sources[0x59]	7762	1			T1	4		T20	4		T23	2
valid_sources[0x5a]	7935	1			T1	3		T20	4		T21	1
valid_sources[0x5b]	8585	1			T1	4		T2	2		T19	1
valid_sources[0x5c]	7970	1			T1	9		T4	2		T20	2
valid_sources[0x5d]	8734	1			T1	3		T20	3		T17	44
valid_sources[0x5e]	7992	1			T1	5		T19	1		T20	1
valid_sources[0x5f]	8285	1			T1	4		T2	3		T19	1
valid_sources[0x60]	8789	1			T1	4		T20	2		T21	1
valid_sources[0x61]	7799	1			T1	7		T2	1		T19	1
valid_sources[0x62]	9171	1			T1	4		T19	1		T20	2
valid_sources[0x63]	7736	1			T1	12		T2	1		T20	5
valid_sources[0x64]	8041	1			T1	2		T19	1		T20	3
valid_sources[0x65]	7899	1			T1	4		T4	1		T20	3
valid_sources[0x66]	7759	1			T1	7		T20	3		T22	5
valid_sources[0x67]	7415	1			T1	2		T2	5		T14	9
valid_sources[0x68]	8142	1			T1	4		T19	1		T16	1
valid_sources[0x69]	7260	1			T1	4		T2	1		T20	2
valid_sources[0x6a]	8031	1			T1	7		T4	2		T20	1
valid_sources[0x6b]	8240	1			T1	6		T2	1		T20	4
valid_sources[0x6c]	9607	1			T1	1		T20	3		T24	1
valid_sources[0x6d]	7849	1			T1	9		T2	2		T20	7
valid_sources[0x6e]	8049	1			T1	13		T19	1		T20	8
valid_sources[0x6f]	7609	1			T1	5		T19	1		T20	5
valid_sources[0x70]	8051	1			T1	8		T20	6		T21	2
valid_sources[0x71]	7659	1			T1	5		T2	11		T4	1
valid_sources[0x72]	9234	1			T1	6		T2	2		T19	2
valid_sources[0x73]	8616	1			T1	5		T4	1		T20	3
valid_sources[0x74]	8017	1			T1	9		T2	1		T19	2
valid_sources[0x75]	7996	1			T1	6		T3	3		T4	1
valid_sources[0x76]	7578	1			T1	6		T2	4		T20	3
valid_sources[0x77]	8415	1			T1	9		T17	4		T24	1
valid_sources[0x78]	7835	1			T1	4		T20	3		T17	2
valid_sources[0x79]	7261	1			T1	7		T20	7		T46	14
valid_sources[0x7a]	8108	1			T1	5		T20	3		T46	10
valid_sources[0x7b]	8412	1			T1	7		T2	3		T20	7
valid_sources[0x7c]	7409	1			T1	5		T19	2		T20	4
valid_sources[0x7d]	7988	1			T1	2		T20	4		T17	10
valid_sources[0x7e]	7391	1			T1	9		T2	2		T4	1
valid_sources[0x7f]	8412	1			T1	5		T2	1		T4	2
valid_sources[0x80]	8046	1			T1	3		T20	5		T17	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29615

1

T1

16

T2

1

T3

1

values[0x0]

all_enables

biggest_size

223398

1

T1

163

T2

18

T3

11

values[0x1]

all_enables

biggest_size

29317

1

T1

24

T2

2

T3

1