Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	348847684	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	348847684	0	0
T1	1811376	37625	0	0
T2	25032	817	0	0
T3	18088	555	0	0
T4	280112	6206	0	0
T14	41664	1046	0	0
T15	177576	6906	0	0
T16	152040	5081	0	0
T19	32648	497	0	0
T20	106400	4169	0	0
T21	149912	5917	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1811376	1810088	0	0
T2	25032	24360	0	0
T3	18088	17304	0	0
T4	280112	277872	0	0
T14	41664	39984	0	0
T15	177576	174160	0	0
T16	152040	150920	0	0
T19	32648	29008	0	0
T20	106400	104328	0	0
T21	149912	147672	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1811376	1810088	0	0
T2	25032	24360	0	0
T3	18088	17304	0	0
T4	280112	277872	0	0
T14	41664	39984	0	0
T15	177576	174160	0	0
T16	152040	150920	0	0
T19	32648	29008	0	0
T20	106400	104328	0	0
T21	149912	147672	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1811376	1810088	0	0
T2	25032	24360	0	0
T3	18088	17304	0	0
T4	280112	277872	0	0
T14	41664	39984	0	0
T15	177576	174160	0	0
T16	152040	150920	0	0
T19	32648	29008	0	0
T20	106400	104328	0	0
T21	149912	147672	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T14	56	56	0	0
T15	56	56	0	0
T16	56	56	0	0
T19	56	56	0	0
T20	56	56	0	0
T21	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	126920619	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	126920619	0	0
T1	32346	17183	0	0
T2	447	316	0	0
T3	323	213	0	0
T4	5002	2534	0	0
T14	744	262	0	0
T15	3171	2682	0	0
T16	2715	2539	0	0
T19	583	191	0	0
T20	1900	1624	0	0
T21	2677	2302	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	90544364	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	90544364	0	0
T1	32346	4785	0	0
T2	447	167	0	0
T3	323	114	0	0
T4	5002	1212	0	0
T14	744	262	0	0
T15	3171	1408	0	0
T16	2715	1294	0	0
T19	583	102	0	0
T20	1900	849	0	0
T21	2677	1205	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1551040	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1551040	0	0
T1	32346	480	0	0
T2	447	4	0	0
T3	323	2	0	0
T4	5002	36	0	0
T14	744	16	0	0
T15	3171	56	0	0
T16	2715	18	0	0
T19	583	3	0	0
T20	1900	27	0	0
T21	2677	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3784294	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3784294	0	0
T1	32346	188	0	0
T2	447	4	0	0
T3	323	2	0	0
T4	5002	37	0	0
T14	744	16	0	0
T15	3171	56	0	0
T16	2715	18	0	0
T19	583	3	0	0
T20	1900	27	0	0
T21	2677	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1542255	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1542255	0	0
T1	32346	317	0	0
T2	447	6	0	0
T3	323	5	0	0
T4	5002	39	0	0
T14	744	9	0	0
T15	3171	61	0	0
T16	2715	19	0	0
T19	583	7	0	0
T20	1900	24	0	0
T21	2677	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3312570	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3312570	0	0
T1	32346	151	0	0
T2	447	6	0	0
T3	323	5	0	0
T4	5002	62	0	0
T14	744	9	0	0
T15	3171	61	0	0
T16	2715	19	0	0
T19	583	7	0	0
T20	1900	24	0	0
T21	2677	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1535968	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1535968	0	0
T1	32346	393	0	0
T2	447	6	0	0
T3	323	3	0	0
T4	5002	37	0	0
T14	744	4	0	0
T15	3171	48	0	0
T16	2715	24	0	0
T19	583	4	0	0
T20	1900	35	0	0
T21	2677	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3848260	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3848260	0	0
T1	32346	206	0	0
T2	447	6	0	0
T3	323	3	0	0
T4	5002	51	0	0
T14	744	4	0	0
T15	3171	48	0	0
T16	2715	24	0	0
T19	583	4	0	0
T20	1900	35	0	0
T21	2677	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1518418	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1518418	0	0
T1	32346	404	0	0
T2	447	4	0	0
T3	323	5	0	0
T4	5002	14	0	0
T14	744	13	0	0
T15	3171	51	0	0
T16	2715	19	0	0
T19	583	4	0	0
T20	1900	31	0	0
T21	2677	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3173247	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3173247	0	0
T1	32346	158	0	0
T2	447	4	0	0
T3	323	5	0	0
T4	5002	24	0	0
T14	744	13	0	0
T15	3171	51	0	0
T16	2715	19	0	0
T19	583	4	0	0
T20	1900	31	0	0
T21	2677	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1555483	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1555483	0	0
T1	32346	391	0	0
T2	447	6	0	0
T3	323	2	0	0
T4	5002	55	0	0
T14	744	10	0	0
T15	3171	68	0	0
T16	2715	25	0	0
T19	583	2	0	0
T20	1900	25	0	0
T21	2677	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3206128	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3206128	0	0
T1	32346	213	0	0
T2	447	6	0	0
T3	323	2	0	0
T4	5002	50	0	0
T14	744	10	0	0
T15	3171	68	0	0
T16	2715	25	0	0
T19	583	2	0	0
T20	1900	25	0	0
T21	2677	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1586455	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1586455	0	0
T1	32346	397	0	0
T2	447	7	0	0
T3	323	8	0	0
T4	5002	69	0	0
T14	744	10	0	0
T15	3171	45	0	0
T16	2715	26	0	0
T19	583	2	0	0
T20	1900	24	0	0
T21	2677	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3223482	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3223482	0	0
T1	32346	170	0	0
T2	447	7	0	0
T3	323	8	0	0
T4	5002	79	0	0
T14	744	10	0	0
T15	3171	45	0	0
T16	2715	26	0	0
T19	583	2	0	0
T20	1900	24	0	0
T21	2677	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1618173	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1618173	0	0
T1	32346	346	0	0
T2	447	5	0	0
T3	323	5	0	0
T4	5002	28	0	0
T14	744	14	0	0
T15	3171	63	0	0
T16	2715	17	0	0
T19	583	3	0	0
T20	1900	35	0	0
T21	2677	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3169836	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3169836	0	0
T1	32346	145	0	0
T2	447	5	0	0
T3	323	5	0	0
T4	5002	44	0	0
T14	744	14	0	0
T15	3171	63	0	0
T16	2715	17	0	0
T19	583	3	0	0
T20	1900	35	0	0
T21	2677	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1603256	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1603256	0	0
T1	32346	474	0	0
T2	447	9	0	0
T3	323	2	0	0
T4	5002	45	0	0
T14	744	10	0	0
T15	3171	48	0	0
T16	2715	17	0	0
T19	583	3	0	0
T20	1900	24	0	0
T21	2677	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	4186374	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	4186374	0	0
T1	32346	201	0	0
T2	447	9	0	0
T3	323	2	0	0
T4	5002	71	0	0
T14	744	10	0	0
T15	3171	48	0	0
T16	2715	17	0	0
T19	583	3	0	0
T20	1900	24	0	0
T21	2677	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1559331	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1559331	0	0
T1	32346	370	0	0
T2	447	3	0	0
T3	323	9	0	0
T4	5002	59	0	0
T14	744	12	0	0
T15	3171	46	0	0
T16	2715	21	0	0
T19	583	8	0	0
T20	1900	44	0	0
T21	2677	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3128773	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3128773	0	0
T1	32346	202	0	0
T2	447	3	0	0
T3	323	9	0	0
T4	5002	31	0	0
T14	744	12	0	0
T15	3171	46	0	0
T16	2715	21	0	0
T19	583	8	0	0
T20	1900	44	0	0
T21	2677	31	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1569204	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1569204	0	0
T1	32346	354	0	0
T2	447	10	0	0
T3	323	2	0	0
T4	5002	104	0	0
T14	744	10	0	0
T15	3171	56	0	0
T16	2715	29	0	0
T19	583	3	0	0
T20	1900	27	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3135058	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3135058	0	0
T1	32346	188	0	0
T2	447	10	0	0
T3	323	2	0	0
T4	5002	89	0	0
T14	744	10	0	0
T15	3171	56	0	0
T16	2715	29	0	0
T19	583	3	0	0
T20	1900	27	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1559364	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1559364	0	0
T1	32346	362	0	0
T2	447	6	0	0
T3	323	4	0	0
T4	5002	68	0	0
T14	744	12	0	0
T15	3171	49	0	0
T16	2715	18	0	0
T19	583	4	0	0
T20	1900	35	0	0
T21	2677	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3763474	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3763474	0	0
T1	32346	108	0	0
T2	447	6	0	0
T3	323	4	0	0
T4	5002	39	0	0
T14	744	12	0	0
T15	3171	49	0	0
T16	2715	18	0	0
T19	583	4	0	0
T20	1900	35	0	0
T21	2677	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1524398	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1524398	0	0
T1	32346	373	0	0
T2	447	8	0	0
T3	323	6	0	0
T4	5002	78	0	0
T14	744	13	0	0
T15	3171	45	0	0
T16	2715	29	0	0
T19	583	1	0	0
T20	1900	34	0	0
T21	2677	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3443788	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3443788	0	0
T1	32346	153	0	0
T2	447	8	0	0
T3	323	6	0	0
T4	5002	84	0	0
T14	744	13	0	0
T15	3171	45	0	0
T16	2715	29	0	0
T19	583	1	0	0
T20	1900	34	0	0
T21	2677	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1551013	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1551013	0	0
T1	32346	586	0	0
T2	447	5	0	0
T3	323	9	0	0
T4	5002	60	0	0
T14	744	6	0	0
T15	3171	56	0	0
T16	2715	18	0	0
T19	583	5	0	0
T20	1900	42	0	0
T21	2677	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3077793	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3077793	0	0
T1	32346	191	0	0
T2	447	5	0	0
T3	323	9	0	0
T4	5002	40	0	0
T14	744	6	0	0
T15	3171	56	0	0
T16	2715	18	0	0
T19	583	5	0	0
T20	1900	42	0	0
T21	2677	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1574079	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1574079	0	0
T1	32346	441	0	0
T2	447	6	0	0
T3	323	4	0	0
T4	5002	30	0	0
T14	744	11	0	0
T15	3171	47	0	0
T16	2715	21	0	0
T19	583	9	0	0
T20	1900	41	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	2763753	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	2763753	0	0
T1	32346	194	0	0
T2	447	6	0	0
T3	323	4	0	0
T4	5002	26	0	0
T14	744	11	0	0
T15	3171	47	0	0
T16	2715	21	0	0
T19	583	9	0	0
T20	1900	41	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1509141	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1509141	0	0
T1	32346	400	0	0
T2	447	3	0	0
T3	323	2	0	0
T4	5002	28	0	0
T14	744	8	0	0
T15	3171	50	0	0
T16	2715	26	0	0
T19	583	3	0	0
T20	1900	34	0	0
T21	2677	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	2691302	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	2691302	0	0
T1	32346	149	0	0
T2	447	3	0	0
T3	323	2	0	0
T4	5002	13	0	0
T14	744	8	0	0
T15	3171	50	0	0
T16	2715	26	0	0
T19	583	3	0	0
T20	1900	34	0	0
T21	2677	39	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1477661	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1477661	0	0
T1	32346	447	0	0
T2	447	8	0	0
T3	323	4	0	0
T4	5002	12	0	0
T14	744	6	0	0
T15	3171	56	0	0
T16	2715	21	0	0
T19	583	1	0	0
T20	1900	34	0	0
T21	2677	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	2762633	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	2762633	0	0
T1	32346	201	0	0
T2	447	8	0	0
T3	323	4	0	0
T4	5002	4	0	0
T14	744	6	0	0
T15	3171	56	0	0
T16	2715	21	0	0
T19	583	1	0	0
T20	1900	34	0	0
T21	2677	43	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1536916	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1536916	0	0
T1	32346	454	0	0
T2	447	5	0	0
T3	323	5	0	0
T4	5002	19	0	0
T14	744	7	0	0
T15	3171	51	0	0
T16	2715	29	0	0
T19	583	3	0	0
T20	1900	36	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3884357	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3884357	0	0
T1	32346	194	0	0
T2	447	5	0	0
T3	323	5	0	0
T4	5002	25	0	0
T14	744	7	0	0
T15	3171	51	0	0
T16	2715	29	0	0
T19	583	3	0	0
T20	1900	36	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1495329	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1495329	0	0
T1	32346	393	0	0
T2	447	10	0	0
T3	323	4	0	0
T4	5002	51	0	0
T14	744	10	0	0
T15	3171	42	0	0
T16	2715	19	0	0
T19	583	2	0	0
T20	1900	35	0	0
T21	2677	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3099721	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3099721	0	0
T1	32346	234	0	0
T2	447	10	0	0
T3	323	4	0	0
T4	5002	31	0	0
T14	744	10	0	0
T15	3171	42	0	0
T16	2715	19	0	0
T19	583	2	0	0
T20	1900	35	0	0
T21	2677	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1522984	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1522984	0	0
T1	32346	398	0	0
T2	447	8	0	0
T3	323	4	0	0
T4	5002	32	0	0
T14	744	6	0	0
T15	3171	49	0	0
T16	2715	23	0	0
T19	583	1	0	0
T20	1900	29	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3024169	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3024169	0	0
T1	32346	172	0	0
T2	447	8	0	0
T3	323	4	0	0
T4	5002	39	0	0
T14	744	6	0	0
T15	3171	49	0	0
T16	2715	23	0	0
T19	583	1	0	0
T20	1900	29	0	0
T21	2677	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1518038	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1518038	0	0
T1	32346	359	0	0
T2	447	5	0	0
T3	323	7	0	0
T4	5002	42	0	0
T14	744	8	0	0
T15	3171	46	0	0
T16	2715	23	0	0
T19	583	5	0	0
T20	1900	30	0	0
T21	2677	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	2943934	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	2943934	0	0
T1	32346	180	0	0
T2	447	5	0	0
T3	323	7	0	0
T4	5002	24	0	0
T14	744	8	0	0
T15	3171	46	0	0
T16	2715	23	0	0
T19	583	5	0	0
T20	1900	30	0	0
T21	2677	65	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1558780	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1558780	0	0
T1	32346	309	0	0
T2	447	6	0	0
T3	323	3	0	0
T4	5002	47	0	0
T14	744	14	0	0
T15	3171	47	0	0
T16	2715	23	0	0
T19	583	4	0	0
T20	1900	23	0	0
T21	2677	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3160840	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3160840	0	0
T1	32346	150	0	0
T2	447	6	0	0
T3	323	3	0	0
T4	5002	35	0	0
T14	744	14	0	0
T15	3171	47	0	0
T16	2715	23	0	0
T19	583	4	0	0
T20	1900	23	0	0
T21	2677	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1541006	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1541006	0	0
T1	32346	473	0	0
T2	447	5	0	0
T3	323	5	0	0
T4	5002	51	0	0
T14	744	6	0	0
T15	3171	65	0	0
T16	2715	30	0	0
T19	583	3	0	0
T20	1900	27	0	0
T21	2677	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3769019	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3769019	0	0
T1	32346	201	0	0
T2	447	5	0	0
T3	323	5	0	0
T4	5002	25	0	0
T14	744	6	0	0
T15	3171	65	0	0
T16	2715	30	0	0
T19	583	3	0	0
T20	1900	27	0	0
T21	2677	45	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1534719	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1534719	0	0
T1	32346	340	0	0
T2	447	6	0	0
T3	323	2	0	0
T4	5002	83	0	0
T14	744	8	0	0
T15	3171	49	0	0
T16	2715	20	0	0
T19	583	3	0	0
T20	1900	23	0	0
T21	2677	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	2892579	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	2892579	0	0
T1	32346	184	0	0
T2	447	6	0	0
T3	323	2	0	0
T4	5002	85	0	0
T14	744	8	0	0
T15	3171	49	0	0
T16	2715	20	0	0
T19	583	3	0	0
T20	1900	23	0	0
T21	2677	41	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1551536	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1551536	0	0
T1	32346	339	0	0
T2	447	6	0	0
T3	323	1	0	0
T4	5002	19	0	0
T14	744	10	0	0
T15	3171	59	0	0
T16	2715	33	0	0
T19	583	4	0	0
T20	1900	33	0	0
T21	2677	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3269977	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3269977	0	0
T1	32346	153	0	0
T2	447	6	0	0
T3	323	1	0	0
T4	5002	29	0	0
T14	744	10	0	0
T15	3171	59	0	0
T16	2715	33	0	0
T19	583	4	0	0
T20	1900	33	0	0
T21	2677	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1624480	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1624480	0	0
T1	32346	447	0	0
T2	447	8	0	0
T3	323	1	0	0
T4	5002	17	0	0
T14	744	6	0	0
T15	3171	58	0	0
T16	2715	16	0	0
T19	583	4	0	0
T20	1900	30	0	0
T21	2677	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3899626	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3899626	0	0
T1	32346	129	0	0
T2	447	8	0	0
T3	323	1	0	0
T4	5002	16	0	0
T14	744	6	0	0
T15	3171	58	0	0
T16	2715	16	0	0
T19	583	4	0	0
T20	1900	30	0	0
T21	2677	46	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1552306	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1552306	0	0
T1	32346	443	0	0
T2	447	8	0	0
T3	323	5	0	0
T4	5002	60	0	0
T14	744	13	0	0
T15	3171	45	0	0
T16	2715	30	0	0
T19	583	8	0	0
T20	1900	29	0	0
T21	2677	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3441232	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3441232	0	0
T1	32346	141	0	0
T2	447	8	0	0
T3	323	5	0	0
T4	5002	81	0	0
T14	744	13	0	0
T15	3171	45	0	0
T16	2715	30	0	0
T19	583	8	0	0
T20	1900	29	0	0
T21	2677	67	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	1569308	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	1569308	0	0
T1	32346	383	0	0
T2	447	4	0	0
T3	323	5	0	0
T4	5002	65	0	0
T14	744	9	0	0
T15	3171	52	0	0
T16	2715	30	0	0
T19	583	3	0	0
T20	1900	37	0	0
T21	2677	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314966507	3485841	0	0
DepthKnown_A	314966507	314850635	0	0
RvalidKnown_A	314966507	314850635	0	0
WreadyKnown_A	314966507	314850635	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	3485841	0	0
T1	32346	228	0	0
T2	447	4	0	0
T3	323	5	0	0
T4	5002	78	0	0
T14	744	9	0	0
T15	3171	52	0	0
T16	2715	30	0	0
T19	583	3	0	0
T20	1900	37	0	0
T21	2677	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	314966507	314850635	0	0
T1	32346	32323	0	0
T2	447	435	0	0
T3	323	309	0	0
T4	5002	4962	0	0
T14	744	714	0	0
T15	3171	3110	0	0
T16	2715	2695	0	0
T19	583	518	0	0
T20	1900	1863	0	0
T21	2677	2637	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0