Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1652774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259575

1

T1

16

T2

271

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	647775	1			T1	55		T2	642		T3	45
values[0x0]	616067	1			T1	54		T2	630		T3	52
values[0x1]	648507	1			T1	34		T2	659		T3	55

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1281275	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

631074

1

T1

40

T2

657

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7010	1			T2	7		T19	8		T22	2
valid_sources[0x01]	7480	1			T2	9		T19	6		T23	12
valid_sources[0x02]	6220	1			T2	4		T19	3		T23	6
valid_sources[0x03]	7933	1			T2	9		T21	146		T19	8
valid_sources[0x04]	7481	1			T2	8		T19	7		T22	13
valid_sources[0x05]	8243	1			T2	4		T19	5		T23	9
valid_sources[0x06]	7355	1			T2	16		T19	13		T23	8
valid_sources[0x07]	7002	1			T2	7		T19	6		T23	11
valid_sources[0x08]	7841	1			T1	15		T2	4		T19	4
valid_sources[0x09]	9024	1			T2	4		T19	6		T22	10
valid_sources[0x0a]	8728	1			T2	10		T19	4		T22	17
valid_sources[0x0b]	11052	1			T2	11		T19	9		T23	10
valid_sources[0x0c]	7107	1			T2	7		T19	8		T23	1
valid_sources[0x0d]	6572	1			T2	5		T19	9		T22	7
valid_sources[0x0e]	6837	1			T2	13		T19	9		T22	1
valid_sources[0x0f]	6596	1			T2	8		T4	1		T19	11
valid_sources[0x10]	7075	1			T2	5		T19	11		T23	10
valid_sources[0x11]	7519	1			T2	6		T19	6		T22	1
valid_sources[0x12]	6858	1			T2	8		T19	9		T22	5
valid_sources[0x13]	7268	1			T2	2		T19	10		T22	24
valid_sources[0x14]	7303	1			T2	7		T19	8		T22	5
valid_sources[0x15]	7162	1			T2	1		T19	5		T22	14
valid_sources[0x16]	6942	1			T2	12		T19	2		T22	21
valid_sources[0x17]	7157	1			T2	14		T19	5		T23	12
valid_sources[0x18]	6790	1			T2	7		T19	9		T22	10
valid_sources[0x19]	8400	1			T2	8		T19	8		T23	8
valid_sources[0x1a]	7650	1			T2	4		T19	11		T22	22
valid_sources[0x1b]	7081	1			T2	8		T19	4		T22	9
valid_sources[0x1c]	7045	1			T2	6		T19	11		T22	10
valid_sources[0x1d]	8212	1			T2	5		T19	4		T22	3
valid_sources[0x1e]	6839	1			T2	4		T19	5		T23	28
valid_sources[0x1f]	7961	1			T2	5		T19	14		T22	4
valid_sources[0x20]	7328	1			T2	6		T19	7		T22	16
valid_sources[0x21]	7896	1			T19	7		T23	2		T5	1
valid_sources[0x22]	8066	1			T2	3		T19	3		T22	7
valid_sources[0x23]	6442	1			T2	5		T4	1		T19	5
valid_sources[0x24]	6878	1			T2	11		T19	8		T23	10
valid_sources[0x25]	7384	1			T2	10		T19	3		T22	14
valid_sources[0x26]	8066	1			T2	6		T19	4		T23	19
valid_sources[0x27]	7121	1			T2	5		T19	7		T23	11
valid_sources[0x28]	8199	1			T2	8		T19	9		T22	27
valid_sources[0x29]	7233	1			T2	2		T19	5		T23	19
valid_sources[0x2a]	7069	1			T2	17		T3	76		T19	7
valid_sources[0x2b]	7586	1			T2	8		T19	7		T23	8
valid_sources[0x2c]	6767	1			T2	6		T19	4		T23	16
valid_sources[0x2d]	7716	1			T2	9		T19	5		T22	12
valid_sources[0x2e]	7171	1			T2	7		T4	1		T19	1
valid_sources[0x2f]	7884	1			T2	6		T19	15		T22	22
valid_sources[0x30]	7246	1			T2	11		T19	9		T23	5
valid_sources[0x31]	7644	1			T2	8		T19	6		T22	9
valid_sources[0x32]	7688	1			T2	9		T19	3		T22	8
valid_sources[0x33]	7643	1			T2	7		T19	9		T22	14
valid_sources[0x34]	7878	1			T2	1		T19	5		T22	6
valid_sources[0x35]	7758	1			T2	6		T19	7		T22	35
valid_sources[0x36]	7039	1			T2	9		T19	9		T23	14
valid_sources[0x37]	7342	1			T2	6		T19	2		T22	67
valid_sources[0x38]	7702	1			T2	5		T19	8		T23	7
valid_sources[0x39]	7497	1			T2	5		T19	3		T22	2
valid_sources[0x3a]	7968	1			T2	11		T19	6		T23	17
valid_sources[0x3b]	9224	1			T2	6		T19	5		T22	17
valid_sources[0x3c]	8405	1			T2	7		T19	1		T22	23
valid_sources[0x3d]	7486	1			T2	10		T4	1		T19	7
valid_sources[0x3e]	7751	1			T2	11		T19	11		T22	18
valid_sources[0x3f]	7822	1			T2	6		T19	12		T22	4
valid_sources[0x40]	7461	1			T2	9		T19	8		T23	8
valid_sources[0x41]	8346	1			T2	2		T19	9		T22	2
valid_sources[0x42]	6754	1			T2	12		T19	8		T22	2
valid_sources[0x43]	7077	1			T2	7		T19	8		T22	8
valid_sources[0x44]	7187	1			T2	3		T19	4		T22	1
valid_sources[0x45]	8629	1			T2	8		T19	4		T23	9
valid_sources[0x46]	7551	1			T2	8		T19	8		T22	10
valid_sources[0x47]	6959	1			T2	5		T19	17		T22	5
valid_sources[0x48]	7833	1			T2	3		T19	6		T23	20
valid_sources[0x49]	6790	1			T2	9		T19	11		T22	7
valid_sources[0x4a]	8757	1			T2	10		T19	5		T23	14
valid_sources[0x4b]	7775	1			T2	8		T19	6		T22	6
valid_sources[0x4c]	7176	1			T2	4		T19	9		T23	10
valid_sources[0x4d]	7410	1			T2	6		T19	7		T23	13
valid_sources[0x4e]	6629	1			T2	6		T19	8		T22	3
valid_sources[0x4f]	7285	1			T2	7		T19	3		T22	9
valid_sources[0x50]	7289	1			T2	8		T19	6		T22	13
valid_sources[0x51]	7236	1			T2	10		T19	11		T22	21
valid_sources[0x52]	6549	1			T2	3		T19	21		T23	14
valid_sources[0x53]	6874	1			T2	8		T19	9		T22	6
valid_sources[0x54]	7232	1			T2	5		T19	7		T20	2
valid_sources[0x55]	7815	1			T2	8		T4	1		T19	7
valid_sources[0x56]	9293	1			T2	3		T19	11		T20	4
valid_sources[0x57]	6890	1			T2	10		T19	1		T22	9
valid_sources[0x58]	6290	1			T2	10		T19	3		T23	21
valid_sources[0x59]	6743	1			T2	5		T19	8		T22	9
valid_sources[0x5a]	7525	1			T2	6		T19	13		T23	17
valid_sources[0x5b]	7254	1			T2	9		T19	10		T23	5
valid_sources[0x5c]	8209	1			T2	7		T19	7		T22	20
valid_sources[0x5d]	9562	1			T2	4		T19	10		T22	40
valid_sources[0x5e]	6817	1			T2	10		T19	16		T22	6
valid_sources[0x5f]	7486	1			T2	4		T19	16		T22	16
valid_sources[0x60]	7935	1			T2	6		T19	2		T23	6
valid_sources[0x61]	7269	1			T2	9		T19	8		T23	7
valid_sources[0x62]	7570	1			T2	9		T19	7		T22	5
valid_sources[0x63]	8285	1			T2	7		T19	8		T22	32
valid_sources[0x64]	7022	1			T2	3		T19	13		T22	23
valid_sources[0x65]	7769	1			T2	8		T19	5		T22	2
valid_sources[0x66]	6890	1			T2	8		T19	12		T22	8
valid_sources[0x67]	8169	1			T2	5		T19	6		T22	7
valid_sources[0x68]	7742	1			T2	7		T19	2		T22	4
valid_sources[0x69]	7975	1			T2	6		T19	5		T22	12
valid_sources[0x6a]	7443	1			T1	4		T2	12		T19	5
valid_sources[0x6b]	7019	1			T2	8		T19	6		T22	7
valid_sources[0x6c]	6465	1			T2	7		T19	5		T22	21
valid_sources[0x6d]	6676	1			T2	3		T19	5		T22	22
valid_sources[0x6e]	6867	1			T2	7		T19	5		T22	11
valid_sources[0x6f]	7889	1			T2	10		T19	10		T22	1
valid_sources[0x70]	8107	1			T2	6		T19	4		T23	12
valid_sources[0x71]	7142	1			T2	5		T19	8		T23	1
valid_sources[0x72]	7600	1			T2	5		T19	5		T23	24
valid_sources[0x73]	8154	1			T2	7		T19	2		T23	11
valid_sources[0x74]	6653	1			T2	6		T19	8		T22	5
valid_sources[0x75]	8326	1			T2	10		T19	9		T22	2
valid_sources[0x76]	7004	1			T2	11		T19	2		T22	3
valid_sources[0x77]	7179	1			T2	7		T19	8		T22	11
valid_sources[0x78]	7747	1			T2	7		T19	2		T22	25
valid_sources[0x79]	7334	1			T2	6		T19	3		T22	6
valid_sources[0x7a]	9144	1			T2	1		T19	13		T22	9
valid_sources[0x7b]	7842	1			T2	13		T19	9		T23	10
valid_sources[0x7c]	7028	1			T2	12		T19	5		T22	13
valid_sources[0x7d]	7218	1			T2	9		T19	10		T22	8
valid_sources[0x7e]	7652	1			T2	10		T19	3		T23	24
valid_sources[0x7f]	7062	1			T2	13		T19	5		T22	2
valid_sources[0x80]	6990	1			T2	6		T19	11		T22	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27496

1

T1

2

T2

33

T3

1

values[0x0]

all_enables

biggest_size

204458

1

T1

13

T2

204

T3

17

values[0x1]

all_enables

biggest_size

27621

1

T1

1

T2

34

T3

2