Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	332402455	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	332402455
T1	199192	3667
T2	218232	7642
T3	47376	746
T4	455840	10726
T5	48216	924
T19	225512	7189
T20	254968	8026
T21	32424	2079
T22	229488	9592
T23	336952	15006
T24	0	1716

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	199192	194320
T2	218232	217560
T3	47376	43176
T4	455840	454888
T5	48216	44632
T19	225512	222992
T20	254968	249536
T21	32424	32088
T22	229488	226688
T23	336952	335832

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	199192	194320
T2	218232	217560
T3	47376	43176
T4	455840	454888
T5	48216	44632
T19	225512	222992
T20	254968	249536
T21	32424	32088
T22	229488	226688
T23	336952	335832

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	199192	194320
T2	218232	217560
T3	47376	43176
T4	455840	454888
T5	48216	44632
T19	225512	222992
T20	254968	249536
T21	32424	32088
T22	229488	226688
T23	336952	335832

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T19	56	56
T20	56	56
T21	56	56
T22	56	56
T23	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	126391101	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	126391101
T1	3557	1558
T2	3897	3795
T3	846	290
T4	8140	4267
T5	861	360
T19	4027	3604
T20	4553	3950
T21	579	521
T22	4098	3742
T23	6017	5820

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	85653966	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	85653966
T1	3557	588
T2	3897	1931
T3	846	152
T4	8140	2167
T5	861	188
T19	4027	1833
T20	4553	2022
T21	579	520
T22	4098	1950
T23	6017	3062

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1359229	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1359229
T1	3557	36
T2	3897	38
T3	846	2
T4	8140	87
T5	861	10
T19	4027	32
T20	4553	33
T21	579	0
T22	4098	74
T23	6017	135
T24	0	31

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3406862	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3406862
T1	3557	37
T2	3897	38
T3	846	2
T4	8140	88
T5	861	10
T19	4027	32
T20	4553	33
T21	579	0
T22	4098	74
T23	6017	135
T24	0	12

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1295788	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1295788
T1	3557	89
T2	3897	27
T3	846	3
T4	8140	77
T5	861	5
T19	4027	44
T20	4553	29
T21	579	0
T22	4098	66
T23	6017	98
T24	0	46

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3031284	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3031284
T1	3557	50
T2	3897	27
T3	846	3
T4	8140	111
T5	861	5
T19	4027	44
T20	4553	29
T21	579	0
T22	4098	66
T23	6017	98
T24	0	5

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1317509	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1317509
T1	3557	8
T2	3897	33
T3	846	6
T4	8140	68
T5	861	8
T19	4027	40
T20	4553	58
T21	579	0
T22	4098	78
T23	6017	94
T24	0	51

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3641120	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3641120
T1	3557	3
T2	3897	33
T3	846	6
T4	8140	64
T5	861	8
T19	4027	40
T20	4553	58
T21	579	0
T22	4098	78
T23	6017	94
T24	0	17

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1333020	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1333020
T1	3557	5
T2	3897	43
T3	846	4
T4	8140	155
T5	861	6
T19	4027	30
T20	4553	23
T21	579	0
T22	4098	58
T23	6017	113
T24	0	20

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3005268	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3005268
T1	3557	1
T2	3897	43
T3	846	4
T4	8140	118
T5	861	6
T19	4027	30
T20	4553	23
T21	579	0
T22	4098	58
T23	6017	113
T24	0	24

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1326802	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1326802
T1	3557	49
T2	3897	36
T3	846	6
T4	8140	128
T5	861	7
T19	4027	34
T20	4553	35
T21	579	0
T22	4098	59
T23	6017	100
T24	0	36

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3127438	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3127438
T1	3557	36
T2	3897	36
T3	846	6
T4	8140	136
T5	861	7
T19	4027	34
T20	4553	35
T21	579	0
T22	4098	59
T23	6017	100
T24	0	6

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1304888	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1304888
T1	3557	24
T2	3897	34
T3	846	9
T4	8140	64
T5	861	8
T19	4027	30
T20	4553	42
T21	579	0
T22	4098	74
T23	6017	101
T24	0	57

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3723030	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3723030
T1	3557	17
T2	3897	34
T3	846	9
T4	8140	78
T5	861	8
T19	4027	30
T20	4553	42
T21	579	0
T22	4098	74
T23	6017	101
T24	0	27

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1312076	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1312076
T1	3557	9
T2	3897	36
T3	846	7
T4	8140	73
T5	861	8
T19	4027	30
T20	4553	42
T21	579	0
T22	4098	67
T23	6017	115
T24	0	88

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2685861	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2685861
T1	3557	2
T2	3897	36
T3	846	7
T4	8140	75
T5	861	8
T19	4027	30
T20	4553	42
T21	579	0
T22	4098	67
T23	6017	115
T24	0	41

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1291933	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1291933
T1	3557	27
T2	3897	39
T3	846	6
T4	8140	71
T5	861	3
T19	4027	34
T20	4553	33
T21	579	293
T22	4098	63
T23	6017	106

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2642133	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2642133
T1	3557	42
T2	3897	39
T3	846	6
T4	8140	56
T5	861	3
T19	4027	34
T20	4553	33
T21	579	293
T22	4098	63
T23	6017	106

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1334252	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1334252
T1	3557	11
T2	3897	38
T3	846	9
T4	8140	61
T5	861	7
T19	4027	26
T20	4553	31
T21	579	0
T22	4098	71
T23	6017	126
T24	0	7

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3223330	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3223330
T1	3557	9
T2	3897	38
T3	846	9
T4	8140	65
T5	861	7
T19	4027	26
T20	4553	31
T21	579	0
T22	4098	71
T23	6017	126
T24	0	1

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1310249	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1310249
T1	3557	61
T2	3897	39
T3	846	7
T4	8140	77
T5	861	7
T19	4027	27
T20	4553	45
T21	579	0
T22	4098	77
T23	6017	99
T24	0	87

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3016601	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3016601
T1	3557	33
T2	3897	39
T3	846	7
T4	8140	128
T5	861	7
T19	4027	27
T20	4553	45
T21	579	0
T22	4098	77
T23	6017	99
T24	0	32

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1346322	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1346322
T1	3557	15
T2	3897	45
T3	846	6
T4	8140	41
T5	861	5
T19	4027	37
T20	4553	48
T21	579	0
T22	4098	67
T23	6017	115
T24	0	140

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3260376	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3260376
T1	3557	1
T2	3897	45
T3	846	6
T4	8140	42
T5	861	5
T19	4027	37
T20	4553	48
T21	579	0
T22	4098	67
T23	6017	115
T24	0	17

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1338382	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1338382
T1	3557	22
T2	3897	31
T3	846	5
T4	8140	124
T5	861	8
T19	4027	26
T20	4553	37
T21	579	0
T22	4098	79
T23	6017	124
T24	0	50

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3693600	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3693600
T1	3557	10
T2	3897	31
T3	846	5
T4	8140	79
T5	861	8
T19	4027	26
T20	4553	37
T21	579	0
T22	4098	79
T23	6017	124
T24	0	41

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1306557	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1306557
T1	3557	40
T2	3897	41
T3	846	7
T4	8140	86
T5	861	11
T19	4027	24
T20	4553	35
T21	579	0
T22	4098	67
T23	6017	105
T24	0	52

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2840466	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2840466
T1	3557	21
T2	3897	41
T3	846	7
T4	8140	91
T5	861	11
T19	4027	24
T20	4553	35
T21	579	0
T22	4098	67
T23	6017	105
T24	0	20

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1319190	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1319190
T1	3557	24
T2	3897	34
T3	846	4
T4	8140	42
T5	861	5
T19	4027	27
T20	4553	38
T21	579	0
T22	4098	75
T23	6017	136
T24	0	59

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3182697	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3182697
T1	3557	26
T2	3897	34
T3	846	4
T4	8140	75
T5	861	5
T19	4027	27
T20	4553	38
T21	579	0
T22	4098	75
T23	6017	136
T24	0	16

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1330174	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1330174
T1	3557	37
T2	3897	31
T3	846	11
T4	8140	81
T5	861	10
T19	4027	42
T20	4553	30
T21	579	0
T22	4098	73
T23	6017	105
T24	0	31

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2915639	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2915639
T1	3557	28
T2	3897	31
T3	846	11
T4	8140	113
T5	861	10
T19	4027	42
T20	4553	30
T21	579	0
T22	4098	73
T23	6017	105
T24	0	9

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1344404	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1344404
T1	3557	43
T2	3897	29
T3	846	7
T4	8140	37
T5	861	4
T19	4027	28
T20	4553	40
T21	579	0
T22	4098	70
T23	6017	106
T24	0	45

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2807338	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2807338
T1	3557	11
T2	3897	29
T3	846	7
T4	8140	32
T5	861	4
T19	4027	28
T20	4553	40
T21	579	0
T22	4098	70
T23	6017	106
T24	0	29

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1331769	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1331769
T1	3557	63
T2	3897	46
T3	846	3
T4	8140	74
T5	861	6
T19	4027	48
T20	4553	36
T21	579	0
T22	4098	82
T23	6017	132
T24	0	36

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2321351	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2321351
T1	3557	23
T2	3897	46
T3	846	3
T4	8140	90
T5	861	6
T19	4027	48
T20	4553	36
T21	579	0
T22	4098	82
T23	6017	132
T24	0	11

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1341358	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1341358
T1	3557	63
T2	3897	42
T3	846	4
T4	8140	86
T5	861	6
T19	4027	36
T20	4553	25
T21	579	0
T22	4098	69
T23	6017	134
T24	0	38

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3186125	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3186125
T1	3557	50
T2	3897	42
T3	846	4
T4	8140	68
T5	861	6
T19	4027	36
T20	4553	25
T21	579	0
T22	4098	69
T23	6017	134
T24	0	22

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1354174	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1354174
T1	3557	25
T2	3897	29
T3	846	5
T4	8140	50
T5	861	3
T19	4027	29
T20	4553	32
T21	579	0
T22	4098	78
T23	6017	103
T24	0	74

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3393509	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3393509
T1	3557	17
T2	3897	29
T3	846	5
T4	8140	65
T5	861	3
T19	4027	29
T20	4553	32
T21	579	0
T22	4098	78
T23	6017	103
T24	0	18

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1273886	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1273886
T1	3557	12
T2	3897	28
T3	846	7
T4	8140	36
T5	861	5
T19	4027	25
T20	4553	40
T21	579	0
T22	4098	72
T23	6017	105
T24	0	33

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3128072	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3128072
T1	3557	2
T2	3897	28
T3	846	7
T4	8140	58
T5	861	5
T19	4027	25
T20	4553	40
T21	579	0
T22	4098	72
T23	6017	105
T24	0	39

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1376237	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1376237
T1	3557	45
T2	3897	32
T3	846	7
T4	8140	125
T5	861	6
T19	4027	29
T20	4553	45
T21	579	0
T22	4098	67
T23	6017	109
T24	0	7

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3074825	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3074825
T1	3557	36
T2	3897	32
T3	846	7
T4	8140	143
T5	861	6
T19	4027	29
T20	4553	45
T21	579	0
T22	4098	67
T23	6017	109
T24	0	15

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1296245	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1296245
T1	3557	72
T2	3897	33
T3	846	3
T4	8140	45
T5	861	8
T19	4027	37
T20	4553	40
T21	579	0
T22	4098	77
T23	6017	122
T24	0	8

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3737602	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3737602
T1	3557	26
T2	3897	33
T3	846	3
T4	8140	78
T5	861	8
T19	4027	37
T20	4553	40
T21	579	0
T22	4098	77
T23	6017	122
T24	0	2

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1300061	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1300061
T1	3557	38
T2	3897	39
T3	846	6
T4	8140	89
T5	861	8
T19	4027	24
T20	4553	40
T21	579	0
T22	4098	71
T23	6017	116
T24	0	43

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2695850	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2695850
T1	3557	34
T2	3897	39
T3	846	6
T4	8140	52
T5	861	8
T19	4027	24
T20	4553	40
T21	579	0
T22	4098	71
T23	6017	116
T24	0	8

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1288378	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1288378
T1	3557	11
T2	3897	37
T3	846	5
T4	8140	121
T5	861	10
T19	4027	29
T20	4553	54
T21	579	0
T22	4098	75
T23	6017	114
T24	0	18

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	2757327	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	2757327
T1	3557	15
T2	3897	37
T3	846	5
T4	8140	94
T5	861	10
T19	4027	29
T20	4553	54
T21	579	0
T22	4098	75
T23	6017	114
T24	0	32

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1369448	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1369448
T1	3557	31
T2	3897	37
T3	846	3
T4	8140	60
T5	861	6
T19	4027	45
T20	4553	33
T21	579	0
T22	4098	73
T23	6017	117
T24	0	91

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3694010	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3694010
T1	3557	7
T2	3897	37
T3	846	3
T4	8140	52
T5	861	6
T19	4027	45
T20	4553	33
T21	579	0
T22	4098	73
T23	6017	117
T24	0	53

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1278963	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1278963
T1	3557	53
T2	3897	31
T3	846	6
T4	8140	132
T5	861	9
T19	4027	27
T20	4553	37
T21	579	226
T22	4098	76
T23	6017	123

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3288886	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3288886
T1	3557	45
T2	3897	31
T3	846	6
T4	8140	74
T5	861	9
T19	4027	27
T20	4553	37
T21	579	226
T22	4098	76
T23	6017	123

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	1272183	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	1272183
T1	3557	20
T2	3897	30
T3	846	4
T4	8140	35
T5	861	9
T19	4027	36
T20	4553	46
T21	579	0
T22	4098	92
T23	6017	109
T24	0	56

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	293178653	3223311	0	0
DepthKnown_A	293178653	293048511	0	0
RvalidKnown_A	293178653	293048511	0	0
WreadyKnown_A	293178653	293048511	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	293178653	3223311
T1	3557	6
T2	3897	30
T3	846	4
T4	8140	42
T5	861	9
T19	4027	36
T20	4553	46
T21	579	0
T22	4098	92
T23	6017	109
T24	0	15

DepthKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

RvalidKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

WreadyKnown_A

Name	Attempts	Real Successes
Total	293178653	293048511
T1	3557	3470
T2	3897	3885
T3	846	771
T4	8140	8123
T5	861	797
T19	4027	3982
T20	4553	4456
T21	579	573
T22	4098	4048
T23	6017	5997

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1
T23	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children