Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1662270	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

261072

1

T1

17

T2

13

T3

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	651185	1			T1	51		T2	41		T3	70
values[0x0]	622130	1			T1	40		T2	39		T3	74
values[0x1]	650027	1			T1	44		T2	40		T3	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1288629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634713

1

T1

44

T2

42

T3

74

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7597	1			T3	1		T4	3		T19	16
valid_sources[0x01]	7340	1			T4	1		T5	14		T14	2
valid_sources[0x02]	8321	1			T2	2		T4	3		T17	14
valid_sources[0x03]	6955	1			T4	3		T20	6		T22	3
valid_sources[0x04]	8425	1			T3	1		T4	2		T14	1
valid_sources[0x05]	6871	1			T2	2		T3	1		T4	1
valid_sources[0x06]	7146	1			T6	88		T4	1		T14	1
valid_sources[0x07]	7297	1			T1	11		T3	1		T19	15
valid_sources[0x08]	7946	1			T3	2		T4	1		T14	3
valid_sources[0x09]	8798	1			T1	4		T3	2		T4	2
valid_sources[0x0a]	7640	1			T3	1		T4	1		T17	6
valid_sources[0x0b]	7106	1			T3	1		T4	4		T19	18
valid_sources[0x0c]	7675	1			T4	1		T14	1		T17	7
valid_sources[0x0d]	6612	1			T3	7		T4	1		T15	1
valid_sources[0x0e]	7702	1			T3	1		T4	2		T14	4
valid_sources[0x0f]	6589	1			T1	2		T4	1		T14	4
valid_sources[0x10]	8057	1			T1	2		T3	2		T4	3
valid_sources[0x11]	7249	1			T1	8		T4	4		T19	6
valid_sources[0x12]	6883	1			T3	1		T4	1		T19	12
valid_sources[0x13]	7547	1			T4	2		T14	1		T15	1
valid_sources[0x14]	7208	1			T3	3		T4	1		T14	1
valid_sources[0x15]	8170	1			T3	1		T4	1		T19	15
valid_sources[0x16]	7491	1			T4	1		T19	20		T14	3
valid_sources[0x17]	7245	1			T3	1		T4	2		T15	1
valid_sources[0x18]	7048	1			T4	2		T19	11		T14	2
valid_sources[0x19]	7605	1			T2	6		T16	1		T15	7
valid_sources[0x1a]	7045	1			T3	2		T4	1		T14	2
valid_sources[0x1b]	7344	1			T3	2		T17	20		T23	11
valid_sources[0x1c]	7757	1			T3	1		T4	2		T14	2
valid_sources[0x1d]	7007	1			T6	151		T4	3		T14	3
valid_sources[0x1e]	7360	1			T1	1		T4	4		T5	31
valid_sources[0x1f]	6910	1			T3	1		T6	97		T4	3
valid_sources[0x20]	7593	1			T3	5		T4	1		T5	26
valid_sources[0x21]	7177	1			T4	2		T17	5		T21	3
valid_sources[0x22]	6341	1			T4	3		T22	3		T23	64
valid_sources[0x23]	6417	1			T4	1		T17	4		T20	5
valid_sources[0x24]	8118	1			T17	2		T37	1		T39	1
valid_sources[0x25]	7049	1			T3	1		T4	2		T19	19
valid_sources[0x26]	6975	1			T4	1		T15	1		T18	15
valid_sources[0x27]	6756	1			T3	1		T4	4		T19	32
valid_sources[0x28]	6425	1			T14	4		T17	16		T22	2
valid_sources[0x29]	6929	1			T4	1		T19	18		T15	1
valid_sources[0x2a]	6470	1			T2	1		T4	4		T19	9
valid_sources[0x2b]	7554	1			T2	3		T4	2		T15	2
valid_sources[0x2c]	7174	1			T3	1		T19	11		T17	4
valid_sources[0x2d]	6259	1			T4	1		T14	1		T15	6
valid_sources[0x2e]	7616	1			T4	6		T17	17		T20	1
valid_sources[0x2f]	7372	1			T2	1		T3	3		T4	1
valid_sources[0x30]	8620	1			T2	1		T3	1		T4	2
valid_sources[0x31]	7582	1			T1	1		T3	2		T19	13
valid_sources[0x32]	7293	1			T3	1		T6	169		T4	6
valid_sources[0x33]	10729	1			T3	2		T4	3		T19	5
valid_sources[0x34]	9132	1			T2	2		T4	1		T19	6
valid_sources[0x35]	8490	1			T4	3		T19	19		T15	1
valid_sources[0x36]	8565	1			T2	5		T6	158		T4	1
valid_sources[0x37]	8330	1			T4	3		T17	8		T39	1
valid_sources[0x38]	8306	1			T2	2		T4	3		T19	46
valid_sources[0x39]	8393	1			T2	1		T3	1		T4	3
valid_sources[0x3a]	8731	1			T3	3		T14	2		T15	5
valid_sources[0x3b]	6532	1			T3	1		T4	2		T15	1
valid_sources[0x3c]	9229	1			T3	2		T4	4		T17	2
valid_sources[0x3d]	6910	1			T3	2		T17	20		T20	3
valid_sources[0x3e]	7852	1			T2	2		T3	1		T4	2
valid_sources[0x3f]	6814	1			T1	1		T2	1		T3	3
valid_sources[0x40]	6440	1			T2	4		T3	2		T4	3
valid_sources[0x41]	7106	1			T2	1		T3	1		T4	2
valid_sources[0x42]	6574	1			T2	2		T4	3		T19	16
valid_sources[0x43]	6972	1			T2	3		T3	1		T4	3
valid_sources[0x44]	7067	1			T3	1		T4	3		T17	1
valid_sources[0x45]	7437	1			T4	1		T19	12		T17	18
valid_sources[0x46]	7086	1			T4	2		T14	1		T17	27
valid_sources[0x47]	6472	1			T3	4		T4	1		T19	19
valid_sources[0x48]	7875	1			T2	1		T3	2		T4	2
valid_sources[0x49]	7608	1			T1	8		T2	3		T3	1
valid_sources[0x4a]	7444	1			T3	4		T4	1		T15	1
valid_sources[0x4b]	6634	1			T4	2		T19	13		T14	1
valid_sources[0x4c]	8184	1			T3	2		T17	15		T20	1
valid_sources[0x4d]	7593	1			T2	1		T14	1		T15	4
valid_sources[0x4e]	7963	1			T4	1		T17	10		T20	3
valid_sources[0x4f]	7561	1			T2	4		T4	2		T19	7
valid_sources[0x50]	8037	1			T2	1		T4	5		T37	1
valid_sources[0x51]	6957	1			T4	2		T16	1		T15	3
valid_sources[0x52]	6988	1			T3	1		T19	30		T17	12
valid_sources[0x53]	7391	1			T4	1		T17	2		T18	21
valid_sources[0x54]	7502	1			T3	2		T6	75		T4	3
valid_sources[0x55]	8645	1			T1	12		T4	2		T19	19
valid_sources[0x56]	7112	1			T4	1		T14	2		T17	17
valid_sources[0x57]	6702	1			T14	2		T15	3		T17	2
valid_sources[0x58]	6159	1			T1	3		T15	2		T17	13
valid_sources[0x59]	7810	1			T2	1		T3	1		T4	2
valid_sources[0x5a]	7870	1			T4	2		T19	14		T14	1
valid_sources[0x5b]	8155	1			T3	2		T15	2		T17	4
valid_sources[0x5c]	7973	1			T3	2		T4	3		T19	12
valid_sources[0x5d]	7692	1			T3	3		T4	2		T19	33
valid_sources[0x5e]	6607	1			T1	1		T3	2		T4	2
valid_sources[0x5f]	6864	1			T14	2		T17	2		T38	6
valid_sources[0x60]	6345	1			T3	1		T4	5		T19	6
valid_sources[0x61]	6343	1			T17	6		T22	1		T24	2
valid_sources[0x62]	8507	1			T1	9		T4	1		T19	15
valid_sources[0x63]	8350	1			T3	1		T4	2		T19	16
valid_sources[0x64]	7867	1			T1	1		T2	1		T4	3
valid_sources[0x65]	7743	1			T39	1		T18	9		T25	10
valid_sources[0x66]	6868	1			T4	1		T15	1		T17	14
valid_sources[0x67]	6987	1			T3	1		T4	2		T19	17
valid_sources[0x68]	8078	1			T2	3		T19	9		T16	1
valid_sources[0x69]	6891	1			T3	1		T6	7		T4	3
valid_sources[0x6a]	6930	1			T3	2		T4	1		T19	14
valid_sources[0x6b]	7908	1			T3	2		T6	173		T4	2
valid_sources[0x6c]	6829	1			T2	5		T3	1		T4	2
valid_sources[0x6d]	7250	1			T6	56		T4	4		T19	34
valid_sources[0x6e]	7208	1			T4	2		T16	1		T17	11
valid_sources[0x6f]	7243	1			T3	2		T16	1		T17	34
valid_sources[0x70]	6795	1			T3	1		T4	1		T14	2
valid_sources[0x71]	6926	1			T2	5		T4	1		T14	2
valid_sources[0x72]	7615	1			T2	2		T4	4		T19	17
valid_sources[0x73]	6569	1			T3	1		T4	2		T17	8
valid_sources[0x74]	8750	1			T4	1		T17	21		T20	1
valid_sources[0x75]	7097	1			T1	1		T2	1		T4	3
valid_sources[0x76]	7168	1			T3	2		T4	1		T5	31
valid_sources[0x77]	7848	1			T3	1		T4	3		T20	3
valid_sources[0x78]	8025	1			T1	9		T4	2		T19	10
valid_sources[0x79]	7968	1			T4	2		T19	28		T20	1
valid_sources[0x7a]	7464	1			T1	1		T3	2		T4	2
valid_sources[0x7b]	7800	1			T3	1		T4	3		T17	12
valid_sources[0x7c]	6753	1			T2	1		T3	1		T4	2
valid_sources[0x7d]	6896	1			T6	24		T4	3		T17	17
valid_sources[0x7e]	7001	1			T3	1		T19	5		T15	1
valid_sources[0x7f]	6398	1			T4	3		T19	12		T17	21
valid_sources[0x80]	9482	1			T4	3		T14	1		T17	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27467

1

T1

1

T3

3

T6

18

values[0x0]

all_enables

biggest_size

206477

1

T1

16

T2

11

T3

25

values[0x1]

all_enables

biggest_size

27128

1

T2

2

T3

3

T6

26