Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	352986422	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	352986422
T1	26992	662
T2	188720	3313
T3	52640	1068
T4	43792	2060
T5	7992656	138991
T6	194656	8191
T14	5051256	89967
T15	39424	621
T16	184800	6047
T17	0	2626
T19	204456	6890
T20	0	25

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	26992	25536
T2	188720	184296
T3	52640	49336
T4	43792	41328
T5	7992656	7991368
T6	194656	193256
T14	5051256	5050416
T15	39424	37072
T16	184800	182896
T19	204456	202720

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	26992	25536
T2	188720	184296
T3	52640	49336
T4	43792	41328
T5	7992656	7991368
T6	194656	193256
T14	5051256	5050416
T15	39424	37072
T16	184800	182896
T19	204456	202720

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	26992	25536
T2	188720	184296
T3	52640	49336
T4	43792	41328
T5	7992656	7991368
T6	194656	193256
T14	5051256	5050416
T15	39424	37072
T16	184800	182896
T19	204456	202720

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T6	56	56
T14	56	56
T15	56	56
T16	56	56
T19	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	130713576	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	130713576
T1	482	257
T2	3370	1400
T3	940	414
T4	782	515
T5	142726	66955
T6	3476	3193
T14	90201	88218
T15	704	242
T16	3300	3016
T19	3651	1725

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	92339724	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	92339724
T1	482	135
T2	3370	506
T3	940	218
T4	782	515
T5	142726	14182
T6	3476	1668
T14	90201	464
T15	704	127
T16	3300	1537
T19	3651	1725

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1426661	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1426661
T1	482	2
T2	3370	8
T3	940	9
T4	782	0
T5	142726	329
T6	3476	54
T14	90201	33
T15	704	3
T16	3300	25
T17	0	54
T19	3651	52

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	2938101	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	2938101
T1	482	2
T2	3370	10
T3	940	9
T4	782	0
T5	142726	285
T6	3476	54
T14	90201	6
T15	704	3
T16	3300	25
T17	0	54
T19	3651	52

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1435114	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1435114
T1	482	3
T2	3370	40
T3	940	8
T4	782	0
T5	142726	1873
T6	3476	66
T14	90201	46
T15	704	2
T16	3300	32
T17	0	53
T19	3651	72

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3985053	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3985053
T1	482	3
T2	3370	30
T3	940	8
T4	782	0
T5	142726	775
T6	3476	66
T14	90201	10
T15	704	2
T16	3300	32
T17	0	53
T19	3651	72

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1371957	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1371957
T1	482	6
T2	3370	42
T3	940	9
T4	782	0
T5	142726	202
T6	3476	66
T14	90201	27
T15	704	6
T16	3300	28
T17	0	51
T19	3651	54

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3886911	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3886911
T1	482	6
T2	3370	29
T3	940	9
T4	782	0
T5	142726	440
T6	3476	66
T14	90201	7
T15	704	6
T16	3300	28
T17	0	51
T19	3651	54

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1427204	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1427204
T1	482	4
T2	3370	46
T3	940	9
T4	782	0
T5	142726	1489
T6	3476	71
T14	90201	16
T15	704	11
T16	3300	38
T17	0	63
T19	3651	50

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3744706	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3744706
T1	482	4
T2	3370	10
T3	940	9
T4	782	0
T5	142726	344
T6	3476	71
T14	90201	5
T15	704	11
T16	3300	38
T17	0	63
T19	3651	50

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1438282	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1438282
T1	482	5
T2	3370	2
T3	940	7
T4	782	0
T5	142726	2266
T6	3476	56
T14	90201	37
T15	704	5
T16	3300	20
T17	0	55
T19	3651	73

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	2726832	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	2726832
T1	482	5
T2	3370	9
T3	940	7
T4	782	0
T5	142726	423
T6	3476	56
T14	90201	7
T15	704	5
T16	3300	20
T17	0	55
T19	3651	73

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1412425	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1412425
T1	482	7
T2	3370	65
T3	940	9
T4	782	0
T5	142726	3233
T6	3476	64
T14	90201	29
T15	704	4
T16	3300	24
T17	0	44
T19	3651	69

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3197317	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3197317
T1	482	7
T2	3370	21
T3	940	9
T4	782	0
T5	142726	1389
T6	3476	64
T14	90201	7
T15	704	4
T16	3300	24
T17	0	44
T19	3651	69

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1376117	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1376117
T1	482	9
T2	3370	30
T3	940	11
T4	782	0
T5	142726	954
T6	3476	72
T14	90201	26
T15	704	3
T16	3300	17
T17	0	47
T19	3651	61

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3810727	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3810727
T1	482	9
T2	3370	27
T3	940	11
T4	782	0
T5	142726	518
T6	3476	72
T14	90201	5
T15	704	3
T16	3300	17
T17	0	47
T19	3651	61

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1444500	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1444500
T1	482	8
T2	3370	20
T3	940	5
T4	782	0
T5	142726	2404
T6	3476	61
T14	90201	36
T15	704	5
T16	3300	23
T17	0	66
T19	3651	56

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3918043	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3918043
T1	482	8
T2	3370	6
T3	940	5
T4	782	0
T5	142726	1276
T6	3476	61
T14	90201	7
T15	704	5
T16	3300	23
T17	0	66
T19	3651	56

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1449413	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1449413
T1	482	3
T2	3370	23
T3	940	10
T4	782	0
T5	142726	1800
T6	3476	69
T14	90201	31
T15	704	2
T16	3300	25
T17	0	46
T19	3651	69

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3945243	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3945243
T1	482	3
T2	3370	8
T3	940	10
T4	782	0
T5	142726	161
T6	3476	69
T14	90201	9
T15	704	2
T16	3300	25
T17	0	46
T19	3651	69

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1522679	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1522679
T1	482	3
T2	3370	8
T3	940	4
T4	782	268
T5	142726	437
T6	3476	64
T14	90201	31
T15	704	5
T16	3300	23
T19	3651	54

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3896857	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3896857
T1	482	3
T2	3370	2
T3	940	4
T4	782	268
T5	142726	686
T6	3476	64
T14	90201	7
T15	704	5
T16	3300	23
T19	3651	54

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1444601	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1444601
T1	482	5
T2	3370	85
T3	940	7
T4	782	0
T5	142726	908
T6	3476	64
T14	90201	41
T15	704	2
T16	3300	31
T17	0	54
T19	3651	73

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3570136	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3570136
T1	482	5
T2	3370	38
T3	940	7
T4	782	0
T5	142726	45
T6	3476	64
T14	90201	7
T15	704	2
T16	3300	31
T17	0	54
T19	3651	73

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1400815	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1400815
T1	482	6
T2	3370	60
T3	940	5
T4	782	0
T5	142726	1121
T6	3476	67
T14	90201	11
T15	704	5
T16	3300	17
T17	0	49
T19	3651	77

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3357059	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3357059
T1	482	6
T2	3370	54
T3	940	5
T4	782	0
T5	142726	97
T6	3476	67
T14	90201	3
T15	704	5
T16	3300	17
T17	0	49
T19	3651	77

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1431597	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1431597
T1	482	9
T2	3370	7
T3	940	14
T4	782	0
T5	142726	1684
T6	3476	61
T14	90201	25
T15	704	5
T16	3300	22
T17	0	41
T19	3651	56

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3769850	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3769850
T1	482	9
T2	3370	1
T3	940	14
T4	782	0
T5	142726	833
T6	3476	61
T14	90201	7
T15	704	5
T16	3300	22
T17	0	41
T19	3651	56

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1405506	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1405506
T1	482	3
T2	3370	19
T3	940	6
T4	782	0
T5	142726	2192
T6	3476	68
T14	90201	23
T15	704	4
T16	3300	22
T17	0	49
T19	3651	48

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3201143	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3201143
T1	482	3
T2	3370	14
T3	940	6
T4	782	0
T5	142726	408
T6	3476	68
T14	90201	8
T15	704	4
T16	3300	22
T17	0	49
T19	3651	48

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1451372	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1451372
T1	482	1
T2	3370	25
T3	940	15
T4	782	0
T5	142726	1295
T6	3476	54
T14	90201	28
T15	704	6
T16	3300	31
T17	0	44
T19	3651	67

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3271615	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3271615
T1	482	1
T2	3370	13
T3	940	15
T4	782	0
T5	142726	486
T6	3476	54
T14	90201	6
T15	704	6
T16	3300	31
T17	0	44
T19	3651	67

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1424021	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1424021
T1	482	5
T2	3370	69
T3	940	6
T4	782	0
T5	142726	3001
T6	3476	63
T14	90201	29
T15	704	6
T16	3300	34
T17	0	67
T19	3651	56

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3362324	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3362324
T1	482	5
T2	3370	21
T3	940	6
T4	782	0
T5	142726	434
T6	3476	63
T14	90201	7
T15	704	6
T16	3300	34
T17	0	67
T19	3651	56

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1472173	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1472173
T1	482	2
T2	3370	41
T3	940	9
T4	782	0
T5	142726	1502
T6	3476	55
T14	90201	28
T15	704	11
T16	3300	26
T17	0	63
T19	3651	63

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3338343	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3338343
T1	482	2
T2	3370	26
T3	940	9
T4	782	0
T5	142726	145
T6	3476	55
T14	90201	6
T15	704	11
T16	3300	26
T17	0	63
T19	3651	63

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1432281	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1432281
T1	482	11
T2	3370	35
T3	940	8
T4	782	0
T5	142726	2834
T6	3476	68
T14	90201	44
T15	704	3
T16	3300	33
T17	0	51
T19	3651	51

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3263033	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3263033
T1	482	11
T2	3370	11
T3	940	8
T4	782	0
T5	142726	528
T6	3476	68
T14	90201	7
T15	704	3
T16	3300	33
T17	0	51
T19	3651	51

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1407510	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1407510
T1	482	7
T2	3370	23
T3	940	10
T4	782	0
T5	142726	1412
T6	3476	57
T14	90201	40
T15	704	4
T16	3300	35
T17	0	64
T19	3651	60

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	2840447	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	2840447
T1	482	7
T2	3370	28
T3	940	10
T4	782	0
T5	142726	437
T6	3476	57
T14	90201	289
T15	704	4
T16	3300	35
T17	0	64
T19	3651	60

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1427309	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1427309
T1	482	5
T2	3370	28
T3	940	8
T4	782	0
T5	142726	3284
T6	3476	51
T14	90201	35
T15	704	5
T16	3300	29
T17	0	60
T19	3651	78

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3657644	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3657644
T1	482	5
T2	3370	17
T3	940	8
T4	782	0
T5	142726	1247
T6	3476	51
T14	90201	9
T15	704	5
T16	3300	29
T17	0	60
T19	3651	78

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1474784	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1474784
T1	482	3
T2	3370	7
T3	940	9
T4	782	0
T5	142726	2236
T6	3476	66
T14	90201	14
T15	704	3
T16	3300	23
T17	0	53
T19	3651	64

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3656154	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3656154
T1	482	3
T2	3370	16
T3	940	9
T4	782	0
T5	142726	807
T6	3476	66
T14	90201	5
T15	704	3
T16	3300	23
T17	0	53
T19	3651	64

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1447784	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1447784
T1	482	3
T2	3370	15
T3	940	4
T4	782	0
T5	142726	1008
T6	3476	59
T14	90201	0
T15	704	5
T16	3300	33
T17	0	34
T19	3651	77
T20	0	15

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3421289	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3421289
T1	482	3
T2	3370	2
T3	940	4
T4	782	0
T5	142726	207
T6	3476	59
T14	90201	0
T15	704	5
T16	3300	33
T17	0	34
T19	3651	77
T20	0	10

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1427056	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1427056
T1	482	4
T2	3370	73
T3	940	6
T4	782	0
T5	142726	1618
T6	3476	52
T14	90201	49
T15	704	5
T16	3300	33
T17	0	52
T19	3651	74

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3626291	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3626291
T1	482	4
T2	3370	24
T3	940	6
T4	782	0
T5	142726	893
T6	3476	52
T14	90201	12
T15	704	5
T16	3300	33
T17	0	52
T19	3651	74

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1382511	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1382511
T1	482	8
T2	3370	25
T3	940	8
T4	782	0
T5	142726	589
T6	3476	51
T14	90201	49
T15	704	2
T16	3300	30
T17	0	50
T19	3651	66

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	3352319	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	3352319
T1	482	8
T2	3370	12
T3	940	8
T4	782	0
T5	142726	429
T6	3476	51
T14	90201	12
T15	704	2
T16	3300	30
T17	0	50
T19	3651	66

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1420364	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1420364
T1	482	6
T2	3370	9
T3	940	8
T4	782	0
T5	142726	1885
T6	3476	65
T14	90201	44
T15	704	4
T16	3300	23
T17	0	52
T19	3651	65

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	2569469	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	2569469
T1	482	6
T2	3370	14
T3	940	8
T4	782	0
T5	142726	78
T6	3476	65
T14	90201	8
T15	704	4
T16	3300	23
T17	0	52
T19	3651	65

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1453349	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1453349
T1	482	4
T2	3370	56
T3	940	6
T4	782	247
T5	142726	1928
T6	3476	65
T14	90201	26
T15	704	5
T16	3300	31
T19	3651	73

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	2485203	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	2485203
T1	482	4
T2	3370	51
T3	940	6
T4	782	247
T5	142726	810
T6	3476	65
T14	90201	4
T15	704	5
T16	3300	31
T19	3651	73

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	1358979	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	1358979
T1	482	3
T2	3370	40
T3	940	8
T4	782	0
T5	142726	188
T6	3476	56
T14	90201	23
T15	704	5
T16	3300	39
T17	0	51
T19	3651	62

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	317898326	2574649	0	0
DepthKnown_A	317898326	317789935	0	0
RvalidKnown_A	317898326	317789935	0	0
WreadyKnown_A	317898326	317789935	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	317898326	2574649
T1	482	3
T2	3370	12
T3	940	8
T4	782	0
T5	142726	1
T6	3476	56
T14	90201	4
T15	704	5
T16	3300	39
T17	0	51
T19	3651	62

DepthKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

RvalidKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

WreadyKnown_A

Name	Attempts	Real Successes
Total	317898326	317789935
T1	482	456
T2	3370	3291
T3	940	881
T4	782	738
T5	142726	142703
T6	3476	3451
T14	90201	90186
T15	704	662
T16	3300	3266
T19	3651	3620

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T15	1	1
T16	1	1
T19	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children