Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1717514	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

269930

1

T1

24

T2

23

T3

81

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	672882	1			T1	53		T2	59		T3	191
values[0x0]	640960	1			T1	56		T2	53		T3	193
values[0x1]	673602	1			T1	44		T2	71		T3	187

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1330886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

656558

1

T1

48

T2

66

T3

181

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7646	1			T22	6		T26	8		T43	4
valid_sources[0x01]	9091	1			T1	2		T16	16		T19	2
valid_sources[0x02]	7341	1			T2	1		T3	13		T4	1
valid_sources[0x03]	7031	1			T16	17		T22	6		T24	10
valid_sources[0x04]	7337	1			T1	1		T19	2		T20	96
valid_sources[0x05]	7408	1			T1	1		T19	2		T22	7
valid_sources[0x06]	8447	1			T2	3		T4	3		T5	1
valid_sources[0x07]	7525	1			T1	1		T2	1		T19	2
valid_sources[0x08]	7801	1			T1	1		T4	31		T22	7
valid_sources[0x09]	7509	1			T2	1		T5	2		T19	2
valid_sources[0x0a]	7816	1			T2	3		T16	5		T21	2
valid_sources[0x0b]	7320	1			T1	2		T16	15		T5	2
valid_sources[0x0c]	7708	1			T1	2		T3	1		T5	1
valid_sources[0x0d]	7477	1			T16	10		T5	1		T19	2
valid_sources[0x0e]	7596	1			T1	2		T3	11		T18	4
valid_sources[0x0f]	7553	1			T5	1		T22	7		T25	2
valid_sources[0x10]	8794	1			T4	3		T16	18		T5	1
valid_sources[0x11]	7162	1			T1	3		T18	6		T21	3
valid_sources[0x12]	6933	1			T1	1		T2	1		T22	6
valid_sources[0x13]	7793	1			T2	4		T3	13		T22	8
valid_sources[0x14]	7422	1			T1	1		T3	1		T4	3
valid_sources[0x15]	7799	1			T1	2		T3	4		T19	2
valid_sources[0x16]	7202	1			T1	1		T2	1		T4	15
valid_sources[0x17]	7512	1			T1	2		T5	1		T19	2
valid_sources[0x18]	7033	1			T5	1		T19	1		T22	4
valid_sources[0x19]	8254	1			T2	3		T5	1		T6	1
valid_sources[0x1a]	7959	1			T2	1		T5	1		T19	1
valid_sources[0x1b]	8310	1			T2	3		T19	1		T22	19
valid_sources[0x1c]	7353	1			T1	3		T2	1		T3	1
valid_sources[0x1d]	7240	1			T5	1		T22	6		T23	1
valid_sources[0x1e]	7800	1			T1	1		T4	20		T5	1
valid_sources[0x1f]	7352	1			T2	2		T4	10		T17	247
valid_sources[0x20]	7769	1			T2	4		T5	1		T6	1
valid_sources[0x21]	7703	1			T2	1		T21	4		T22	15
valid_sources[0x22]	8411	1			T3	5		T14	1		T22	4
valid_sources[0x23]	7888	1			T1	1		T16	9		T22	8
valid_sources[0x24]	7592	1			T1	1		T15	1		T22	12
valid_sources[0x25]	7508	1			T2	2		T16	9		T21	2
valid_sources[0x26]	7952	1			T1	2		T2	1		T4	6
valid_sources[0x27]	7871	1			T1	3		T21	1		T22	13
valid_sources[0x28]	7947	1			T2	2		T19	1		T21	1
valid_sources[0x29]	7374	1			T1	3		T2	2		T4	2
valid_sources[0x2a]	7540	1			T3	29		T4	2		T21	1
valid_sources[0x2b]	8381	1			T4	16		T16	20		T22	8
valid_sources[0x2c]	7806	1			T21	4		T14	3		T15	2
valid_sources[0x2d]	7544	1			T3	20		T4	30		T16	16
valid_sources[0x2e]	7826	1			T1	1		T16	9		T5	1
valid_sources[0x2f]	7736	1			T1	1		T5	1		T22	13
valid_sources[0x30]	7409	1			T5	1		T21	2		T22	12
valid_sources[0x31]	7520	1			T4	10		T16	5		T5	2
valid_sources[0x32]	7751	1			T2	1		T19	2		T15	4
valid_sources[0x33]	7615	1			T3	7		T5	2		T19	1
valid_sources[0x34]	7619	1			T3	3		T4	12		T5	1
valid_sources[0x35]	7277	1			T1	1		T4	1		T16	14
valid_sources[0x36]	7619	1			T5	1		T19	3		T22	12
valid_sources[0x37]	7761	1			T3	15		T15	4		T22	14
valid_sources[0x38]	7971	1			T1	1		T16	6		T5	1
valid_sources[0x39]	7436	1			T4	8		T5	1		T22	4
valid_sources[0x3a]	7537	1			T16	17		T5	1		T22	9
valid_sources[0x3b]	7907	1			T21	2		T22	12		T52	1
valid_sources[0x3c]	7686	1			T1	1		T2	1		T4	13
valid_sources[0x3d]	7457	1			T1	2		T4	28		T19	3
valid_sources[0x3e]	7927	1			T1	1		T2	2		T5	1
valid_sources[0x3f]	7235	1			T2	5		T15	4		T22	6
valid_sources[0x40]	7810	1			T1	1		T2	1		T4	10
valid_sources[0x41]	7801	1			T3	10		T16	21		T5	1
valid_sources[0x42]	8400	1			T19	2		T22	12		T23	1
valid_sources[0x43]	8083	1			T3	11		T4	3		T17	227
valid_sources[0x44]	7967	1			T1	3		T5	1		T21	1
valid_sources[0x45]	8426	1			T4	23		T22	10		T41	4
valid_sources[0x46]	8543	1			T1	1		T6	3		T22	9
valid_sources[0x47]	8515	1			T4	1		T16	15		T21	1
valid_sources[0x48]	7711	1			T5	1		T19	1		T22	8
valid_sources[0x49]	7952	1			T1	1		T4	2		T5	1
valid_sources[0x4a]	7565	1			T21	2		T22	11		T23	1
valid_sources[0x4b]	7358	1			T13	5		T15	2		T22	12
valid_sources[0x4c]	7392	1			T4	13		T22	9		T25	1
valid_sources[0x4d]	8369	1			T16	11		T5	1		T17	127
valid_sources[0x4e]	7655	1			T2	1		T3	30		T5	1
valid_sources[0x4f]	8348	1			T4	9		T16	13		T19	5
valid_sources[0x50]	7307	1			T1	1		T14	2		T15	2
valid_sources[0x51]	8346	1			T1	1		T2	2		T16	16
valid_sources[0x52]	7411	1			T2	1		T4	15		T19	1
valid_sources[0x53]	8232	1			T19	1		T22	9		T24	12
valid_sources[0x54]	8315	1			T18	3		T21	1		T22	9
valid_sources[0x55]	8348	1			T1	2		T15	1		T22	3
valid_sources[0x56]	7786	1			T1	2		T2	1		T3	1
valid_sources[0x57]	8276	1			T4	2		T5	1		T22	8
valid_sources[0x58]	8412	1			T1	1		T21	3		T22	9
valid_sources[0x59]	7617	1			T2	2		T5	1		T6	1
valid_sources[0x5a]	8022	1			T3	9		T4	2		T19	1
valid_sources[0x5b]	7728	1			T1	1		T4	3		T5	1
valid_sources[0x5c]	8120	1			T2	1		T16	7		T5	1
valid_sources[0x5d]	7591	1			T3	21		T4	6		T5	1
valid_sources[0x5e]	8872	1			T1	1		T2	1		T16	8
valid_sources[0x5f]	6832	1			T16	18		T13	2		T21	2
valid_sources[0x60]	8400	1			T3	1		T16	14		T21	2
valid_sources[0x61]	7519	1			T2	1		T4	10		T22	3
valid_sources[0x62]	7314	1			T4	23		T5	1		T22	10
valid_sources[0x63]	8330	1			T22	9		T23	7		T41	3
valid_sources[0x64]	7338	1			T16	18		T5	2		T15	3
valid_sources[0x65]	7099	1			T1	1		T2	2		T16	15
valid_sources[0x66]	8305	1			T2	1		T5	1		T19	2
valid_sources[0x67]	8112	1			T1	1		T19	1		T22	12
valid_sources[0x68]	8073	1			T17	209		T14	1		T15	1
valid_sources[0x69]	8086	1			T19	2		T22	9		T23	1
valid_sources[0x6a]	7529	1			T1	1		T19	6		T21	1
valid_sources[0x6b]	7129	1			T1	1		T2	1		T4	16
valid_sources[0x6c]	8226	1			T3	22		T4	9		T15	1
valid_sources[0x6d]	8248	1			T2	5		T3	8		T21	5
valid_sources[0x6e]	7649	1			T18	4		T21	2		T22	10
valid_sources[0x6f]	7786	1			T2	2		T21	1		T22	5
valid_sources[0x70]	7992	1			T1	1		T18	21		T19	2
valid_sources[0x71]	7652	1			T1	1		T2	1		T4	28
valid_sources[0x72]	8389	1			T1	1		T2	1		T4	2
valid_sources[0x73]	7623	1			T1	1		T2	1		T4	7
valid_sources[0x74]	7785	1			T1	1		T15	2		T22	11
valid_sources[0x75]	7424	1			T1	1		T5	2		T14	1
valid_sources[0x76]	7840	1			T4	33		T22	13		T24	5
valid_sources[0x77]	7650	1			T3	10		T4	2		T15	1
valid_sources[0x78]	7806	1			T2	3		T3	10		T4	3
valid_sources[0x79]	7748	1			T1	2		T19	5		T39	252
valid_sources[0x7a]	8157	1			T2	2		T22	9		T41	2
valid_sources[0x7b]	7515	1			T2	1		T22	6		T23	1
valid_sources[0x7c]	7977	1			T1	1		T22	8		T41	2
valid_sources[0x7d]	7552	1			T1	5		T2	1		T6	2
valid_sources[0x7e]	7292	1			T19	2		T21	1		T22	2
valid_sources[0x7f]	8122	1			T5	1		T22	4		T25	3
valid_sources[0x80]	7878	1			T1	2		T5	2		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28656

1

T1

3

T2

3

T3

7

values[0x0]

all_enables

biggest_size

212599

1

T1

20

T2

16

T3

65

values[0x1]

all_enables

biggest_size

28675

1

T1

1

T2

4

T3

9