Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_s1n_28.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo	100.00	100.00					100.00

---

Module Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[3].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[4].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[5].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[6].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[7].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[8].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[9].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[10].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[11].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[12].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[13].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[14].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[15].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[16].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[17].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[18].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[19].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[20].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[21].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[22].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[23].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[24].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[25].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[26].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	357310735	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	357310735	0	0
T1	30296	745	0	0
T2	51520	898	0	0
T3	93240	2802	0	0
T4	1048656	21348	0	0
T5	155232	2281	0	0
T6	152768	5508	0	0
T13	0	28429	0	0
T16	91952	2524	0	0
T17	183736	11376	0	0
T18	39144	526	0	0
T19	44240	961	0	0
T20	0	104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	30296	28112	0	0
T2	51520	46928	0	0
T3	93240	89208	0	0
T4	1048656	1047816	0	0
T5	155232	152208	0	0
T6	152768	147392	0	0
T16	91952	88704	0	0
T17	183736	179816	0	0
T18	39144	34832	0	0
T19	44240	42000	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	30296	28112	0	0
T2	51520	46928	0	0
T3	93240	89208	0	0
T4	1048656	1047816	0	0
T5	155232	152208	0	0
T6	152768	147392	0	0
T16	91952	88704	0	0
T17	183736	179816	0	0
T18	39144	34832	0	0
T19	44240	42000	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	30296	28112	0	0
T2	51520	46928	0	0
T3	93240	89208	0	0
T4	1048656	1047816	0	0
T5	155232	152208	0	0
T6	152768	147392	0	0
T16	91952	88704	0	0
T17	183736	179816	0	0
T18	39144	34832	0	0
T19	44240	42000	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	50400	50400	0	0
T1	56	56	0	0
T2	56	56	0	0
T3	56	56	0	0
T4	56	56	0	0
T5	56	56	0	0
T6	56	56	0	0
T16	56	56	0	0
T17	56	56	0	0
T18	56	56	0	0
T19	56	56	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	133286549	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	133286549	0	0
T1	541	286	0	0
T2	920	349	0	0
T3	1665	1089	0	0
T4	18726	9402	0	0
T5	2772	932	0	0
T6	2728	2151	0	0
T16	1642	632	0	0
T17	3281	2844	0	0
T18	699	205	0	0
T19	790	376	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	91041304	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	91041304	0	0
T1	541	153	0	0
T2	920	183	0	0
T3	1665	571	0	0
T4	18726	2919	0	0
T5	2772	681	0	0
T6	2728	1119	0	0
T16	1642	632	0	0
T17	3281	2844	0	0
T18	699	107	0	0
T19	790	195	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1600480	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1600480	0	0
T1	541	10	0	0
T2	920	9	0	0
T3	1665	18	0	0
T4	18726	292	0	0
T5	2772	4	0	0
T6	2728	40	0	0
T13	0	15	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3202640	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3202640	0	0
T1	541	10	0	0
T2	920	9	0	0
T3	1665	18	0	0
T4	18726	176	0	0
T5	2772	4	0	0
T6	2728	40	0	0
T13	0	479	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1525372	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1525372	0	0
T1	541	7	0	0
T2	920	14	0	0
T3	1665	18	0	0
T4	18726	203	0	0
T5	2772	4	0	0
T6	2728	54	0	0
T16	1642	27	0	0
T17	3281	210	0	0
T18	699	4	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	2540698	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	2540698	0	0
T1	541	7	0	0
T2	920	14	0	0
T3	1665	18	0	0
T4	18726	122	0	0
T5	2772	8	0	0
T6	2728	54	0	0
T16	1642	27	0	0
T17	3281	210	0	0
T18	699	4	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1589090	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1589090	0	0
T1	541	4	0	0
T2	920	3	0	0
T3	1665	15	0	0
T4	18726	277	0	0
T5	2772	16	0	0
T6	2728	42	0	0
T13	0	19	0	0
T16	1642	33	0	0
T17	3281	0	0	0
T18	699	6	0	0
T19	790	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3197501	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3197501	0	0
T1	541	4	0	0
T2	920	3	0	0
T3	1665	15	0	0
T4	18726	158	0	0
T5	2772	28	0	0
T6	2728	42	0	0
T13	0	1773	0	0
T16	1642	33	0	0
T17	3281	0	0	0
T18	699	6	0	0
T19	790	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1607882	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1607882	0	0
T1	541	4	0	0
T2	920	7	0	0
T3	1665	27	0	0
T4	18726	223	0	0
T5	2772	0	0	0
T6	2728	34	0	0
T13	0	15	0	0
T16	1642	26	0	0
T17	3281	255	0	0
T18	699	6	0	0
T19	790	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	4487850	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	4487850	0	0
T1	541	4	0	0
T2	920	7	0	0
T3	1665	27	0	0
T4	18726	103	0	0
T5	2772	0	0	0
T6	2728	34	0	0
T13	0	950	0	0
T16	1642	26	0	0
T17	3281	255	0	0
T18	699	6	0	0
T19	790	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1616920	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1616920	0	0
T1	541	5	0	0
T2	920	0	0	0
T3	1665	24	0	0
T4	18726	211	0	0
T5	2772	16	0	0
T6	2728	51	0	0
T13	0	11	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	10	0	0
T20	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3926211	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3926211	0	0
T1	541	5	0	0
T2	920	0	0	0
T3	1665	24	0	0
T4	18726	109	0	0
T5	2772	5	0	0
T6	2728	51	0	0
T13	0	637	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	10	0	0
T20	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1659183	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1659183	0	0
T1	541	8	0	0
T2	920	3	0	0
T3	1665	20	0	0
T4	18726	188	0	0
T5	2772	30	0	0
T6	2728	45	0	0
T13	0	16	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3301841	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3301841	0	0
T1	541	8	0	0
T2	920	3	0	0
T3	1665	20	0	0
T4	18726	61	0	0
T5	2772	24	0	0
T6	2728	45	0	0
T13	0	1858	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1576083	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1576083	0	0
T1	541	2	0	0
T2	920	6	0	0
T3	1665	18	0	0
T4	18726	294	0	0
T5	2772	48	0	0
T6	2728	39	0	0
T13	0	24	0	0
T16	1642	30	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3866999	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3866999	0	0
T1	541	2	0	0
T2	920	6	0	0
T3	1665	18	0	0
T4	18726	96	0	0
T5	2772	37	0	0
T6	2728	39	0	0
T13	0	884	0	0
T16	1642	30	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1619558	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1619558	0	0
T1	541	8	0	0
T2	920	7	0	0
T3	1665	18	0	0
T4	18726	211	0	0
T5	2772	0	0	0
T6	2728	50	0	0
T13	0	18	0	0
T16	1642	17	0	0
T17	3281	0	0	0
T18	699	1	0	0
T19	790	9	0	0
T20	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	2792218	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	2792218	0	0
T1	541	8	0	0
T2	920	7	0	0
T3	1665	18	0	0
T4	18726	154	0	0
T5	2772	0	0	0
T6	2728	50	0	0
T13	0	755	0	0
T16	1642	17	0	0
T17	3281	0	0	0
T18	699	1	0	0
T19	790	9	0	0
T20	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1617127	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1617127	0	0
T1	541	4	0	0
T2	920	7	0	0
T3	1665	20	0	0
T4	18726	240	0	0
T5	2772	50	0	0
T6	2728	42	0	0
T13	0	18	0	0
T16	1642	26	0	0
T17	3281	0	0	0
T18	699	5	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	2861992	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	2861992	0	0
T1	541	4	0	0
T2	920	7	0	0
T3	1665	20	0	0
T4	18726	126	0	0
T5	2772	8	0	0
T6	2728	42	0	0
T13	0	1040	0	0
T16	1642	26	0	0
T17	3281	0	0	0
T18	699	5	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1594659	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1594659	0	0
T1	541	4	0	0
T2	920	7	0	0
T3	1665	20	0	0
T4	18726	210	0	0
T5	2772	0	0	0
T6	2728	37	0	0
T13	0	10	0	0
T16	1642	26	0	0
T17	3281	0	0	0
T18	699	5	0	0
T19	790	10	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3380014	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3380014	0	0
T1	541	4	0	0
T2	920	7	0	0
T3	1665	20	0	0
T4	18726	135	0	0
T5	2772	0	0	0
T6	2728	37	0	0
T13	0	2020	0	0
T16	1642	26	0	0
T17	3281	0	0	0
T18	699	5	0	0
T19	790	10	0	0
T20	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1608135	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1608135	0	0
T1	541	10	0	0
T2	920	9	0	0
T3	1665	19	0	0
T4	18726	154	0	0
T5	2772	2	0	0
T6	2728	46	0	0
T13	0	6	0	0
T16	1642	24	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3694863	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3694863	0	0
T1	541	10	0	0
T2	920	9	0	0
T3	1665	19	0	0
T4	18726	57	0	0
T5	2772	19	0	0
T6	2728	46	0	0
T13	0	776	0	0
T16	1642	24	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1596268	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1596268	0	0
T1	541	7	0	0
T2	920	7	0	0
T3	1665	23	0	0
T4	18726	232	0	0
T5	2772	27	0	0
T6	2728	34	0	0
T16	1642	14	0	0
T17	3281	508	0	0
T18	699	7	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3735211	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3735211	0	0
T1	541	7	0	0
T2	920	7	0	0
T3	1665	23	0	0
T4	18726	68	0	0
T5	2772	17	0	0
T6	2728	34	0	0
T16	1642	14	0	0
T17	3281	508	0	0
T18	699	7	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1610184	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1610184	0	0
T1	541	7	0	0
T2	920	6	0	0
T3	1665	18	0	0
T4	18726	246	0	0
T5	2772	12	0	0
T6	2728	52	0	0
T13	0	13	0	0
T16	1642	26	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3329311	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3329311	0	0
T1	541	7	0	0
T2	920	6	0	0
T3	1665	18	0	0
T4	18726	101	0	0
T5	2772	12	0	0
T6	2728	52	0	0
T13	0	1453	0	0
T16	1642	26	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1562988	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1562988	0	0
T1	541	7	0	0
T2	920	6	0	0
T3	1665	25	0	0
T4	18726	242	0	0
T5	2772	3	0	0
T6	2728	43	0	0
T16	1642	30	0	0
T17	3281	409	0	0
T18	699	6	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3861551	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3861551	0	0
T1	541	7	0	0
T2	920	6	0	0
T3	1665	25	0	0
T4	18726	92	0	0
T5	2772	4	0	0
T6	2728	43	0	0
T16	1642	30	0	0
T17	3281	409	0	0
T18	699	6	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1632251	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1632251	0	0
T1	541	9	0	0
T2	920	8	0	0
T3	1665	25	0	0
T4	18726	155	0	0
T5	2772	4	0	0
T6	2728	42	0	0
T13	0	6	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	1	0	0
T19	790	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3125256	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3125256	0	0
T1	541	9	0	0
T2	920	8	0	0
T3	1665	25	0	0
T4	18726	108	0	0
T5	2772	1	0	0
T6	2728	42	0	0
T13	0	1611	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	1	0	0
T19	790	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1625670	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1625670	0	0
T1	541	2	0	0
T2	920	9	0	0
T3	1665	24	0	0
T4	18726	292	0	0
T5	2772	23	0	0
T6	2728	54	0	0
T13	0	3	0	0
T16	1642	19	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3033200	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3033200	0	0
T1	541	2	0	0
T2	920	9	0	0
T3	1665	24	0	0
T4	18726	101	0	0
T5	2772	22	0	0
T6	2728	54	0	0
T13	0	1	0	0
T16	1642	19	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1557856	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1557856	0	0
T1	541	5	0	0
T2	920	12	0	0
T3	1665	17	0	0
T4	18726	303	0	0
T5	2772	9	0	0
T6	2728	45	0	0
T16	1642	19	0	0
T17	3281	246	0	0
T18	699	6	0	0
T19	790	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3523102	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3523102	0	0
T1	541	5	0	0
T2	920	12	0	0
T3	1665	17	0	0
T4	18726	146	0	0
T5	2772	18	0	0
T6	2728	45	0	0
T16	1642	19	0	0
T17	3281	246	0	0
T18	699	6	0	0
T19	790	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1576365	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1576365	0	0
T1	541	6	0	0
T2	920	4	0	0
T3	1665	23	0	0
T4	18726	131	0	0
T5	2772	20	0	0
T6	2728	32	0	0
T13	0	25	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	2	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3407443	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3407443	0	0
T1	541	6	0	0
T2	920	4	0	0
T3	1665	23	0	0
T4	18726	103	0	0
T5	2772	17	0	0
T6	2728	32	0	0
T13	0	858	0	0
T16	1642	21	0	0
T17	3281	0	0	0
T18	699	2	0	0
T19	790	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1592536	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1592536	0	0
T1	541	3	0	0
T2	920	3	0	0
T3	1665	29	0	0
T4	18726	193	0	0
T5	2772	24	0	0
T6	2728	31	0	0
T16	1642	20	0	0
T17	3281	483	0	0
T18	699	3	0	0
T19	790	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3318560	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3318560	0	0
T1	541	3	0	0
T2	920	3	0	0
T3	1665	29	0	0
T4	18726	111	0	0
T5	2772	9	0	0
T6	2728	31	0	0
T16	1642	20	0	0
T17	3281	483	0	0
T18	699	3	0	0
T19	790	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1551553	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1551553	0	0
T1	541	7	0	0
T2	920	5	0	0
T3	1665	25	0	0
T4	18726	231	0	0
T5	2772	1	0	0
T6	2728	29	0	0
T13	0	29	0	0
T16	1642	22	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3119684	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3119684	0	0
T1	541	7	0	0
T2	920	5	0	0
T3	1665	25	0	0
T4	18726	84	0	0
T5	2772	3	0	0
T6	2728	29	0	0
T13	0	2100	0	0
T16	1642	22	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1533326	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1533326	0	0
T1	541	6	0	0
T2	920	13	0	0
T3	1665	31	0	0
T4	18726	186	0	0
T5	2772	14	0	0
T6	2728	51	0	0
T13	0	2	0	0
T16	1642	30	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3029960	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3029960	0	0
T1	541	6	0	0
T2	920	13	0	0
T3	1665	31	0	0
T4	18726	76	0	0
T5	2772	1	0	0
T6	2728	51	0	0
T13	0	416	0	0
T16	1642	30	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1578056	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1578056	0	0
T1	541	5	0	0
T2	920	2	0	0
T3	1665	19	0	0
T4	18726	220	0	0
T5	2772	0	0	0
T6	2728	43	0	0
T13	0	25	0	0
T16	1642	21	0	0
T17	3281	490	0	0
T18	699	3	0	0
T19	790	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3988149	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3988149	0	0
T1	541	5	0	0
T2	920	2	0	0
T3	1665	19	0	0
T4	18726	125	0	0
T5	2772	0	0	0
T6	2728	43	0	0
T13	0	2457	0	0
T16	1642	21	0	0
T17	3281	490	0	0
T18	699	3	0	0
T19	790	5	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1589613	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1589613	0	0
T1	541	5	0	0
T2	920	6	0	0
T3	1665	20	0	0
T4	18726	258	0	0
T5	2772	13	0	0
T6	2728	43	0	0
T13	0	28	0	0
T16	1642	33	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3141270	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3141270	0	0
T1	541	5	0	0
T2	920	6	0	0
T3	1665	20	0	0
T4	18726	128	0	0
T5	2772	9	0	0
T6	2728	43	0	0
T13	0	2578	0	0
T16	1642	33	0	0
T17	3281	0	0	0
T18	699	4	0	0
T19	790	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1572307	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1572307	0	0
T1	541	7	0	0
T2	920	8	0	0
T3	1665	17	0	0
T4	18726	265	0	0
T5	2772	29	0	0
T6	2728	36	0	0
T13	0	25	0	0
T16	1642	20	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3315012	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3315012	0	0
T1	541	7	0	0
T2	920	8	0	0
T3	1665	17	0	0
T4	18726	96	0	0
T5	2772	21	0	0
T6	2728	36	0	0
T13	0	3040	0	0
T16	1642	20	0	0
T17	3281	0	0	0
T18	699	3	0	0
T19	790	4	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1592805	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1592805	0	0
T1	541	2	0	0
T2	920	7	0	0
T3	1665	20	0	0
T4	18726	176	0	0
T5	2772	15	0	0
T6	2728	30	0	0
T16	1642	17	0	0
T17	3281	243	0	0
T18	699	4	0	0
T19	790	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	2590776	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	2590776	0	0
T1	541	2	0	0
T2	920	7	0	0
T3	1665	20	0	0
T4	18726	112	0	0
T5	2772	17	0	0
T6	2728	30	0	0
T16	1642	17	0	0
T17	3281	243	0	0
T18	699	4	0	0
T19	790	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1532506	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1532506	0	0
T1	541	6	0	0
T2	920	11	0	0
T3	1665	18	0	0
T4	18726	227	0	0
T5	2772	0	0	0
T6	2728	37	0	0
T13	0	9	0	0
T16	1642	27	0	0
T17	3281	0	0	0
T18	699	2	0	0
T19	790	2	0	0
T20	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	3413329	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	3413329	0	0
T1	541	6	0	0
T2	920	11	0	0
T3	1665	18	0	0
T4	18726	102	0	0
T5	2772	0	0	0
T6	2728	37	0	0
T13	0	756	0	0
T16	1642	27	0	0
T17	3281	0	0	0
T18	699	2	0	0
T19	790	2	0	0
T20	0	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	1544502	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	1544502	0	0
T1	541	3	0	0
T2	920	4	0	0
T3	1665	20	0	0
T4	18726	248	0	0
T5	2772	11	0	0
T6	2728	37	0	0
T13	0	33	0	0
T16	1642	18	0	0
T17	3281	0	0	0
T18	699	8	0	0
T19	790	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	320437697	2934966	0	0
DepthKnown_A	320437697	320321545	0	0
RvalidKnown_A	320437697	320321545	0	0
WreadyKnown_A	320437697	320321545	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	2934966	0	0
T1	541	3	0	0
T2	920	4	0	0
T3	1665	20	0	0
T4	18726	69	0	0
T5	2772	9	0	0
T6	2728	37	0	0
T13	0	1637	0	0
T16	1642	18	0	0
T17	3281	0	0	0
T18	699	8	0	0
T19	790	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320437697	320321545	0	0
T1	541	502	0	0
T2	920	838	0	0
T3	1665	1593	0	0
T4	18726	18711	0	0
T5	2772	2718	0	0
T6	2728	2632	0	0
T16	1642	1584	0	0
T17	3281	3211	0	0
T18	699	622	0	0
T19	790	750	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0