Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1694892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

266430

1

T1

15

T2

12

T3

65

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	665415	1			T1	49		T2	56		T3	156
values[0x0]	632386	1			T1	51		T2	58		T3	178
values[0x1]	663521	1			T1	54		T2	48		T3	172

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1312946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

648376

1

T1

38

T2

40

T3

175

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8148	1			T1	1		T5	2		T18	11
valid_sources[0x01]	7878	1			T3	2		T18	10		T20	1
valid_sources[0x02]	6987	1			T3	5		T5	5		T18	2
valid_sources[0x03]	7214	1			T3	2		T18	8		T14	9
valid_sources[0x04]	7324	1			T2	3		T3	4		T18	4
valid_sources[0x05]	8060	1			T2	1		T3	4		T5	15
valid_sources[0x06]	7176	1			T2	1		T3	7		T18	4
valid_sources[0x07]	7895	1			T2	1		T3	2		T5	2
valid_sources[0x08]	7355	1			T18	5		T14	2		T23	1
valid_sources[0x09]	7252	1			T2	4		T3	1		T5	11
valid_sources[0x0a]	7761	1			T3	3		T5	2		T18	9
valid_sources[0x0b]	7262	1			T5	4		T18	8		T14	13
valid_sources[0x0c]	6850	1			T2	1		T5	8		T18	6
valid_sources[0x0d]	7063	1			T1	1		T3	1		T18	7
valid_sources[0x0e]	7243	1			T3	1		T5	8		T18	7
valid_sources[0x0f]	7744	1			T5	6		T18	5		T14	2
valid_sources[0x10]	7056	1			T2	1		T18	13		T21	2
valid_sources[0x11]	8182	1			T2	2		T3	2		T18	16
valid_sources[0x12]	7506	1			T2	1		T18	2		T20	1
valid_sources[0x13]	7251	1			T1	1		T3	1		T18	18
valid_sources[0x14]	8774	1			T2	4		T3	1		T5	5
valid_sources[0x15]	8440	1			T3	1		T18	3		T19	15
valid_sources[0x16]	7151	1			T2	1		T18	1		T20	1
valid_sources[0x17]	7348	1			T2	2		T5	7		T18	7
valid_sources[0x18]	7498	1			T2	1		T3	3		T5	4
valid_sources[0x19]	8067	1			T2	3		T18	7		T14	7
valid_sources[0x1a]	7129	1			T2	1		T3	1		T5	3
valid_sources[0x1b]	7249	1			T2	2		T3	1		T5	1
valid_sources[0x1c]	7841	1			T2	1		T5	8		T18	16
valid_sources[0x1d]	7501	1			T2	1		T3	2		T5	10
valid_sources[0x1e]	7820	1			T3	2		T18	12		T20	3
valid_sources[0x1f]	7966	1			T3	2		T18	6		T20	1
valid_sources[0x20]	8140	1			T2	6		T3	1		T18	5
valid_sources[0x21]	8167	1			T2	1		T3	1		T18	7
valid_sources[0x22]	7170	1			T2	1		T3	7		T18	11
valid_sources[0x23]	7378	1			T2	1		T3	1		T5	1
valid_sources[0x24]	7849	1			T3	5		T5	9		T18	4
valid_sources[0x25]	7490	1			T2	3		T18	3		T21	3
valid_sources[0x26]	7692	1			T1	4		T2	1		T5	4
valid_sources[0x27]	7770	1			T3	1		T5	4		T18	11
valid_sources[0x28]	7502	1			T2	2		T3	2		T21	2
valid_sources[0x29]	7575	1			T1	5		T3	4		T18	9
valid_sources[0x2a]	7348	1			T3	3		T18	6		T20	1
valid_sources[0x2b]	7910	1			T3	1		T18	13		T14	11
valid_sources[0x2c]	7778	1			T18	10		T14	10		T23	1
valid_sources[0x2d]	7343	1			T2	1		T3	1		T18	2
valid_sources[0x2e]	9995	1			T3	1		T18	14		T21	3
valid_sources[0x2f]	7739	1			T3	3		T18	3		T14	4
valid_sources[0x30]	7620	1			T3	3		T5	5		T18	16
valid_sources[0x31]	7138	1			T5	4		T18	12		T14	11
valid_sources[0x32]	6825	1			T3	1		T5	2		T18	8
valid_sources[0x33]	8253	1			T5	2		T18	19		T20	1
valid_sources[0x34]	7477	1			T3	2		T18	6		T21	1
valid_sources[0x35]	7802	1			T2	1		T3	3		T5	2
valid_sources[0x36]	7651	1			T18	4		T20	1		T14	17
valid_sources[0x37]	7732	1			T3	3		T18	6		T19	16
valid_sources[0x38]	7846	1			T1	14		T3	1		T18	9
valid_sources[0x39]	7671	1			T3	3		T18	3		T14	16
valid_sources[0x3a]	7570	1			T3	1		T5	1		T18	7
valid_sources[0x3b]	7473	1			T5	3		T18	13		T14	7
valid_sources[0x3c]	7181	1			T3	6		T5	2		T18	7
valid_sources[0x3d]	7395	1			T1	5		T3	3		T18	16
valid_sources[0x3e]	7718	1			T2	5		T18	15		T22	1
valid_sources[0x3f]	7986	1			T3	1		T18	3		T14	6
valid_sources[0x40]	7104	1			T3	1		T5	4		T18	4
valid_sources[0x41]	9249	1			T2	1		T3	4		T18	7
valid_sources[0x42]	7171	1			T2	3		T5	1		T18	8
valid_sources[0x43]	7594	1			T2	1		T5	5		T18	6
valid_sources[0x44]	7145	1			T2	2		T3	1		T18	18
valid_sources[0x45]	7692	1			T5	1		T18	1		T20	1
valid_sources[0x46]	8701	1			T3	2		T18	4		T19	9
valid_sources[0x47]	8033	1			T2	1		T3	2		T5	1
valid_sources[0x48]	7995	1			T3	7		T5	6		T18	12
valid_sources[0x49]	7127	1			T3	7		T18	1		T19	5
valid_sources[0x4a]	7195	1			T2	1		T3	3		T5	4
valid_sources[0x4b]	7975	1			T18	11		T20	1		T14	14
valid_sources[0x4c]	8622	1			T3	2		T5	4		T18	7
valid_sources[0x4d]	8395	1			T3	2		T18	11		T14	6
valid_sources[0x4e]	7581	1			T3	3		T18	8		T14	5
valid_sources[0x4f]	7074	1			T3	7		T18	8		T14	9
valid_sources[0x50]	7428	1			T3	3		T18	11		T14	2
valid_sources[0x51]	8037	1			T2	2		T3	2		T5	1
valid_sources[0x52]	7586	1			T3	3		T18	11		T20	1
valid_sources[0x53]	7890	1			T1	3		T2	1		T3	1
valid_sources[0x54]	7804	1			T3	3		T18	10		T21	4
valid_sources[0x55]	7917	1			T3	6		T18	7		T20	2
valid_sources[0x56]	7409	1			T18	3		T14	2		T22	1
valid_sources[0x57]	9152	1			T2	1		T5	9		T18	2
valid_sources[0x58]	7171	1			T3	4		T5	1		T18	6
valid_sources[0x59]	7254	1			T1	1		T2	2		T3	1
valid_sources[0x5a]	7376	1			T3	1		T5	2		T20	2
valid_sources[0x5b]	8451	1			T2	1		T5	7		T18	18
valid_sources[0x5c]	7535	1			T3	2		T18	5		T19	13
valid_sources[0x5d]	7726	1			T1	11		T3	2		T5	7
valid_sources[0x5e]	6935	1			T3	2		T5	4		T18	14
valid_sources[0x5f]	8403	1			T3	4		T18	5		T19	12
valid_sources[0x60]	7565	1			T2	3		T3	2		T18	11
valid_sources[0x61]	7729	1			T1	2		T2	2		T18	5
valid_sources[0x62]	8084	1			T2	2		T3	1		T5	17
valid_sources[0x63]	7121	1			T3	1		T5	6		T18	5
valid_sources[0x64]	7585	1			T18	9		T19	11		T21	1
valid_sources[0x65]	7175	1			T2	1		T3	1		T18	10
valid_sources[0x66]	7421	1			T3	1		T18	1		T21	2
valid_sources[0x67]	7724	1			T3	4		T18	3		T14	4
valid_sources[0x68]	7651	1			T2	2		T3	1		T18	6
valid_sources[0x69]	7726	1			T2	3		T3	2		T5	1
valid_sources[0x6a]	8120	1			T3	1		T18	2		T19	12
valid_sources[0x6b]	6707	1			T3	1		T5	9		T18	1
valid_sources[0x6c]	6837	1			T3	1		T18	7		T20	1
valid_sources[0x6d]	7579	1			T2	4		T5	5		T18	8
valid_sources[0x6e]	7532	1			T5	4		T18	9		T20	1
valid_sources[0x6f]	6915	1			T2	1		T3	1		T18	1
valid_sources[0x70]	7154	1			T3	3		T18	5		T14	2
valid_sources[0x71]	8608	1			T3	4		T5	1		T18	14
valid_sources[0x72]	7903	1			T2	1		T3	7		T5	4
valid_sources[0x73]	7468	1			T1	2		T5	1		T18	3
valid_sources[0x74]	7794	1			T3	5		T5	6		T18	23
valid_sources[0x75]	8048	1			T3	3		T5	5		T18	8
valid_sources[0x76]	8288	1			T3	3		T18	11		T14	2
valid_sources[0x77]	7488	1			T2	3		T5	3		T18	5
valid_sources[0x78]	7710	1			T18	4		T14	7		T23	2
valid_sources[0x79]	7639	1			T2	1		T3	7		T18	1
valid_sources[0x7a]	7573	1			T2	2		T5	2		T18	3
valid_sources[0x7b]	7947	1			T18	2		T14	5		T15	1
valid_sources[0x7c]	7174	1			T3	2		T5	4		T18	1
valid_sources[0x7d]	6884	1			T3	1		T5	5		T18	5
valid_sources[0x7e]	7311	1			T1	7		T18	14		T20	1
valid_sources[0x7f]	8390	1			T3	2		T18	12		T14	8
valid_sources[0x80]	8119	1			T1	3		T2	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28095

1

T1

1

T2

1

T3

4

values[0x0]

all_enables

biggest_size

210134

1

T1

12

T2

10

T3

54

values[0x1]

all_enables

biggest_size

28201

1

T1

2

T2

1

T3

7