Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	349645514	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	349645514
T1	29624	753
T2	249032	4271
T3	73584	2486
T4	6451480	127639
T5	58688	2514
T14	192024	5897
T15	0	230
T18	110656	7640
T19	665784	9624
T20	204456	4653
T21	26992	947
T22	0	45484

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	29624	28392
T2	249032	246624
T3	73584	70672
T4	6451480	6447336
T5	58688	58408
T14	192024	187544
T18	110656	110208
T19	665784	663208
T20	204456	201600
T21	26992	26152

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	29624	28392
T2	249032	246624
T3	73584	70672
T4	6451480	6447336
T5	58688	58408
T14	192024	187544
T18	110656	110208
T19	665784	663208
T20	204456	201600
T21	26992	26152

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	29624	28392
T2	249032	246624
T3	73584	70672
T4	6451480	6447336
T5	58688	58408
T14	192024	187544
T18	110656	110208
T19	665784	663208
T20	204456	201600
T21	26992	26152

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T14	56	56
T18	56	56
T19	56	56
T20	56	56
T21	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	128645533	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	128645533
T1	529	291
T2	4447	1953
T3	1314	968
T4	115205	59196
T5	1048	984
T14	3429	2939
T18	1976	1910
T19	11889	2461
T20	3651	2013
T21	482	365

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	91151342	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	91151342
T1	529	154
T2	4447	529
T3	1314	506
T4	115205	14152
T5	1048	510
T14	3429	1500
T18	1976	1910
T19	11889	2351
T20	3651	888
T21	482	194

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1514648	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1514648
T1	529	5
T2	4447	17
T3	1314	8
T4	115205	3649
T5	1048	23
T14	3429	29
T18	1976	0
T19	11889	12
T20	3651	53
T21	482	8
T22	0	10

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3660742	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3660742
T1	529	5
T2	4447	5
T3	1314	8
T4	115205	378
T5	1048	23
T14	3429	29
T18	1976	0
T19	11889	22
T20	3651	58
T21	482	8
T22	0	355

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1460113	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1460113
T1	529	2
T2	4447	68
T3	1314	17
T4	115205	2831
T5	1048	23
T14	3429	24
T18	1976	0
T19	11889	126
T20	3651	36
T21	482	14
T22	0	28

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3486674	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3486674
T1	529	2
T2	4447	17
T3	1314	17
T4	115205	261
T5	1048	23
T14	3429	24
T18	1976	0
T19	11889	155
T20	3651	45
T21	482	14
T22	0	2571

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1454883	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1454883
T1	529	6
T2	4447	4
T3	1314	22
T4	115205	2910
T5	1048	14
T14	3429	28
T15	0	50
T18	1976	0
T19	11889	75
T20	3651	6
T21	482	10

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3494290	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3494290
T1	529	6
T2	4447	1
T3	1314	22
T4	115205	221
T5	1048	14
T14	3429	28
T15	0	50
T18	1976	0
T19	11889	61
T20	3651	7
T21	482	10

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1535349	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1535349
T1	529	10
T2	4447	36
T3	1314	25
T4	115205	1085
T5	1048	25
T14	3429	36
T18	1976	0
T19	11889	150
T20	3651	36
T21	482	12
T22	0	16

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	4107862	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	4107862
T1	529	10
T2	4447	28
T3	1314	25
T4	115205	679
T5	1048	25
T14	3429	36
T18	1976	0
T19	11889	177
T20	3651	20
T21	482	12
T22	0	1380

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1505048	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1505048
T1	529	8
T2	4447	73
T3	1314	14
T4	115205	1876
T5	1048	21
T14	3429	31
T18	1976	0
T19	11889	138
T20	3651	43
T21	482	6
T22	0	35

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3687096	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3687096
T1	529	8
T2	4447	43
T3	1314	14
T4	115205	873
T5	1048	21
T14	3429	31
T18	1976	0
T19	11889	91
T20	3651	42
T21	482	6
T22	0	1350

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1514302	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1514302
T1	529	2
T2	4447	40
T3	1314	16
T4	115205	3254
T5	1048	10
T14	3429	26
T18	1976	0
T19	11889	45
T20	3651	12
T21	482	3
T22	0	35

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3457170	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3457170
T1	529	2
T2	4447	20
T3	1314	16
T4	115205	897
T5	1048	10
T14	3429	26
T18	1976	0
T19	11889	69
T20	3651	34
T21	482	3
T22	0	4505

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1467227	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1467227
T1	529	7
T2	4447	54
T3	1314	21
T4	115205	77
T5	1048	22
T14	3429	28
T18	1976	0
T19	11889	146
T20	3651	2
T21	482	6
T22	0	26

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	4612687	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	4612687
T1	529	7
T2	4447	17
T3	1314	21
T4	115205	535
T5	1048	22
T14	3429	28
T18	1976	0
T19	11889	177
T20	3651	2
T21	482	6
T22	0	2952

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1478720	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1478720
T1	529	8
T2	4447	58
T3	1314	19
T4	115205	739
T5	1048	17
T14	3429	22
T18	1976	491
T19	11889	40
T20	3651	1
T21	482	11

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3223301	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3223301
T1	529	8
T2	4447	21
T3	1314	19
T4	115205	403
T5	1048	17
T14	3429	22
T18	1976	491
T19	11889	39
T20	3651	2
T21	482	11

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1435096	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1435096
T1	529	10
T2	4447	21
T3	1314	32
T4	115205	840
T5	1048	28
T14	3429	22
T18	1976	0
T19	11889	28
T20	3651	40
T21	482	3
T22	0	16

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3742171	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3742171
T1	529	10
T2	4447	16
T3	1314	32
T4	115205	277
T5	1048	28
T14	3429	22
T18	1976	0
T19	11889	37
T20	3651	38
T21	482	3
T22	0	1604

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1453161	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1453161
T1	529	6
T2	4447	41
T3	1314	22
T4	115205	666
T5	1048	23
T14	3429	20
T18	1976	0
T19	11889	108
T20	3651	13
T21	482	11
T22	0	17

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3260356	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3260356
T1	529	6
T2	4447	17
T3	1314	22
T4	115205	199
T5	1048	23
T14	3429	20
T18	1976	0
T19	11889	39
T20	3651	1
T21	482	11
T22	0	2599

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1476131	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1476131
T1	529	4
T2	4447	48
T3	1314	25
T4	115205	271
T5	1048	15
T14	3429	30
T18	1976	0
T19	11889	76
T20	3651	21
T21	482	3
T22	0	37

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3465782	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3465782
T1	529	4
T2	4447	13
T3	1314	25
T4	115205	114
T5	1048	15
T14	3429	30
T18	1976	0
T19	11889	83
T20	3651	47
T21	482	3
T22	0	3151

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1442333	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1442333
T1	529	5
T2	4447	83
T3	1314	21
T4	115205	3873
T5	1048	17
T14	3429	18
T18	1976	0
T19	11889	99
T20	3651	30
T21	482	8
T22	0	31

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3025694	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3025694
T1	529	5
T2	4447	18
T3	1314	21
T4	115205	620
T5	1048	17
T14	3429	18
T18	1976	0
T19	11889	112
T20	3651	38
T21	482	8
T22	0	3622

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1484363	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1484363
T1	529	5
T2	4447	36
T3	1314	19
T4	115205	1445
T5	1048	21
T14	3429	32
T18	1976	0
T19	11889	89
T20	3651	58
T21	482	7
T22	0	17

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3960535	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3960535
T1	529	5
T2	4447	23
T3	1314	19
T4	115205	729
T5	1048	21
T14	3429	32
T18	1976	0
T19	11889	56
T20	3651	67
T21	482	7
T22	0	1945

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1473643	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1473643
T1	529	5
T2	4447	37
T3	1314	18
T4	115205	1086
T5	1048	24
T14	3429	22
T18	1976	0
T19	11889	89
T20	3651	39
T21	482	4
T22	0	15

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3135245	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3135245
T1	529	5
T2	4447	16
T3	1314	18
T4	115205	496
T5	1048	24
T14	3429	22
T18	1976	0
T19	11889	63
T20	3651	60
T21	482	4
T22	0	2430

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1456598	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1456598
T1	529	3
T2	4447	46
T3	1314	15
T4	115205	1010
T5	1048	17
T14	3429	34
T18	1976	200
T19	11889	56
T20	3651	30
T21	482	2

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	2560014	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	2560014
T1	529	3
T2	4447	39
T3	1314	15
T4	115205	110
T5	1048	17
T14	3429	34
T18	1976	200
T19	11889	118
T20	3651	16
T21	482	2

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1476754	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1476754
T1	529	7
T2	4447	88
T3	1314	21
T4	115205	2602
T5	1048	21
T14	3429	24
T18	1976	217
T19	11889	95
T20	3651	79
T21	482	9

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3426711	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3426711
T1	529	7
T2	4447	33
T3	1314	21
T4	115205	1138
T5	1048	21
T14	3429	24
T18	1976	217
T19	11889	91
T20	3651	93
T21	482	9

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1483149	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1483149
T1	529	5
T2	4447	99
T3	1314	21
T4	115205	2490
T5	1048	17
T14	3429	28
T18	1976	0
T19	11889	96
T20	3651	61
T21	482	5
T22	0	38

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	2649321	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	2649321
T1	529	5
T2	4447	37
T3	1314	21
T4	115205	124
T5	1048	17
T14	3429	28
T18	1976	0
T19	11889	68
T20	3651	55
T21	482	5
T22	0	2408

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1428657	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1428657
T1	529	4
T2	4447	74
T3	1314	18
T4	115205	1772
T5	1048	21
T14	3429	28
T18	1976	298
T19	11889	71
T20	3651	25
T21	482	6

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3576113	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3576113
T1	529	4
T2	4447	31
T3	1314	18
T4	115205	1549
T5	1048	21
T14	3429	28
T18	1976	298
T19	11889	62
T20	3651	62
T21	482	6

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1423026	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1423026
T1	529	4
T2	4447	47
T3	1314	18
T4	115205	1221
T5	1048	20
T14	3429	25
T18	1976	0
T19	11889	50
T20	3651	41
T21	482	11
T22	0	42

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3094556	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3094556
T1	529	4
T2	4447	8
T3	1314	18
T4	115205	1396
T5	1048	20
T14	3429	25
T18	1976	0
T19	11889	52
T20	3651	40
T21	482	11
T22	0	2763

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1442138	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1442138
T1	529	7
T2	4447	30
T3	1314	23
T4	115205	830
T5	1048	17
T14	3429	28
T18	1976	0
T19	11889	99
T20	3651	38
T21	482	8
T22	0	22

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3360329	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3360329
T1	529	7
T2	4447	17
T3	1314	23
T4	115205	3
T5	1048	17
T14	3429	28
T18	1976	0
T19	11889	59
T20	3651	15
T21	482	8
T22	0	1840

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1505127	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1505127
T1	529	5
T2	4447	51
T3	1314	9
T4	115205	1938
T5	1048	14
T14	3429	40
T18	1976	0
T19	11889	134
T20	3651	47
T21	482	9
T22	0	10

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3987197	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3987197
T1	529	5
T2	4447	23
T3	1314	9
T4	115205	246
T5	1048	14
T14	3429	40
T18	1976	0
T19	11889	73
T20	3651	49
T21	482	9
T22	0	2189

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1460760	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1460760
T1	529	2
T2	4447	53
T3	1314	13
T4	115205	1119
T5	1048	19
T14	3429	22
T18	1976	0
T19	11889	136
T20	3651	67
T21	482	6
T22	0	28

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	2947764	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	2947764
T1	529	2
T2	4447	13
T3	1314	13
T4	115205	25
T5	1048	19
T14	3429	22
T18	1976	0
T19	11889	112
T20	3651	31
T21	482	6
T22	0	1857

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1432410	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1432410
T1	529	4
T2	4447	43
T3	1314	21
T4	115205	555
T5	1048	18
T14	3429	23
T18	1976	277
T19	11889	59
T20	3651	15
T21	482	7

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	2690722	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	2690722
T1	529	4
T2	4447	17
T3	1314	21
T4	115205	1704
T5	1048	18
T14	3429	23
T18	1976	277
T19	11889	87
T20	3651	5
T21	482	7

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1419279	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1419279
T1	529	7
T2	4447	21
T3	1314	21
T4	115205	0
T5	1048	14
T14	3429	28
T15	0	65
T18	1976	0
T19	11889	78
T20	3651	10
T21	482	5
T22	0	49

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	2913301	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	2913301
T1	529	7
T2	4447	9
T3	1314	21
T4	115205	0
T5	1048	14
T14	3429	28
T15	0	65
T18	1976	0
T19	11889	125
T20	3651	2
T21	482	5
T22	0	2077

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1485556	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1485556
T1	529	7
T2	4447	36
T3	1314	11
T4	115205	245
T5	1048	27
T14	3429	29
T18	1976	427
T19	11889	154
T20	3651	6
T21	482	3

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	3168776	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	3168776
T1	529	7
T2	4447	15
T3	1314	11
T4	115205	1
T5	1048	27
T14	3429	29
T18	1976	427
T19	11889	128
T20	3651	19
T21	482	3

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1456744	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1456744
T1	529	5
T2	4447	13
T3	1314	12
T4	115205	1236
T5	1048	9
T14	3429	25
T18	1976	0
T19	11889	105
T20	3651	15
T21	482	9
T22	0	60

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	2778020	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	2778020
T1	529	5
T2	4447	6
T3	1314	12
T4	115205	242
T5	1048	9
T14	3429	25
T18	1976	0
T19	11889	100
T20	3651	8
T21	482	9
T22	0	2663

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	1523352	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	1523352
T1	529	11
T2	4447	43
T3	1314	24
T4	115205	519
T5	1048	13
T14	3429	27
T18	1976	0
T19	11889	107
T20	3651	40
T21	482	8
T22	0	14

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314508675	2687643	0	0
DepthKnown_A	314508675	314382128	0	0
RvalidKnown_A	314508675	314382128	0	0
WreadyKnown_A	314508675	314382128	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314508675	2687643
T1	529	11
T2	4447	26
T3	1314	24
T4	115205	932
T5	1048	13
T14	3429	27
T18	1976	0
T19	11889	95
T20	3651	32
T21	482	8
T22	0	677

DepthKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

RvalidKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

WreadyKnown_A

Name	Attempts	Real Successes
Total	314508675	314382128
T1	529	507
T2	4447	4404
T3	1314	1262
T4	115205	115131
T5	1048	1043
T14	3429	3349
T18	1976	1968
T19	11889	11843
T20	3651	3600
T21	482	467

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T14	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children