Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1685566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

265533

1

T1

11

T2

20

T3

165

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	660362	1			T1	35		T2	36		T3	350
values[0x0]	629745	1			T1	39		T2	49		T3	367
values[0x1]	660992	1			T1	33		T2	51		T3	375

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1305045	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

646054

1

T1

25

T2

41

T3

375

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7322	1			T1	9		T3	5		T11	6
valid_sources[0x01]	7674	1			T3	3		T11	6		T12	1
valid_sources[0x02]	7389	1			T3	3		T11	4		T12	8
valid_sources[0x03]	8075	1			T3	8		T11	12		T12	3
valid_sources[0x04]	9725	1			T2	68		T3	2		T11	6
valid_sources[0x05]	8874	1			T3	11		T11	3		T12	1
valid_sources[0x06]	7602	1			T11	7		T12	3		T15	13
valid_sources[0x07]	7261	1			T3	4		T11	5		T12	3
valid_sources[0x08]	6738	1			T3	2		T11	6		T12	3
valid_sources[0x09]	8039	1			T3	8		T11	13		T12	5
valid_sources[0x0a]	8944	1			T3	4		T11	8		T12	3
valid_sources[0x0b]	7176	1			T3	7		T11	4		T12	9
valid_sources[0x0c]	7992	1			T3	2		T11	6		T12	1
valid_sources[0x0d]	7834	1			T3	6		T11	7		T12	1
valid_sources[0x0e]	8038	1			T3	4		T11	7		T12	4
valid_sources[0x0f]	7179	1			T3	3		T11	8		T12	7
valid_sources[0x10]	7708	1			T3	5		T11	4		T12	5
valid_sources[0x11]	8690	1			T3	4		T11	5		T12	5
valid_sources[0x12]	7623	1			T3	4		T11	4		T12	2
valid_sources[0x13]	7491	1			T3	5		T11	4		T12	6
valid_sources[0x14]	7892	1			T3	3		T11	12		T12	3
valid_sources[0x15]	8987	1			T3	2		T11	5		T12	1
valid_sources[0x16]	7101	1			T3	1		T11	6		T12	4
valid_sources[0x17]	6744	1			T3	1		T11	13		T12	8
valid_sources[0x18]	7187	1			T3	3		T11	6		T12	1
valid_sources[0x19]	7545	1			T3	2		T11	4		T12	4
valid_sources[0x1a]	7293	1			T3	8		T11	13		T12	7
valid_sources[0x1b]	7291	1			T3	2		T11	10		T12	2
valid_sources[0x1c]	7550	1			T3	5		T11	6		T12	2
valid_sources[0x1d]	7231	1			T3	1		T11	6		T12	6
valid_sources[0x1e]	8029	1			T3	4		T11	2		T12	4
valid_sources[0x1f]	7352	1			T3	4		T12	4		T23	10
valid_sources[0x20]	7057	1			T1	22		T11	5		T12	6
valid_sources[0x21]	8372	1			T3	1		T11	10		T12	5
valid_sources[0x22]	7013	1			T3	9		T4	10		T11	6
valid_sources[0x23]	7143	1			T3	5		T11	11		T12	6
valid_sources[0x24]	7827	1			T11	3		T12	4		T15	29
valid_sources[0x25]	6788	1			T3	7		T11	2		T12	3
valid_sources[0x26]	8244	1			T3	5		T11	9		T12	7
valid_sources[0x27]	8224	1			T3	5		T11	6		T12	4
valid_sources[0x28]	6841	1			T3	6		T11	4		T19	2
valid_sources[0x29]	6918	1			T3	2		T11	2		T12	2
valid_sources[0x2a]	7480	1			T3	4		T11	7		T12	1
valid_sources[0x2b]	7804	1			T3	1		T11	6		T12	1
valid_sources[0x2c]	8573	1			T3	12		T11	7		T12	9
valid_sources[0x2d]	7675	1			T3	1		T11	6		T12	2
valid_sources[0x2e]	7624	1			T1	26		T3	6		T11	7
valid_sources[0x2f]	7344	1			T3	6		T11	7		T12	5
valid_sources[0x30]	7572	1			T3	5		T11	3		T12	6
valid_sources[0x31]	6878	1			T3	2		T11	4		T12	3
valid_sources[0x32]	8359	1			T11	5		T12	6		T18	1
valid_sources[0x33]	7752	1			T3	4		T11	8		T12	8
valid_sources[0x34]	8009	1			T3	3		T11	5		T12	3
valid_sources[0x35]	7405	1			T3	2		T11	7		T12	2
valid_sources[0x36]	7487	1			T3	5		T11	3		T12	5
valid_sources[0x37]	7616	1			T3	1		T11	9		T12	6
valid_sources[0x38]	8418	1			T3	8		T11	9		T15	10
valid_sources[0x39]	7866	1			T3	5		T11	7		T12	8
valid_sources[0x3a]	7120	1			T3	3		T11	4		T19	1
valid_sources[0x3b]	8956	1			T3	5		T11	11		T12	5
valid_sources[0x3c]	8121	1			T3	12		T11	8		T12	3
valid_sources[0x3d]	7395	1			T3	3		T11	5		T12	4
valid_sources[0x3e]	8326	1			T3	4		T11	6		T12	4
valid_sources[0x3f]	7860	1			T3	4		T11	5		T12	8
valid_sources[0x40]	7095	1			T3	5		T11	6		T12	4
valid_sources[0x41]	7670	1			T3	4		T11	11		T12	4
valid_sources[0x42]	8449	1			T3	4		T11	1		T12	4
valid_sources[0x43]	7551	1			T3	3		T11	4		T12	6
valid_sources[0x44]	7855	1			T3	1		T4	12		T11	1
valid_sources[0x45]	7668	1			T1	19		T3	4		T11	8
valid_sources[0x46]	7308	1			T3	6		T11	11		T12	6
valid_sources[0x47]	7287	1			T3	2		T11	10		T12	3
valid_sources[0x48]	7330	1			T3	6		T11	6		T12	7
valid_sources[0x49]	9513	1			T11	4		T12	3		T15	8
valid_sources[0x4a]	7281	1			T3	2		T11	10		T12	5
valid_sources[0x4b]	7422	1			T3	4		T11	7		T12	3
valid_sources[0x4c]	7521	1			T3	4		T11	4		T12	5
valid_sources[0x4d]	8477	1			T3	8		T11	10		T12	4
valid_sources[0x4e]	7506	1			T3	2		T11	8		T12	7
valid_sources[0x4f]	8840	1			T3	6		T11	8		T12	3
valid_sources[0x50]	7267	1			T3	8		T4	6		T11	11
valid_sources[0x51]	7826	1			T3	9		T11	5		T12	5
valid_sources[0x52]	7981	1			T3	8		T11	4		T12	3
valid_sources[0x53]	6926	1			T3	8		T4	5		T11	5
valid_sources[0x54]	7578	1			T3	4		T11	11		T12	4
valid_sources[0x55]	7058	1			T11	10		T12	4		T16	3
valid_sources[0x56]	7678	1			T3	4		T11	11		T12	7
valid_sources[0x57]	7435	1			T3	4		T11	2		T12	2
valid_sources[0x58]	7655	1			T3	5		T11	6		T12	3
valid_sources[0x59]	6949	1			T3	5		T11	10		T12	2
valid_sources[0x5a]	7771	1			T3	2		T11	7		T12	4
valid_sources[0x5b]	7270	1			T11	4		T12	6		T23	4
valid_sources[0x5c]	7319	1			T3	2		T4	2		T11	4
valid_sources[0x5d]	8476	1			T3	1		T11	7		T12	6
valid_sources[0x5e]	7706	1			T3	6		T11	6		T12	3
valid_sources[0x5f]	7242	1			T3	7		T4	11		T11	10
valid_sources[0x60]	7281	1			T3	4		T11	4		T12	2
valid_sources[0x61]	8821	1			T3	1		T11	6		T12	6
valid_sources[0x62]	7154	1			T3	2		T4	7		T11	4
valid_sources[0x63]	6899	1			T3	2		T11	4		T12	2
valid_sources[0x64]	8187	1			T3	5		T11	4		T12	4
valid_sources[0x65]	7470	1			T3	4		T11	7		T12	9
valid_sources[0x66]	8032	1			T3	4		T4	6		T11	7
valid_sources[0x67]	7661	1			T3	7		T11	5		T12	4
valid_sources[0x68]	7804	1			T3	4		T11	1		T12	6
valid_sources[0x69]	8616	1			T3	8		T11	6		T12	5
valid_sources[0x6a]	8373	1			T3	3		T11	5		T12	5
valid_sources[0x6b]	7404	1			T3	7		T11	3		T12	3
valid_sources[0x6c]	7429	1			T3	4		T11	5		T12	5
valid_sources[0x6d]	6991	1			T3	12		T11	6		T12	3
valid_sources[0x6e]	7109	1			T3	8		T11	4		T12	6
valid_sources[0x6f]	7767	1			T3	2		T11	13		T12	3
valid_sources[0x70]	6958	1			T3	6		T11	9		T12	1
valid_sources[0x71]	7537	1			T3	6		T11	8		T12	5
valid_sources[0x72]	7215	1			T3	1		T4	2		T11	2
valid_sources[0x73]	8096	1			T3	2		T11	5		T12	7
valid_sources[0x74]	7336	1			T3	9		T11	8		T12	1
valid_sources[0x75]	7013	1			T3	2		T11	4		T12	5
valid_sources[0x76]	7626	1			T3	11		T11	6		T12	4
valid_sources[0x77]	6973	1			T3	2		T11	9		T12	3
valid_sources[0x78]	6974	1			T3	11		T11	2		T12	2
valid_sources[0x79]	7397	1			T3	2		T11	6		T12	4
valid_sources[0x7a]	7776	1			T3	4		T11	7		T12	5
valid_sources[0x7b]	7368	1			T3	1		T11	4		T12	5
valid_sources[0x7c]	6674	1			T3	3		T11	11		T12	4
valid_sources[0x7d]	7674	1			T3	1		T4	29		T11	3
valid_sources[0x7e]	8339	1			T3	3		T11	6		T12	4
valid_sources[0x7f]	7562	1			T3	2		T11	7		T12	5
valid_sources[0x80]	9063	1			T3	2		T11	5		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28165

1

T1

2

T2

3

T3

12

values[0x0]

all_enables

biggest_size

209293

1

T1

9

T2

13

T3

131

values[0x1]

all_enables

biggest_size

28075

1

T2

4

T3

22

T4

5