Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	356496312	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	356496312
T1	134904	2747
T2	24192	665
T3	129920	5366
T4	5741456	102354
T11	2089696	43710
T12	1419040	29622
T15	2098432	30250
T16	29680	656
T17	18368	0
T18	193872	3414
T19	0	10493
T20	0	36

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	134904	134064
T2	24192	23184
T3	129920	128576
T4	5741456	5738656
T11	2089696	2087624
T12	1419040	1416520
T15	2098432	2094960
T16	29680	28056
T17	18368	12096
T18	193872	191856

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	134904	134064
T2	24192	23184
T3	129920	128576
T4	5741456	5738656
T11	2089696	2087624
T12	1419040	1416520
T15	2098432	2094960
T16	29680	28056
T17	18368	12096
T18	193872	191856

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	134904	134064
T2	24192	23184
T3	129920	128576
T4	5741456	5738656
T11	2089696	2087624
T12	1419040	1416520
T15	2098432	2094960
T16	29680	28056
T17	18368	12096
T18	193872	191856

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T11	56	56
T12	56	56
T15	56	56
T16	56	56
T17	56	56
T18	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	125668568	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	125668568
T1	2409	1282
T2	432	257
T3	2320	2092
T4	102526	100839
T11	37316	19651
T12	25340	11133
T15	37472	7660
T16	530	254
T17	328	0
T18	3462	1459
T19	0	4078

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	95162510	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	95162510
T1	2409	354
T2	432	136
T3	2320	1092
T4	102526	335
T11	37316	5662
T12	25340	9699
T15	37472	7471
T16	530	134
T17	328	0
T18	3462	488
T19	0	2139

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1571161	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1571161
T1	2409	26
T2	432	4
T3	2320	42
T4	102526	17
T11	37316	495
T12	25340	149
T15	37472	315
T16	530	5
T17	328	0
T18	3462	33
T19	0	82

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3462228	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3462228
T1	2409	9
T2	432	4
T3	2320	42
T4	102526	3
T11	37316	148
T12	25340	135
T15	37472	296
T16	530	5
T17	328	0
T18	3462	52
T19	0	82

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1533800	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1533800
T1	2409	1
T2	432	8
T3	2320	43
T4	102526	22
T11	37316	501
T12	25340	131
T15	37472	237
T16	530	6
T17	328	0
T18	3462	47
T19	0	79

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3440445	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3440445
T1	2409	1
T2	432	8
T3	2320	43
T4	102526	13
T11	37316	211
T12	25340	172
T15	37472	250
T16	530	6
T17	328	0
T18	3462	19
T19	0	79

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1502338	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1502338
T1	2409	30
T2	432	3
T3	2320	41
T4	102526	38
T11	37316	699
T12	25340	205
T15	37472	375
T16	530	4
T17	328	0
T18	3462	90
T19	0	74

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3400840	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3400840
T1	2409	27
T2	432	3
T3	2320	41
T4	102526	9
T11	37316	246
T12	25340	268
T15	37472	331
T16	530	4
T17	328	0
T18	3462	36
T19	0	74

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1536380	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1536380
T1	2409	19
T2	432	3
T3	2320	33
T4	102526	97
T11	37316	375
T12	25340	88
T15	37472	270
T16	530	7
T17	328	0
T18	3462	32
T19	0	83

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	2938212	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	2938212
T1	2409	13
T2	432	3
T3	2320	33
T4	102526	17
T11	37316	214
T12	25340	86
T15	37472	252
T16	530	7
T17	328	0
T18	3462	4
T19	0	83

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1495695	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1495695
T1	2409	6
T2	432	3
T3	2320	48
T4	102526	36
T11	37316	447
T12	25340	207
T15	37472	152
T16	530	7
T17	328	0
T18	3462	39
T19	0	94

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	4326703	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	4326703
T1	2409	13
T2	432	3
T3	2320	48
T4	102526	6
T11	37316	145
T12	25340	202
T15	37472	159
T16	530	7
T17	328	0
T18	3462	7
T19	0	94

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1592417	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1592417
T1	2409	33
T2	432	8
T3	2320	38
T4	102526	22
T11	37316	411
T12	25340	72
T15	37472	169
T16	530	7
T17	328	0
T18	3462	33
T19	0	68

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	4329844	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	4329844
T1	2409	28
T2	432	8
T3	2320	38
T4	102526	5
T11	37316	170
T12	25340	107
T15	37472	194
T16	530	7
T17	328	0
T18	3462	20
T19	0	68

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1528176	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1528176
T1	2409	40
T2	432	1
T3	2320	32
T4	102526	12
T11	37316	322
T12	25340	204
T15	37472	254
T16	530	5
T17	328	0
T18	3462	0
T19	0	83
T20	0	8

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	2971826	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	2971826
T1	2409	13
T2	432	1
T3	2320	32
T4	102526	4
T11	37316	159
T12	25340	175
T15	37472	278
T16	530	5
T17	328	0
T18	3462	0
T19	0	83
T20	0	8

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1553968	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1553968
T1	2409	54
T2	432	7
T3	2320	41
T4	102526	42
T11	37316	513
T12	25340	157
T15	37472	315
T16	530	4
T17	328	0
T18	3462	58
T19	0	78

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3413786	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3413786
T1	2409	23
T2	432	7
T3	2320	41
T4	102526	134
T11	37316	238
T12	25340	159
T15	37472	306
T16	530	4
T17	328	0
T18	3462	34
T19	0	78

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1554413	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1554413
T1	2409	29
T2	432	3
T3	2320	43
T4	102526	32
T11	37316	552
T12	25340	180
T15	37472	257
T16	530	4
T17	328	0
T18	3462	42
T19	0	90

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3453215	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3453215
T1	2409	10
T2	432	3
T3	2320	43
T4	102526	8
T11	37316	208
T12	25340	215
T15	37472	249
T16	530	4
T17	328	0
T18	3462	19
T19	0	90

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1526621	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1526621
T1	2409	38
T2	432	3
T3	2320	44
T4	102526	32
T11	37316	544
T12	25340	149
T15	37472	463
T16	530	1
T17	328	0
T18	3462	24
T19	0	72

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3701965	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3701965
T1	2409	15
T2	432	3
T3	2320	44
T4	102526	7
T11	37316	224
T12	25340	156
T15	37472	359
T16	530	1
T17	328	0
T18	3462	20
T19	0	72

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1520473	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1520473
T1	2409	42
T2	432	7
T3	2320	42
T4	102526	34
T11	37316	539
T12	25340	167
T15	37472	159
T16	530	4
T17	328	0
T18	3462	18
T19	0	90

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3242885	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3242885
T1	2409	8
T2	432	7
T3	2320	42
T4	102526	11
T11	37316	216
T12	25340	179
T15	37472	164
T16	530	4
T17	328	0
T18	3462	9
T19	0	90

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1554596	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1554596
T1	2409	13
T2	432	9
T3	2320	41
T4	102526	15
T11	37316	567
T12	25340	209
T15	37472	269
T16	530	2
T17	328	0
T18	3462	27
T19	0	67

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	2709904	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	2709904
T1	2409	8
T2	432	9
T3	2320	41
T4	102526	5
T11	37316	238
T12	25340	248
T15	37472	331
T16	530	2
T17	328	0
T18	3462	39
T19	0	67

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1531928	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1531928
T1	2409	49
T2	432	9
T3	2320	42
T4	102526	26
T11	37316	346
T12	25340	119
T15	37472	282
T16	530	7
T17	328	0
T18	3462	43
T19	0	87

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3474825	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3474825
T1	2409	19
T2	432	9
T3	2320	42
T4	102526	5
T11	37316	133
T12	25340	65
T15	37472	237
T16	530	7
T17	328	0
T18	3462	21
T19	0	87

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1511376	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1511376
T1	2409	10
T2	432	4
T3	2320	44
T4	102526	42
T11	37316	365
T12	25340	229
T15	37472	280
T16	530	4
T17	328	0
T18	3462	14
T19	0	68

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3153312	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3153312
T1	2409	2
T2	432	4
T3	2320	44
T4	102526	6
T11	37316	195
T12	25340	220
T15	37472	376
T16	530	4
T17	328	0
T18	3462	5
T19	0	68

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1599511	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1599511
T1	2409	36
T2	432	3
T3	2320	45
T4	102526	35
T11	37316	486
T12	25340	128
T15	37472	318
T16	530	4
T17	328	0
T18	3462	55
T19	0	71

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3669014	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3669014
T1	2409	26
T2	432	3
T3	2320	45
T4	102526	7
T11	37316	231
T12	25340	128
T15	37472	310
T16	530	4
T17	328	0
T18	3462	27
T19	0	71

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1545491	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1545491
T1	2409	44
T2	432	8
T3	2320	44
T4	102526	32
T11	37316	571
T12	25340	136
T15	37472	306
T16	530	4
T17	328	0
T18	3462	35
T19	0	71

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3399875	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3399875
T1	2409	17
T2	432	8
T3	2320	44
T4	102526	8
T11	37316	295
T12	25340	212
T15	37472	342
T16	530	4
T17	328	0
T18	3462	13
T19	0	71

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1582516	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1582516
T1	2409	47
T2	432	8
T3	2320	37
T4	102526	34
T11	37316	478
T12	25340	177
T15	37472	277
T16	530	1
T17	328	0
T18	3462	39
T19	0	84

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	4129079	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	4129079
T1	2409	4
T2	432	8
T3	2320	37
T4	102526	11
T11	37316	272
T12	25340	159
T15	37472	219
T16	530	1
T17	328	0
T18	3462	15
T19	0	84

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1581647	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1581647
T1	2409	62
T2	432	3
T3	2320	41
T4	102526	45
T11	37316	441
T12	25340	138
T15	37472	278
T16	530	6
T17	328	0
T18	3462	37
T19	0	98

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3043885	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3043885
T1	2409	38
T2	432	3
T3	2320	41
T4	102526	9
T11	37316	181
T12	25340	160
T15	37472	278
T16	530	6
T17	328	0
T18	3462	16
T19	0	98

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1506705	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1506705
T1	2409	18
T2	432	6
T3	2320	40
T4	102526	33
T11	37316	328
T12	25340	214
T15	37472	175
T16	530	4
T17	328	0
T18	3462	0
T19	0	88
T20	0	10

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3816346	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3816346
T1	2409	13
T2	432	6
T3	2320	40
T4	102526	7
T11	37316	169
T12	25340	196
T15	37472	175
T16	530	4
T17	328	0
T18	3462	0
T19	0	88
T20	0	10

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1540145	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1540145
T1	2409	21
T2	432	3
T3	2320	53
T4	102526	16
T11	37316	488
T12	25340	133
T15	37472	295
T16	530	3
T17	328	0
T18	3462	62
T19	0	92

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3473199	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3473199
T1	2409	7
T2	432	3
T3	2320	53
T4	102526	5
T11	37316	194
T12	25340	130
T15	37472	261
T16	530	3
T17	328	0
T18	3462	44
T19	0	92

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1563047	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1563047
T1	2409	13
T2	432	4
T3	2320	37
T4	102526	34
T11	37316	519
T12	25340	192
T15	37472	447
T16	530	6
T17	328	0
T18	3462	10
T19	0	73

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	4257480	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	4257480
T1	2409	2
T2	432	4
T3	2320	37
T4	102526	9
T11	37316	209
T12	25340	153
T15	37472	392
T16	530	6
T17	328	0
T18	3462	13
T19	0	73

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1511948	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1511948
T1	2409	23
T2	432	8
T3	2320	34
T4	102526	22
T11	37316	475
T12	25340	108
T15	37472	326
T16	530	5
T17	328	0
T18	3462	21
T19	0	67

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3311972	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3311972
T1	2409	6
T2	432	8
T3	2320	34
T4	102526	7
T11	37316	248
T12	25340	145
T15	37472	352
T16	530	5
T17	328	0
T18	3462	21
T19	0	67

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1548168	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1548168
T1	2409	13
T2	432	2
T3	2320	39
T4	102526	30
T11	37316	484
T12	25340	211
T15	37472	261
T16	530	12
T17	328	0
T18	3462	57
T19	0	82

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3463450	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3463450
T1	2409	5
T2	432	2
T3	2320	39
T4	102526	9
T11	37316	256
T12	25340	231
T15	37472	161
T16	530	12
T17	328	0
T18	3462	18
T19	0	82

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1513832	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1513832
T1	2409	23
T2	432	7
T3	2320	32
T4	102526	47
T11	37316	474
T12	25340	219
T15	37472	280
T16	530	6
T17	328	0
T18	3462	40
T19	0	70

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3401696	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3401696
T1	2409	12
T2	432	7
T3	2320	32
T4	102526	15
T11	37316	259
T12	25340	125
T15	37472	256
T16	530	6
T17	328	0
T18	3462	10
T19	0	70

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1523971	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1523971
T1	2409	16
T2	432	3
T3	2320	32
T4	102526	11
T11	37316	495
T12	25340	87
T15	37472	205
T16	530	5
T17	328	0
T18	3462	47
T19	0	77

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3026588	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3026588
T1	2409	12
T2	432	3
T3	2320	32
T4	102526	6
T11	37316	264
T12	25340	144
T15	37472	287
T16	530	5
T17	328	0
T18	3462	8
T19	0	77

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1568783	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1568783
T1	2409	34
T2	432	4
T3	2320	49
T4	102526	19
T11	37316	399
T12	25340	162
T15	37472	322
T16	530	5
T17	328	0
T18	3462	34
T19	0	72

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3479506	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3479506
T1	2409	6
T2	432	4
T3	2320	49
T4	102526	3
T11	37316	146
T12	25340	174
T15	37472	366
T16	530	5
T17	328	0
T18	3462	7
T19	0	72

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	1562922	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	1562922
T1	2409	17
T2	432	5
T3	2320	34
T4	102526	20
T11	37316	421
T12	25340	135
T15	37472	367
T16	530	6
T17	328	0
T18	3462	42
T19	0	78

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	325306657	3511126	0	0
DepthKnown_A	325306657	325181695	0	0
RvalidKnown_A	325306657	325181695	0	0
WreadyKnown_A	325306657	325181695	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	325306657	3511126
T1	2409	17
T2	432	5
T3	2320	34
T4	102526	6
T11	37316	193
T12	25340	140
T15	37472	284
T16	530	6
T17	328	0
T18	3462	11
T19	0	78

DepthKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

RvalidKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

WreadyKnown_A

Name	Attempts	Real Successes
Total	325306657	325181695
T1	2409	2394
T2	432	414
T3	2320	2296
T4	102526	102476
T11	37316	37279
T12	25340	25295
T15	37472	37410
T16	530	501
T17	328	216
T18	3462	3426

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T11	1	1
T12	1	1
T15	1	1
T16	1	1
T17	1	1
T18	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children