Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1652768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

259946

1

T1

15

T2

15

T3

194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	646702	1			T1	42		T2	39		T3	516
values[0x0]	617236	1			T1	42		T2	41		T3	526
values[0x1]	648776	1			T1	35		T2	45		T3	527

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1280350	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

632364

1

T1

36

T2

40

T3

471

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7676	1			T2	1		T15	19		T21	1
valid_sources[0x01]	6676	1			T1	2		T5	11		T16	1
valid_sources[0x02]	7419	1			T1	2		T3	5		T5	7
valid_sources[0x03]	8083	1			T1	1		T3	8		T5	15
valid_sources[0x04]	7848	1			T1	1		T5	10		T16	3
valid_sources[0x05]	7295	1			T1	1		T3	17		T5	8
valid_sources[0x06]	7617	1			T5	1		T16	8		T19	1
valid_sources[0x07]	6902	1			T5	9		T16	1		T15	20
valid_sources[0x08]	7418	1			T5	7		T16	4		T15	17
valid_sources[0x09]	7237	1			T1	6		T18	1		T5	16
valid_sources[0x0a]	7649	1			T3	7		T5	4		T16	11
valid_sources[0x0b]	7283	1			T5	8		T16	8		T14	1
valid_sources[0x0c]	7376	1			T1	1		T18	1		T5	5
valid_sources[0x0d]	9016	1			T3	12		T5	2		T16	2
valid_sources[0x0e]	6926	1			T3	2		T18	2		T5	5
valid_sources[0x0f]	7645	1			T5	5		T16	2		T19	1
valid_sources[0x10]	6801	1			T1	4		T5	10		T16	6
valid_sources[0x11]	7455	1			T18	2		T5	1		T16	2
valid_sources[0x12]	7194	1			T3	3		T5	1		T16	4
valid_sources[0x13]	7304	1			T1	6		T3	13		T5	4
valid_sources[0x14]	7290	1			T3	6		T5	7		T6	12
valid_sources[0x15]	7572	1			T1	1		T5	12		T15	15
valid_sources[0x16]	8528	1			T18	2		T5	9		T16	4
valid_sources[0x17]	7180	1			T3	5		T5	8		T6	18
valid_sources[0x18]	7439	1			T1	1		T3	17		T5	4
valid_sources[0x19]	7377	1			T3	3		T18	1		T5	13
valid_sources[0x1a]	7825	1			T2	5		T18	1		T5	4
valid_sources[0x1b]	6915	1			T1	2		T3	5		T5	11
valid_sources[0x1c]	7310	1			T18	1		T5	11		T16	3
valid_sources[0x1d]	6899	1			T1	2		T3	9		T5	22
valid_sources[0x1e]	7994	1			T3	13		T5	2		T16	10
valid_sources[0x1f]	7081	1			T3	9		T5	4		T19	1
valid_sources[0x20]	8595	1			T1	1		T3	8		T18	2
valid_sources[0x21]	6760	1			T3	31		T5	13		T16	8
valid_sources[0x22]	7629	1			T2	8		T3	6		T5	7
valid_sources[0x23]	7830	1			T5	1		T16	2		T14	1
valid_sources[0x24]	7311	1			T3	9		T5	9		T16	12
valid_sources[0x25]	8046	1			T3	21		T5	5		T16	2
valid_sources[0x26]	9748	1			T1	3		T3	3		T5	4
valid_sources[0x27]	7615	1			T18	1		T5	10		T6	18
valid_sources[0x28]	7731	1			T5	6		T16	6		T19	2
valid_sources[0x29]	7042	1			T1	1		T5	12		T16	10
valid_sources[0x2a]	7202	1			T3	6		T18	2		T5	4
valid_sources[0x2b]	7351	1			T3	1		T18	2		T5	8
valid_sources[0x2c]	8217	1			T1	1		T3	22		T5	9
valid_sources[0x2d]	7626	1			T3	18		T5	9		T16	4
valid_sources[0x2e]	7220	1			T3	32		T5	14		T19	1
valid_sources[0x2f]	8577	1			T1	5		T18	1		T5	5
valid_sources[0x30]	8372	1			T18	1		T5	10		T6	13
valid_sources[0x31]	7214	1			T3	11		T5	2		T16	16
valid_sources[0x32]	7106	1			T5	8		T19	1		T15	10
valid_sources[0x33]	7864	1			T5	7		T16	9		T15	12
valid_sources[0x34]	6723	1			T5	3		T16	5		T19	1
valid_sources[0x35]	7368	1			T3	1		T5	11		T16	8
valid_sources[0x36]	7416	1			T3	6		T5	5		T16	5
valid_sources[0x37]	7421	1			T3	3		T5	3		T6	12
valid_sources[0x38]	7521	1			T3	17		T5	16		T16	22
valid_sources[0x39]	8087	1			T3	44		T18	2		T5	7
valid_sources[0x3a]	7411	1			T3	2		T5	5		T16	8
valid_sources[0x3b]	7120	1			T1	4		T4	2		T18	1
valid_sources[0x3c]	7415	1			T3	1		T5	4		T16	15
valid_sources[0x3d]	7269	1			T1	2		T5	6		T16	4
valid_sources[0x3e]	7041	1			T5	2		T19	1		T15	19
valid_sources[0x3f]	7866	1			T2	6		T3	18		T18	1
valid_sources[0x40]	6577	1			T3	1		T5	6		T14	3
valid_sources[0x41]	7645	1			T2	2		T3	6		T5	2
valid_sources[0x42]	7488	1			T2	2		T16	4		T19	1
valid_sources[0x43]	7282	1			T1	1		T2	1		T5	4
valid_sources[0x44]	6884	1			T3	6		T5	8		T6	13
valid_sources[0x45]	6927	1			T1	4		T5	8		T16	5
valid_sources[0x46]	8051	1			T1	1		T2	3		T3	3
valid_sources[0x47]	7336	1			T3	22		T5	11		T16	11
valid_sources[0x48]	7278	1			T3	9		T5	12		T6	7
valid_sources[0x49]	7383	1			T5	3		T16	23		T19	1
valid_sources[0x4a]	6978	1			T2	2		T5	1		T16	2
valid_sources[0x4b]	8037	1			T3	4		T5	9		T16	1
valid_sources[0x4c]	7286	1			T2	1		T3	2		T5	8
valid_sources[0x4d]	6885	1			T3	4		T5	4		T16	1
valid_sources[0x4e]	7150	1			T3	32		T5	6		T16	6
valid_sources[0x4f]	8190	1			T1	1		T3	11		T5	5
valid_sources[0x50]	7044	1			T5	12		T16	24		T15	12
valid_sources[0x51]	7547	1			T3	3		T18	1		T5	15
valid_sources[0x52]	7234	1			T3	22		T5	2		T16	23
valid_sources[0x53]	8929	1			T1	1		T18	3		T5	3
valid_sources[0x54]	7275	1			T2	1		T3	35		T18	1
valid_sources[0x55]	7802	1			T3	8		T5	6		T16	24
valid_sources[0x56]	7306	1			T18	1		T5	4		T16	7
valid_sources[0x57]	7173	1			T3	7		T5	10		T19	1
valid_sources[0x58]	6886	1			T2	4		T3	9		T5	14
valid_sources[0x59]	7218	1			T2	1		T3	11		T5	15
valid_sources[0x5a]	6873	1			T1	7		T3	7		T18	2
valid_sources[0x5b]	7688	1			T3	4		T18	2		T5	13
valid_sources[0x5c]	7344	1			T1	4		T5	5		T16	3
valid_sources[0x5d]	6865	1			T5	1		T16	13		T15	22
valid_sources[0x5e]	7606	1			T1	1		T3	21		T5	2
valid_sources[0x5f]	8429	1			T3	8		T5	3		T16	17
valid_sources[0x60]	7257	1			T5	6		T6	6		T16	11
valid_sources[0x61]	6755	1			T3	8		T18	1		T5	7
valid_sources[0x62]	7004	1			T18	3		T5	9		T14	4
valid_sources[0x63]	8225	1			T3	1		T18	1		T5	3
valid_sources[0x64]	7448	1			T5	17		T19	1		T14	1
valid_sources[0x65]	7383	1			T2	3		T18	3		T5	6
valid_sources[0x66]	7280	1			T1	1		T3	12		T5	7
valid_sources[0x67]	6949	1			T1	1		T3	3		T5	3
valid_sources[0x68]	7055	1			T5	6		T6	13		T16	3
valid_sources[0x69]	7255	1			T3	6		T5	2		T16	22
valid_sources[0x6a]	6925	1			T5	4		T16	8		T15	23
valid_sources[0x6b]	7607	1			T2	8		T3	22		T5	12
valid_sources[0x6c]	7470	1			T1	1		T18	1		T5	5
valid_sources[0x6d]	7605	1			T18	1		T5	6		T16	13
valid_sources[0x6e]	7747	1			T5	13		T6	15		T16	5
valid_sources[0x6f]	7294	1			T3	2		T5	8		T16	5
valid_sources[0x70]	7327	1			T5	3		T16	1		T15	12
valid_sources[0x71]	7408	1			T3	18		T5	4		T16	5
valid_sources[0x72]	7111	1			T1	1		T2	6		T3	1
valid_sources[0x73]	7403	1			T1	1		T2	1		T3	39
valid_sources[0x74]	7782	1			T5	16		T16	6		T19	1
valid_sources[0x75]	6890	1			T2	1		T5	1		T16	6
valid_sources[0x76]	7434	1			T3	12		T5	9		T16	8
valid_sources[0x77]	7273	1			T2	2		T3	17		T5	4
valid_sources[0x78]	7631	1			T1	1		T2	3		T3	1
valid_sources[0x79]	7525	1			T18	1		T5	10		T16	1
valid_sources[0x7a]	7228	1			T18	1		T5	20		T16	19
valid_sources[0x7b]	7524	1			T18	2		T5	12		T16	18
valid_sources[0x7c]	6728	1			T5	2		T16	8		T19	1
valid_sources[0x7d]	7215	1			T2	1		T3	11		T18	1
valid_sources[0x7e]	8085	1			T1	1		T3	1		T5	8
valid_sources[0x7f]	6785	1			T3	1		T18	2		T5	9
valid_sources[0x80]	6704	1			T1	1		T3	13		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27458

1

T1

3

T2

1

T3

19

values[0x0]

all_enables

biggest_size

204696

1

T1

12

T2

11

T3

157

values[0x1]

all_enables

biggest_size

27792

1

T2

3

T3

18

T18

3