Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	331955554	0	0
DataKnown_AKnownEnable	2147483647	2147483647	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	331955554
T1	27328	583
T2	29176	615
T3	188048	7693
T4	47824	914
T5	3008376	70261
T6	1315160	18820
T14	30352	939
T16	227304	7897
T18	287616	12009
T19	4152736	74000
T20	0	96

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27328	25648
T2	29176	26992
T3	188048	184856
T4	47824	44296
T5	3008376	3007088
T6	1315160	1313704
T14	30352	28840
T16	227304	226240
T18	287616	283976
T19	4152736	4150328

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27328	25648
T2	29176	26992
T3	188048	184856
T4	47824	44296
T5	3008376	3007088
T6	1315160	1313704
T14	30352	28840
T16	227304	226240
T18	287616	283976
T19	4152736	4150328

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27328	25648
T2	29176	26992
T3	188048	184856
T4	47824	44296
T5	3008376	3007088
T6	1315160	1313704
T14	30352	28840
T16	227304	226240
T18	287616	283976
T19	4152736	4150328

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27328	25648
T2	29176	26992
T3	188048	184856
T4	47824	44296
T5	3008376	3007088
T6	1315160	1313704
T14	30352	28840
T16	227304	226240
T18	287616	283976
T19	4152736	4150328

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T6	56	56
T14	56	56
T16	56	56
T18	56	56
T19	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	121811239	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	121811239
T1	488	226
T2	521	240
T3	3358	2990
T4	854	453
T5	53721	27686
T6	23485	4507
T14	542	363
T16	4059	3905
T18	5136	4682
T19	74156	72481

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	85205475	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	85205475
T1	488	119
T2	521	125
T3	3358	1569
T4	854	233
T5	53721	14109
T6	23485	4904
T14	542	192
T16	4059	1994
T18	5136	2443
T19	74156	408

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1489601	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1489601
T1	488	4
T2	521	3
T3	3358	41
T4	854	1
T5	53721	633
T6	23485	173
T14	542	6
T16	4059	35
T18	5136	97
T19	74156	27

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2976291	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2976291
T1	488	4
T2	521	3
T3	3358	41
T4	854	1
T5	53721	709
T6	23485	207
T14	542	6
T16	4059	35
T18	5136	97
T19	74156	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1511472	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1511472
T1	488	4
T2	521	5
T3	3358	68
T4	854	5
T5	53721	577
T6	23485	164
T14	542	0
T16	4059	29
T18	5136	98
T19	74156	49
T20	0	24

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3640178	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3640178
T1	488	4
T2	521	5
T3	3358	68
T4	854	5
T5	53721	497
T6	23485	164
T14	542	0
T16	4059	29
T18	5136	98
T19	74156	8
T20	0	19

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1547558	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1547558
T1	488	4
T2	521	7
T3	3358	58
T4	854	3
T5	53721	419
T6	23485	109
T14	542	11
T16	4059	51
T18	5136	93
T19	74156	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3353175	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3353175
T1	488	4
T2	521	7
T3	3358	58
T4	854	3
T5	53721	423
T6	23485	191
T14	542	11
T16	4059	51
T18	5136	93
T19	74156	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1464937	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1464937
T1	488	7
T2	521	5
T3	3358	45
T4	854	6
T5	53721	573
T6	23485	174
T14	542	6
T16	4059	36
T18	5136	91
T19	74156	18

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2924330	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2924330
T1	488	7
T2	521	5
T3	3358	45
T4	854	6
T5	53721	453
T6	23485	256
T14	542	6
T16	4059	36
T18	5136	91
T19	74156	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1501875	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1501875
T1	488	6
T2	521	1
T3	3358	72
T4	854	3
T5	53721	635
T6	23485	129
T14	542	13
T16	4059	32
T18	5136	84
T19	74156	11

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3221891	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3221891
T1	488	6
T2	521	1
T3	3358	72
T4	854	3
T5	53721	540
T6	23485	132
T14	542	13
T16	4059	32
T18	5136	84
T19	74156	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1492521	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1492521
T1	488	4
T2	521	5
T3	3358	69
T4	854	3
T5	53721	600
T6	23485	173
T14	542	5
T16	4059	33
T18	5136	97
T19	74156	24

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2950026	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2950026
T1	488	4
T2	521	5
T3	3358	69
T4	854	3
T5	53721	487
T6	23485	162
T14	542	5
T16	4059	33
T18	5136	97
T19	74156	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1531171	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1531171
T1	488	3
T2	521	5
T3	3358	48
T4	854	5
T5	53721	558
T6	23485	149
T14	542	9
T16	4059	41
T18	5136	118
T19	74156	52

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2837092	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2837092
T1	488	3
T2	521	5
T3	3358	48
T4	854	5
T5	53721	526
T6	23485	145
T14	542	9
T16	4059	41
T18	5136	118
T19	74156	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1512683	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1512683
T1	488	9
T2	521	5
T3	3358	57
T4	854	5
T5	53721	480
T6	23485	189
T14	542	11
T16	4059	39
T18	5136	95
T19	74156	36

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3486663	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3486663
T1	488	9
T2	521	5
T3	3358	57
T4	854	5
T5	53721	504
T6	23485	171
T14	542	11
T16	4059	39
T18	5136	95
T19	74156	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1513592	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1513592
T1	488	6
T2	521	6
T3	3358	57
T4	854	3
T5	53721	495
T6	23485	111
T14	542	6
T16	4059	57
T18	5136	88
T19	74156	42

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3199252	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3199252
T1	488	6
T2	521	6
T3	3358	57
T4	854	3
T5	53721	652
T6	23485	181
T14	542	6
T16	4059	57
T18	5136	88
T19	74156	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1534525	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1534525
T1	488	2
T2	521	4
T3	3358	61
T4	854	6
T5	53721	385
T6	23485	242
T14	542	8
T16	4059	23
T18	5136	88
T19	74156	32

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2896264	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2896264
T1	488	2
T2	521	4
T3	3358	61
T4	854	6
T5	53721	384
T6	23485	169
T14	542	8
T16	4059	23
T18	5136	88
T19	74156	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1459483	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1459483
T1	488	3
T2	521	1
T3	3358	60
T4	854	3
T5	53721	658
T6	23485	227
T14	542	11
T16	4059	36
T18	5136	74
T19	74156	25

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2612728	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2612728
T1	488	3
T2	521	1
T3	3358	60
T4	854	3
T5	53721	574
T6	23485	218
T14	542	11
T16	4059	36
T18	5136	74
T19	74156	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1462944	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1462944
T1	488	3
T2	521	6
T3	3358	58
T4	854	1
T5	53721	491
T6	23485	210
T14	542	8
T16	4059	30
T18	5136	99
T19	74156	26

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2745141	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2745141
T1	488	3
T2	521	6
T3	3358	58
T4	854	1
T5	53721	489
T6	23485	260
T14	542	8
T16	4059	30
T18	5136	99
T19	74156	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1525778	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1525778
T1	488	7
T2	521	3
T3	3358	52
T4	854	6
T5	53721	521
T6	23485	142
T14	542	12
T16	4059	37
T18	5136	92
T19	74156	38

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3657745	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3657745
T1	488	7
T2	521	3
T3	3358	52
T4	854	6
T5	53721	618
T6	23485	204
T14	542	12
T16	4059	37
T18	5136	92
T19	74156	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1564430	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1564430
T1	488	7
T2	521	2
T3	3358	70
T4	854	6
T5	53721	523
T6	23485	219
T14	542	6
T16	4059	36
T18	5136	103
T19	74156	29

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3609911	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3609911
T1	488	7
T2	521	2
T3	3358	70
T4	854	6
T5	53721	571
T6	23485	291
T14	542	6
T16	4059	36
T18	5136	103
T19	74156	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1513230	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1513230
T1	488	6
T2	521	5
T3	3358	55
T4	854	8
T5	53721	478
T6	23485	168
T14	542	4
T16	4059	33
T18	5136	90
T19	74156	19

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3262502	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3262502
T1	488	6
T2	521	5
T3	3358	55
T4	854	8
T5	53721	441
T6	23485	168
T14	542	4
T16	4059	33
T18	5136	90
T19	74156	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1564571	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1564571
T1	488	3
T2	521	5
T3	3358	54
T4	854	7
T5	53721	401
T6	23485	118
T14	542	2
T16	4059	41
T18	5136	71
T19	74156	26

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2769590	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2769590
T1	488	3
T2	521	5
T3	3358	54
T4	854	7
T5	53721	403
T6	23485	116
T14	542	2
T16	4059	41
T18	5136	71
T19	74156	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1527527	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1527527
T1	488	4
T2	521	4
T3	3358	59
T4	854	3
T5	53721	590
T6	23485	190
T14	542	6
T16	4059	28
T18	5136	88
T19	74156	28

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3450298	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3450298
T1	488	4
T2	521	4
T3	3358	59
T4	854	3
T5	53721	533
T6	23485	250
T14	542	6
T16	4059	28
T18	5136	88
T19	74156	265

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1537636	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1537636
T1	488	2
T2	521	5
T3	3358	66
T4	854	3
T5	53721	664
T6	23485	134
T14	542	8
T16	4059	39
T18	5136	90
T19	74156	21

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2992843	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2992843
T1	488	2
T2	521	5
T3	3358	66
T4	854	3
T5	53721	541
T6	23485	168
T14	542	8
T16	4059	39
T18	5136	90
T19	74156	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1529630	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1529630
T1	488	3
T2	521	6
T3	3358	46
T4	854	1
T5	53721	530
T6	23485	77
T14	542	6
T16	4059	33
T18	5136	101
T19	74156	29

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3180558	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3180558
T1	488	3
T2	521	6
T3	3358	46
T4	854	1
T5	53721	590
T6	23485	112
T14	542	6
T16	4059	33
T18	5136	101
T19	74156	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1554883	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1554883
T1	488	1
T2	521	1
T3	3358	52
T4	854	8
T5	53721	414
T6	23485	173
T14	542	5
T16	4059	47
T18	5136	85
T19	74156	20

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3649268	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3649268
T1	488	1
T2	521	1
T3	3358	52
T4	854	8
T5	53721	485
T6	23485	152
T14	542	5
T16	4059	47
T18	5136	85
T19	74156	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1470852	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1470852
T1	488	5
T2	521	1
T3	3358	68
T4	854	5
T5	53721	421
T6	23485	118
T14	542	5
T16	4059	39
T18	5136	71
T19	74156	18

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2327332	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2327332
T1	488	5
T2	521	1
T3	3358	68
T4	854	5
T5	53721	466
T6	23485	95
T14	542	5
T16	4059	39
T18	5136	71
T19	74156	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1500627	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1500627
T1	488	3
T2	521	7
T3	3358	46
T4	854	5
T5	53721	664
T6	23485	199
T14	542	6
T16	4059	42
T18	5136	103
T19	74156	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2768613	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2768613
T1	488	3
T2	521	7
T3	3358	46
T4	854	5
T5	53721	530
T6	23485	253
T14	542	6
T16	4059	42
T18	5136	103
T19	74156	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1465830	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1465830
T1	488	4
T2	521	9
T3	3358	61
T4	854	0
T5	53721	544
T6	23485	192
T14	542	9
T16	4059	35
T18	5136	83
T19	74156	19
T20	0	26

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3094745	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3094745
T1	488	4
T2	521	9
T3	3358	61
T4	854	0
T5	53721	469
T6	23485	140
T14	542	9
T16	4059	35
T18	5136	83
T19	74156	2
T20	0	27

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1468160	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1468160
T1	488	3
T2	521	5
T3	3358	67
T4	854	6
T5	53721	576
T6	23485	196
T14	542	10
T16	4059	42
T18	5136	82
T19	74156	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2979341	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2979341
T1	488	3
T2	521	5
T3	3358	67
T4	854	6
T5	53721	630
T6	23485	244
T14	542	10
T16	4059	42
T18	5136	82
T19	74156	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1570037	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1570037
T1	488	6
T2	521	7
T3	3358	48
T4	854	3
T5	53721	644
T6	23485	133
T14	542	4
T16	4059	30
T18	5136	84
T19	74156	24

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3510146	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3510146
T1	488	6
T2	521	7
T3	3358	48
T4	854	3
T5	53721	567
T6	23485	176
T14	542	4
T16	4059	30
T18	5136	84
T19	74156	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1509662	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1509662
T1	488	5
T2	521	7
T3	3358	66
T4	854	4
T5	53721	461
T6	23485	165
T14	542	9
T16	4059	41
T18	5136	85
T19	74156	16

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	2850587	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	2850587
T1	488	5
T2	521	7
T3	3358	66
T4	854	4
T5	53721	465
T6	23485	127
T14	542	9
T16	4059	41
T18	5136	85
T19	74156	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	1501929	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	1501929
T1	488	5
T2	521	5
T3	3358	63
T4	854	5
T5	53721	426
T6	23485	232
T14	542	6
T16	4059	34
T18	5136	92
T19	74156	33

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	302618758	3165186	0	0
DataKnown_AKnownEnable	302618758	302503700	0	0
DepthKnown_A	302618758	302503700	0	0
RvalidKnown_A	302618758	302503700	0	0
WreadyKnown_A	302618758	302503700	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	302618758	3165186
T1	488	5
T2	521	5
T3	3358	63
T4	854	5
T5	53721	558
T6	23485	151
T14	542	6
T16	4059	34
T18	5136	92
T19	74156	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

DepthKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

RvalidKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

WreadyKnown_A

Name	Attempts	Real Successes
Total	302618758	302503700
T1	488	458
T2	521	482
T3	3358	3301
T4	854	791
T5	53721	53698
T6	23485	23459
T14	542	515
T16	4059	4040
T18	5136	5071
T19	74156	74113

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T6	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children