Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1864235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

293917

1

T1

22

T2

16

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	729814	1			T1	42		T2	34		T3	49
values[0x0]	699151	1			T1	52		T2	36		T3	51
values[0x1]	729187	1			T1	42		T2	32		T3	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1444861	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

713291

1

T1

49

T2

33

T3

56

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8155	1			T16	1		T24	2		T25	4
valid_sources[0x01]	7758	1			T16	1		T25	10		T18	1
valid_sources[0x02]	8137	1			T4	1		T16	7		T24	2
valid_sources[0x03]	7964	1			T4	10		T16	1		T24	5
valid_sources[0x04]	8402	1			T1	4		T16	3		T24	1
valid_sources[0x05]	10283	1			T16	3		T17	11		T24	2
valid_sources[0x06]	8240	1			T16	2		T17	6		T25	11
valid_sources[0x07]	8958	1			T4	6		T16	1		T24	8
valid_sources[0x08]	8934	1			T4	4		T16	2		T25	11
valid_sources[0x09]	7572	1			T1	12		T16	1		T24	2
valid_sources[0x0a]	8550	1			T2	4		T24	2		T25	9
valid_sources[0x0b]	8777	1			T2	2		T16	1		T25	8
valid_sources[0x0c]	9031	1			T4	12		T17	4		T25	12
valid_sources[0x0d]	8855	1			T4	3		T16	4		T25	14
valid_sources[0x0e]	7767	1			T2	1		T16	2		T17	8
valid_sources[0x0f]	8826	1			T17	1		T25	9		T19	1
valid_sources[0x10]	7697	1			T16	1		T24	2		T25	5
valid_sources[0x11]	9281	1			T16	5		T25	3		T29	4
valid_sources[0x12]	10092	1			T1	14		T4	1		T16	3
valid_sources[0x13]	9259	1			T2	1		T16	1		T24	1
valid_sources[0x14]	8154	1			T16	1		T23	85		T25	9
valid_sources[0x15]	8027	1			T4	4		T16	1		T17	4
valid_sources[0x16]	8541	1			T3	5		T17	18		T25	6
valid_sources[0x17]	8095	1			T16	2		T24	3		T25	7
valid_sources[0x18]	7971	1			T2	2		T16	2		T17	3
valid_sources[0x19]	7329	1			T1	5		T16	1		T25	7
valid_sources[0x1a]	7851	1			T2	1		T16	3		T25	11
valid_sources[0x1b]	8318	1			T4	1		T16	1		T24	2
valid_sources[0x1c]	8329	1			T16	5		T24	3		T25	8
valid_sources[0x1d]	8364	1			T16	2		T24	3		T25	16
valid_sources[0x1e]	8434	1			T16	1		T24	1		T25	7
valid_sources[0x1f]	8785	1			T16	1		T24	1		T25	7
valid_sources[0x20]	8079	1			T16	6		T25	11		T18	9
valid_sources[0x21]	8391	1			T2	1		T4	1		T16	3
valid_sources[0x22]	8791	1			T2	1		T16	3		T24	2
valid_sources[0x23]	8308	1			T16	2		T24	1		T25	11
valid_sources[0x24]	8142	1			T25	7		T21	8		T29	3
valid_sources[0x25]	8449	1			T1	6		T16	2		T25	8
valid_sources[0x26]	8077	1			T25	8		T21	12		T29	3
valid_sources[0x27]	8526	1			T2	1		T16	1		T25	4
valid_sources[0x28]	7800	1			T2	5		T3	20		T16	1
valid_sources[0x29]	8531	1			T4	1		T16	1		T25	6
valid_sources[0x2a]	8197	1			T16	2		T24	4		T25	13
valid_sources[0x2b]	8678	1			T4	2		T16	3		T24	5
valid_sources[0x2c]	8598	1			T2	1		T16	2		T17	10
valid_sources[0x2d]	8481	1			T4	13		T16	1		T17	13
valid_sources[0x2e]	8218	1			T16	1		T17	15		T24	2
valid_sources[0x2f]	8278	1			T2	3		T4	1		T16	1
valid_sources[0x30]	8484	1			T1	10		T16	3		T24	1
valid_sources[0x31]	8373	1			T16	3		T25	7		T21	7
valid_sources[0x32]	7740	1			T1	3		T16	1		T25	9
valid_sources[0x33]	8788	1			T16	4		T25	6		T21	15
valid_sources[0x34]	8582	1			T24	4		T25	5		T29	3
valid_sources[0x35]	9034	1			T16	1		T25	4		T18	2
valid_sources[0x36]	8941	1			T16	1		T24	3		T25	7
valid_sources[0x37]	8113	1			T16	1		T24	2		T25	7
valid_sources[0x38]	8763	1			T16	1		T25	14		T29	3
valid_sources[0x39]	8255	1			T16	5		T25	9		T29	3
valid_sources[0x3a]	8305	1			T16	5		T24	1		T25	4
valid_sources[0x3b]	8677	1			T1	16		T16	1		T25	5
valid_sources[0x3c]	8681	1			T16	2		T24	1		T25	3
valid_sources[0x3d]	8645	1			T16	2		T25	3		T19	1
valid_sources[0x3e]	8514	1			T24	1		T25	3		T21	9
valid_sources[0x3f]	7784	1			T16	2		T17	4		T24	1
valid_sources[0x40]	9120	1			T16	2		T25	22		T29	2
valid_sources[0x41]	8009	1			T2	1		T16	1		T17	6
valid_sources[0x42]	8730	1			T4	1		T16	2		T24	1
valid_sources[0x43]	8330	1			T25	18		T18	9		T29	3
valid_sources[0x44]	8499	1			T16	3		T24	1		T25	13
valid_sources[0x45]	7803	1			T16	2		T25	6		T18	11
valid_sources[0x46]	8057	1			T16	1		T25	12		T18	4
valid_sources[0x47]	7895	1			T16	2		T25	13		T21	7
valid_sources[0x48]	7865	1			T16	1		T25	10		T21	20
valid_sources[0x49]	8105	1			T25	8		T21	11		T19	1
valid_sources[0x4a]	8836	1			T2	1		T4	3		T25	14
valid_sources[0x4b]	8016	1			T2	1		T24	1		T25	8
valid_sources[0x4c]	8807	1			T4	4		T16	1		T25	5
valid_sources[0x4d]	8370	1			T16	1		T17	1		T24	4
valid_sources[0x4e]	9261	1			T4	6		T16	2		T24	1
valid_sources[0x4f]	8697	1			T4	1		T16	4		T24	2
valid_sources[0x50]	8787	1			T16	4		T25	10		T21	11
valid_sources[0x51]	8003	1			T3	11		T16	2		T24	2
valid_sources[0x52]	8358	1			T16	3		T25	3		T21	11
valid_sources[0x53]	9138	1			T16	1		T17	11		T25	5
valid_sources[0x54]	7649	1			T25	5		T19	1		T29	3
valid_sources[0x55]	8633	1			T24	6		T25	6		T29	2
valid_sources[0x56]	8409	1			T16	3		T25	9		T29	3
valid_sources[0x57]	8384	1			T24	6		T25	4		T29	3
valid_sources[0x58]	8565	1			T16	4		T25	11		T21	6
valid_sources[0x59]	8209	1			T16	1		T24	2		T25	13
valid_sources[0x5a]	8109	1			T16	2		T24	1		T25	14
valid_sources[0x5b]	8458	1			T16	1		T17	5		T25	6
valid_sources[0x5c]	8703	1			T16	4		T23	53		T24	4
valid_sources[0x5d]	8456	1			T24	6		T25	12		T29	3
valid_sources[0x5e]	9288	1			T16	1		T25	8		T19	1
valid_sources[0x5f]	8738	1			T16	1		T25	6		T29	3
valid_sources[0x60]	8040	1			T4	8		T17	6		T24	8
valid_sources[0x61]	9065	1			T2	2		T16	2		T17	12
valid_sources[0x62]	8078	1			T16	2		T24	1		T25	10
valid_sources[0x63]	8986	1			T16	3		T17	1		T24	4
valid_sources[0x64]	8590	1			T4	1		T16	3		T24	2
valid_sources[0x65]	7989	1			T16	2		T17	5		T25	8
valid_sources[0x66]	8181	1			T2	1		T4	2		T16	2
valid_sources[0x67]	8591	1			T2	1		T4	1		T16	6
valid_sources[0x68]	8717	1			T16	1		T17	2		T24	6
valid_sources[0x69]	8673	1			T16	1		T24	1		T25	11
valid_sources[0x6a]	8926	1			T16	1		T25	5		T29	3
valid_sources[0x6b]	8382	1			T16	4		T24	7		T25	6
valid_sources[0x6c]	7767	1			T16	2		T17	6		T25	9
valid_sources[0x6d]	8400	1			T25	10		T21	12		T29	2
valid_sources[0x6e]	7798	1			T16	3		T17	1		T24	5
valid_sources[0x6f]	8000	1			T24	5		T25	1		T29	2
valid_sources[0x70]	8328	1			T24	4		T25	4		T29	2
valid_sources[0x71]	8119	1			T16	2		T25	9		T21	14
valid_sources[0x72]	8783	1			T16	2		T25	6		T21	12
valid_sources[0x73]	8314	1			T24	2		T25	9		T29	2
valid_sources[0x74]	7793	1			T1	5		T4	1		T16	1
valid_sources[0x75]	7943	1			T16	3		T25	15		T19	1
valid_sources[0x76]	7591	1			T2	7		T16	4		T25	19
valid_sources[0x77]	8466	1			T2	1		T16	3		T24	1
valid_sources[0x78]	8544	1			T4	8		T16	2		T24	2
valid_sources[0x79]	8654	1			T2	3		T16	1		T24	1
valid_sources[0x7a]	8223	1			T16	3		T25	3		T21	9
valid_sources[0x7b]	8686	1			T1	6		T16	2		T17	10
valid_sources[0x7c]	8703	1			T4	3		T16	1		T25	12
valid_sources[0x7d]	8465	1			T4	3		T17	3		T24	1
valid_sources[0x7e]	9356	1			T24	1		T25	6		T29	3
valid_sources[0x7f]	9000	1			T16	3		T17	3		T24	2
valid_sources[0x80]	9370	1			T16	2		T17	2		T24	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30845

1

T1

2

T3

2

T4

3

values[0x0]

all_enables

biggest_size

232277

1

T1

17

T2

15

T3

18

values[0x1]

all_enables

biggest_size

30795

1

T1

3

T2

1

T3

3