Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	331281002	0	0
DataKnown_AKnownEnable	2147483647	2147483647	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	331281002
T1	182504	3488
T2	21280	497
T3	4405856	78250
T4	13579776	332114
T16	56000	2156
T17	15678880	449241
T21	136864	4320
T22	0	400
T23	46144	1847
T24	23436784	573875
T25	144984	8980

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	182504	179480
T2	21280	20272
T3	4405856	4404904
T4	13579776	13577424
T16	56000	54768
T17	15678880	15677480
T21	136864	134960
T23	46144	45304
T24	23436784	23434320
T25	144984	142184

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	182504	179480
T2	21280	20272
T3	4405856	4404904
T4	13579776	13577424
T16	56000	54768
T17	15678880	15677480
T21	136864	134960
T23	46144	45304
T24	23436784	23434320
T25	144984	142184

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	182504	179480
T2	21280	20272
T3	4405856	4404904
T4	13579776	13577424
T16	56000	54768
T17	15678880	15677480
T21	136864	134960
T23	46144	45304
T24	23436784	23434320
T25	144984	142184

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	182504	179480
T2	21280	20272
T3	4405856	4404904
T4	13579776	13577424
T16	56000	54768
T17	15678880	15677480
T21	136864	134960
T23	46144	45304
T24	23436784	23434320
T25	144984	142184

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T16	56	56
T17	56	56
T21	56	56
T23	56	56
T24	56	56
T25	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	125991443	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	125991443
T1	3259	1630
T2	380	191
T3	78676	76642
T4	242496	141992
T16	1000	839
T17	279980	274253
T21	2444	1082
T23	824	716
T24	418514	244208
T25	2589	2245

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	82476588	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	82476588
T1	3259	412
T2	380	102
T3	78676	452
T4	242496	62896
T16	1000	439
T17	279980	86681
T21	2444	1082
T23	824	377
T24	418514	108677
T25	2589	2245

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1557347	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1557347
T1	3259	62
T2	380	2
T3	78676	32
T4	242496	2417
T16	1000	10
T17	279980	16
T21	2444	32
T22	0	8
T23	824	15
T24	418514	1674
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3117534	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3117534
T1	3259	21
T2	380	2
T3	78676	6
T4	242496	3910
T16	1000	10
T17	279980	1150
T21	2444	32
T22	0	8
T23	824	15
T24	418514	1438
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1541357	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1541357
T1	3259	46
T2	380	1
T3	78676	9
T4	242496	3607
T16	1000	17
T17	279980	69
T21	2444	45
T22	0	11
T23	824	21
T24	418514	2485
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2887779	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2887779
T1	3259	10
T2	380	1
T3	78676	4
T4	242496	3005
T16	1000	17
T17	279980	2643
T21	2444	45
T22	0	11
T23	824	21
T24	418514	5033
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1567709	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1567709
T1	3259	36
T2	380	4
T3	78676	52
T4	242496	1723
T16	1000	13
T17	279980	47
T21	2444	33
T23	824	12
T24	418514	5569
T25	2589	293

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2806406	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2806406
T1	3259	11
T2	380	4
T3	78676	13
T4	242496	1200
T16	1000	13
T17	279980	1037
T21	2444	33
T23	824	12
T24	418514	6947
T25	2589	293

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1515736	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1515736
T1	3259	62
T2	380	4
T3	78676	22
T4	242496	1977
T16	1000	19
T17	279980	80
T21	2444	52
T22	0	10
T23	824	11
T24	418514	4096
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2669038	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2669038
T1	3259	17
T2	380	4
T3	78676	4
T4	242496	1705
T16	1000	19
T17	279980	3857
T21	2444	52
T22	0	10
T23	824	11
T24	418514	4755
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1564134	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1564134
T1	3259	31
T2	380	4
T3	78676	10
T4	242496	2616
T16	1000	10
T17	279980	55
T21	2444	40
T22	0	6
T23	824	16
T24	418514	2356
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2704738	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2704738
T1	3259	7
T2	380	4
T3	78676	5
T4	242496	1960
T16	1000	10
T17	279980	2684
T21	2444	40
T22	0	6
T23	824	16
T24	418514	3119
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1541871	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1541871
T1	3259	43
T2	380	5
T3	78676	25
T4	242496	1935
T16	1000	19
T17	279980	54
T21	2444	43
T22	0	12
T23	824	16
T24	418514	4932
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2967875	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2967875
T1	3259	21
T2	380	5
T3	78676	6
T4	242496	1903
T16	1000	19
T17	279980	1632
T21	2444	43
T22	0	12
T23	824	16
T24	418514	5621
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1546257	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1546257
T1	3259	16
T2	380	2
T3	78676	36
T4	242496	1734
T16	1000	14
T17	279980	73
T21	2444	38
T22	0	10
T23	824	8
T24	418514	5068
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2587781	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2587781
T1	3259	11
T2	380	2
T3	78676	8
T4	242496	3170
T16	1000	14
T17	279980	5533
T21	2444	38
T22	0	10
T23	824	8
T24	418514	4969
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1556025	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1556025
T1	3259	13
T2	380	4
T3	78676	14
T4	242496	2818
T16	1000	16
T17	279980	53
T21	2444	48
T22	0	12
T23	824	12
T24	418514	4353
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3464803	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3464803
T1	3259	14
T2	380	4
T3	78676	295
T4	242496	4027
T16	1000	16
T17	279980	3669
T21	2444	48
T22	0	12
T23	824	12
T24	418514	4274
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1589943	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1589943
T1	3259	51
T2	380	3
T3	78676	40
T4	242496	4348
T16	1000	12
T17	279980	97
T21	2444	48
T23	824	19
T24	418514	2464
T25	2589	277

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3205379	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3205379
T1	3259	30
T2	380	3
T3	78676	9
T4	242496	3272
T16	1000	12
T17	279980	6255
T21	2444	48
T23	824	19
T24	418514	2048
T25	2589	277

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1541274	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1541274
T1	3259	63
T2	380	2
T3	78676	51
T4	242496	2766
T16	1000	10
T17	279980	45
T21	2444	37
T23	824	9
T24	418514	4773
T25	2589	209

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2717473	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2717473
T1	3259	24
T2	380	2
T3	78676	10
T4	242496	1232
T16	1000	10
T17	279980	3091
T21	2444	37
T23	824	9
T24	418514	3820
T25	2589	209

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1522401	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1522401
T1	3259	37
T2	380	2
T3	78676	43
T4	242496	2255
T16	1000	21
T17	279980	59
T21	2444	40
T22	0	10
T23	824	14
T24	418514	5878
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2935596	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2935596
T1	3259	12
T2	380	2
T3	78676	8
T4	242496	2190
T16	1000	21
T17	279980	4107
T21	2444	40
T22	0	10
T23	824	14
T24	418514	5753
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1492050	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1492050
T1	3259	38
T2	380	7
T3	78676	19
T4	242496	2542
T16	1000	10
T17	279980	70
T21	2444	29
T23	824	24
T24	418514	6668
T25	2589	204

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2706343	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2706343
T1	3259	27
T2	380	7
T3	78676	5
T4	242496	3033
T16	1000	10
T17	279980	4979
T21	2444	29
T23	824	24
T24	418514	6763
T25	2589	204

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1486369	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1486369
T1	3259	31
T2	380	2
T3	78676	47
T4	242496	1901
T16	1000	14
T17	279980	87
T21	2444	44
T23	824	8
T24	418514	3330
T25	2589	214

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2944673	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2944673
T1	3259	20
T2	380	2
T3	78676	8
T4	242496	2045
T16	1000	14
T17	279980	4849
T21	2444	44
T23	824	8
T24	418514	2720
T25	2589	214

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1571192	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1571192
T1	3259	11
T2	380	5
T3	78676	17
T4	242496	3412
T16	1000	31
T17	279980	71
T21	2444	39
T22	0	16
T23	824	9
T24	418514	6280
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3434787	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3434787
T1	3259	16
T2	380	5
T3	78676	3
T4	242496	3082
T16	1000	31
T17	279980	4142
T21	2444	39
T22	0	16
T23	824	9
T24	418514	6040
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1526562	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1526562
T1	3259	30
T2	380	4
T3	78676	10
T4	242496	871
T16	1000	11
T17	279980	42
T21	2444	38
T22	0	5
T23	824	20
T24	418514	5787
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2379459	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2379459
T1	3259	13
T2	380	4
T3	78676	3
T4	242496	1994
T16	1000	11
T17	279980	2236
T21	2444	38
T22	0	5
T23	824	20
T24	418514	3369
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1553714	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1553714
T1	3259	3
T2	380	2
T3	78676	29
T4	242496	3921
T16	1000	13
T17	279980	82
T21	2444	32
T22	0	12
T23	824	15
T24	418514	3515
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3253359	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3253359
T1	3259	1
T2	380	2
T3	78676	6
T4	242496	3904
T16	1000	13
T17	279980	3647
T21	2444	32
T22	0	12
T23	824	15
T24	418514	3137
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1596814	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1596814
T1	3259	16
T2	380	5
T3	78676	7
T4	242496	596
T16	1000	15
T17	279980	50
T21	2444	36
T23	824	12
T24	418514	2277
T25	2589	297

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2826250	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2826250
T1	3259	3
T2	380	5
T3	78676	1
T4	242496	2072
T16	1000	15
T17	279980	1372
T21	2444	36
T23	824	12
T24	418514	2322
T25	2589	297

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1477295	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1477295
T1	3259	59
T2	380	8
T3	78676	16
T4	242496	3384
T16	1000	16
T17	279980	78
T21	2444	22
T23	824	12
T24	418514	6814
T25	2589	255

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3138040	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3138040
T1	3259	30
T2	380	8
T3	78676	4
T4	242496	1293
T16	1000	16
T17	279980	2222
T21	2444	22
T23	824	12
T24	418514	5574
T25	2589	255

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1556535	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1556535
T1	3259	83
T2	380	3
T3	78676	23
T4	242496	2199
T16	1000	28
T17	279980	59
T21	2444	46
T23	824	12
T24	418514	4807
T25	2589	257

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3411299	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3411299
T1	3259	24
T2	380	3
T3	78676	3
T4	242496	1008
T16	1000	28
T17	279980	4504
T21	2444	46
T23	824	12
T24	418514	7439
T25	2589	257

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1527480	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1527480
T1	3259	58
T2	380	4
T3	78676	18
T4	242496	4927
T16	1000	15
T17	279980	49
T21	2444	30
T22	0	12
T23	824	15
T24	418514	2616
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2788189	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2788189
T1	3259	10
T2	380	4
T3	78676	4
T4	242496	3446
T16	1000	15
T17	279980	3301
T21	2444	30
T22	0	12
T23	824	15
T24	418514	1652
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1498020	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1498020
T1	3259	44
T2	380	4
T3	78676	22
T4	242496	742
T16	1000	25
T17	279980	73
T21	2444	39
T22	0	10
T23	824	14
T24	418514	4379
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3612228	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3612228
T1	3259	11
T2	380	4
T3	78676	4
T4	242496	2716
T16	1000	25
T17	279980	2454
T21	2444	39
T22	0	10
T23	824	14
T24	418514	2655
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1496633	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1496633
T1	3259	13
T2	380	6
T3	78676	28
T4	242496	814
T16	1000	15
T17	279980	51
T21	2444	54
T22	0	12
T23	824	9
T24	418514	3880
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3083695	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3083695
T1	3259	7
T2	380	6
T3	78676	8
T4	242496	1857
T16	1000	15
T17	279980	2496
T21	2444	54
T22	0	12
T23	824	9
T24	418514	3646
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1519458	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1519458
T1	3259	2
T2	380	2
T3	78676	21
T4	242496	3698
T16	1000	16
T17	279980	70
T21	2444	41
T22	0	13
T23	824	13
T24	418514	2718
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3461079	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3461079
T1	3259	2
T2	380	2
T3	78676	4
T4	242496	3651
T16	1000	16
T17	279980	2114
T21	2444	41
T22	0	13
T23	824	13
T24	418514	3478
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1507450	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1507450
T1	3259	39
T2	380	2
T3	78676	17
T4	242496	3035
T16	1000	14
T17	279980	48
T21	2444	45
T23	824	13
T24	418514	4309
T25	2589	239

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2397284	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2397284
T1	3259	23
T2	380	2
T3	78676	6
T4	242496	2109
T16	1000	14
T17	279980	1275
T21	2444	45
T23	824	13
T24	418514	4221
T25	2589	239

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1507435	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1507435
T1	3259	51
T2	380	3
T3	78676	45
T4	242496	1955
T16	1000	17
T17	279980	65
T21	2444	39
T22	0	18
T23	824	21
T24	418514	3355
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	2684194	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	2684194
T1	3259	5
T2	380	3
T3	78676	9
T4	242496	1895
T16	1000	17
T17	279980	3147
T21	2444	39
T22	0	18
T23	824	21
T24	418514	1761
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1552802	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1552802
T1	3259	56
T2	380	8
T3	78676	29
T4	242496	605
T16	1000	22
T17	279980	51
T21	2444	48
T22	0	12
T23	824	13
T24	418514	5554
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3981706	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3981706
T1	3259	17
T2	380	8
T3	78676	4
T4	242496	318
T16	1000	22
T17	279980	4776
T21	2444	48
T22	0	12
T23	824	13
T24	418514	4148
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	1508921	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	1508921
T1	3259	40
T2	380	4
T3	78676	22
T4	242496	1532
T16	1000	16
T17	279980	61
T21	2444	40
T22	0	11
T23	824	14
T24	418514	2376
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	294612320	3223200	0	0
DataKnown_AKnownEnable	294612320	294473945	0	0
DepthKnown_A	294612320	294473945	0	0
RvalidKnown_A	294612320	294473945	0	0
WreadyKnown_A	294612320	294473945	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	294612320	3223200
T1	3259	25
T2	380	4
T3	78676	12
T4	242496	899
T16	1000	16
T17	279980	3480
T21	2444	40
T22	0	11
T23	824	14
T24	418514	1975
T25	2589	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

DepthKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

RvalidKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

WreadyKnown_A

Name	Attempts	Real Successes
Total	294612320	294473945
T1	3259	3205
T2	380	362
T3	78676	78659
T4	242496	242454
T16	1000	978
T17	279980	279955
T21	2444	2410
T23	824	809
T24	418514	418470
T25	2589	2539

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T16	1	1
T17	1	1
T21	1	1
T23	1	1
T24	1	1
T25	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children