Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1727329	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

272088

1

T1

18

T2

27

T3

275

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	675133	1			T1	50		T2	50		T3	730
values[0x0]	647203	1			T1	53		T2	57		T3	690
values[0x1]	677081	1			T1	57		T2	51		T3	755

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1339692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

659725

1

T1

60

T2

52

T3

717

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7224	1			T3	4		T22	1		T23	26
valid_sources[0x01]	8594	1			T1	1		T3	12		T5	1
valid_sources[0x02]	8450	1			T3	5		T4	1		T15	3
valid_sources[0x03]	6898	1			T2	1		T3	10		T22	1
valid_sources[0x04]	7187	1			T3	9		T21	1		T23	9
valid_sources[0x05]	7682	1			T1	2		T2	2		T3	13
valid_sources[0x06]	8227	1			T3	9		T4	5		T23	8
valid_sources[0x07]	7214	1			T3	8		T4	1		T18	1
valid_sources[0x08]	7501	1			T1	1		T3	9		T15	1
valid_sources[0x09]	6835	1			T2	1		T3	4		T5	1
valid_sources[0x0a]	7535	1			T1	2		T2	5		T3	3
valid_sources[0x0b]	7362	1			T1	3		T3	4		T15	2
valid_sources[0x0c]	6883	1			T1	1		T2	2		T3	16
valid_sources[0x0d]	7735	1			T1	1		T2	1		T3	4
valid_sources[0x0e]	7945	1			T3	8		T5	1		T21	1
valid_sources[0x0f]	7851	1			T1	1		T3	5		T5	1
valid_sources[0x10]	8695	1			T2	2		T3	12		T22	1
valid_sources[0x11]	6669	1			T1	1		T2	3		T3	10
valid_sources[0x12]	7340	1			T2	2		T3	3		T23	8
valid_sources[0x13]	7473	1			T3	5		T5	2		T21	2
valid_sources[0x14]	8363	1			T3	7		T5	1		T23	8
valid_sources[0x15]	9154	1			T1	1		T2	2		T3	7
valid_sources[0x16]	7297	1			T1	1		T3	12		T4	1
valid_sources[0x17]	7667	1			T2	2		T3	13		T19	19
valid_sources[0x18]	9127	1			T3	9		T4	1		T23	6
valid_sources[0x19]	7953	1			T3	7		T5	1		T21	1
valid_sources[0x1a]	9552	1			T3	10		T4	1		T5	1
valid_sources[0x1b]	8118	1			T3	8		T5	2		T21	1
valid_sources[0x1c]	7922	1			T2	2		T3	5		T23	5
valid_sources[0x1d]	7079	1			T3	11		T15	1		T23	17
valid_sources[0x1e]	8257	1			T1	2		T3	8		T4	1
valid_sources[0x1f]	8117	1			T1	1		T2	2		T3	12
valid_sources[0x20]	8535	1			T2	1		T3	6		T5	1
valid_sources[0x21]	7439	1			T2	1		T3	11		T22	1
valid_sources[0x22]	8513	1			T2	1		T3	10		T5	1
valid_sources[0x23]	7278	1			T3	6		T4	2		T16	12
valid_sources[0x24]	7516	1			T1	1		T2	1		T3	10
valid_sources[0x25]	7230	1			T3	5		T23	37		T16	21
valid_sources[0x26]	7504	1			T2	2		T3	8		T4	2
valid_sources[0x27]	8707	1			T1	1		T3	9		T22	1
valid_sources[0x28]	9019	1			T1	1		T2	1		T3	8
valid_sources[0x29]	7674	1			T2	1		T3	12		T21	1
valid_sources[0x2a]	6915	1			T2	1		T3	11		T22	1
valid_sources[0x2b]	7618	1			T1	1		T2	1		T3	4
valid_sources[0x2c]	7358	1			T1	1		T2	1		T3	7
valid_sources[0x2d]	7373	1			T2	1		T3	8		T4	1
valid_sources[0x2e]	8524	1			T3	2		T21	1		T22	1
valid_sources[0x2f]	8582	1			T3	5		T4	2		T5	1
valid_sources[0x30]	7749	1			T1	1		T3	4		T4	3
valid_sources[0x31]	8521	1			T3	11		T4	1		T21	2
valid_sources[0x32]	7544	1			T1	1		T2	1		T3	10
valid_sources[0x33]	6854	1			T2	2		T3	6		T4	1
valid_sources[0x34]	8820	1			T2	1		T3	7		T19	6
valid_sources[0x35]	7887	1			T1	1		T3	7		T4	1
valid_sources[0x36]	7753	1			T1	1		T2	1		T3	12
valid_sources[0x37]	6923	1			T1	1		T2	1		T3	9
valid_sources[0x38]	7849	1			T3	5		T5	1		T22	1
valid_sources[0x39]	8378	1			T1	2		T2	1		T3	11
valid_sources[0x3a]	8758	1			T1	1		T2	1		T3	5
valid_sources[0x3b]	7197	1			T2	1		T3	10		T5	2
valid_sources[0x3c]	7371	1			T3	14		T23	5		T18	3
valid_sources[0x3d]	7642	1			T3	12		T4	1		T5	2
valid_sources[0x3e]	7160	1			T1	1		T3	6		T4	1
valid_sources[0x3f]	6874	1			T3	6		T5	1		T15	1
valid_sources[0x40]	8589	1			T3	11		T15	1		T16	10
valid_sources[0x41]	6709	1			T2	2		T3	10		T5	2
valid_sources[0x42]	6975	1			T1	1		T3	5		T4	2
valid_sources[0x43]	7122	1			T2	1		T3	7		T5	1
valid_sources[0x44]	7626	1			T1	1		T2	1		T3	13
valid_sources[0x45]	7857	1			T2	1		T3	16		T4	1
valid_sources[0x46]	7011	1			T3	14		T4	2		T5	2
valid_sources[0x47]	7615	1			T1	1		T2	1		T3	12
valid_sources[0x48]	7031	1			T3	9		T5	2		T21	1
valid_sources[0x49]	8259	1			T2	3		T3	10		T4	1
valid_sources[0x4a]	6674	1			T1	2		T2	1		T3	9
valid_sources[0x4b]	9226	1			T3	5		T4	1		T21	1
valid_sources[0x4c]	7840	1			T3	4		T4	1		T5	2
valid_sources[0x4d]	7687	1			T2	1		T3	8		T5	1
valid_sources[0x4e]	7430	1			T2	2		T3	9		T4	1
valid_sources[0x4f]	8060	1			T2	1		T3	9		T19	14
valid_sources[0x50]	6924	1			T3	3		T5	1		T15	1
valid_sources[0x51]	8061	1			T2	1		T3	12		T4	1
valid_sources[0x52]	7478	1			T3	8		T4	1		T5	1
valid_sources[0x53]	8076	1			T3	8		T4	2		T5	1
valid_sources[0x54]	7863	1			T1	3		T2	1		T3	8
valid_sources[0x55]	8687	1			T3	7		T4	2		T5	2
valid_sources[0x56]	7752	1			T3	3		T5	1		T22	2
valid_sources[0x57]	7267	1			T1	1		T2	3		T3	10
valid_sources[0x58]	10912	1			T3	6		T5	1		T23	45
valid_sources[0x59]	7978	1			T2	2		T3	10		T4	1
valid_sources[0x5a]	7268	1			T1	1		T3	10		T4	2
valid_sources[0x5b]	7079	1			T1	2		T2	1		T3	12
valid_sources[0x5c]	8434	1			T1	2		T2	1		T3	5
valid_sources[0x5d]	7316	1			T1	2		T2	1		T3	6
valid_sources[0x5e]	7285	1			T3	8		T5	1		T21	1
valid_sources[0x5f]	8800	1			T3	5		T16	14		T26	2
valid_sources[0x60]	6884	1			T1	2		T2	1		T3	7
valid_sources[0x61]	6650	1			T3	9		T21	4		T22	2
valid_sources[0x62]	7263	1			T2	1		T3	3		T5	1
valid_sources[0x63]	8590	1			T3	12		T4	2		T5	3
valid_sources[0x64]	8230	1			T3	11		T5	2		T23	2
valid_sources[0x65]	6815	1			T2	1		T3	13		T4	2
valid_sources[0x66]	7383	1			T1	1		T3	5		T5	2
valid_sources[0x67]	7602	1			T3	9		T4	1		T5	1
valid_sources[0x68]	7256	1			T3	7		T5	1		T21	2
valid_sources[0x69]	7079	1			T1	1		T3	9		T5	1
valid_sources[0x6a]	7832	1			T3	9		T19	9		T5	1
valid_sources[0x6b]	7862	1			T2	1		T3	10		T4	2
valid_sources[0x6c]	7037	1			T1	5		T3	5		T23	6
valid_sources[0x6d]	7872	1			T3	12		T23	4		T16	6
valid_sources[0x6e]	7441	1			T1	1		T2	1		T3	16
valid_sources[0x6f]	7248	1			T2	1		T3	14		T5	1
valid_sources[0x70]	7540	1			T3	14		T4	2		T5	1
valid_sources[0x71]	10094	1			T1	1		T3	9		T4	1
valid_sources[0x72]	7752	1			T1	1		T3	9		T4	1
valid_sources[0x73]	7408	1			T3	8		T21	2		T15	1
valid_sources[0x74]	7681	1			T3	12		T4	1		T17	1
valid_sources[0x75]	7541	1			T1	2		T3	10		T5	2
valid_sources[0x76]	7635	1			T1	1		T2	2		T3	8
valid_sources[0x77]	7277	1			T2	2		T3	11		T5	1
valid_sources[0x78]	9710	1			T2	2		T3	12		T5	2
valid_sources[0x79]	7284	1			T1	1		T2	1		T3	3
valid_sources[0x7a]	7840	1			T1	2		T2	1		T3	5
valid_sources[0x7b]	8257	1			T1	1		T2	1		T3	6
valid_sources[0x7c]	7523	1			T1	3		T2	1		T3	7
valid_sources[0x7d]	7725	1			T1	2		T3	14		T4	2
valid_sources[0x7e]	8858	1			T3	5		T19	5		T5	2
valid_sources[0x7f]	8946	1			T3	3		T19	10		T17	1
valid_sources[0x80]	7597	1			T1	1		T2	3		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28361

1

T1

2

T3

34

T19

1

values[0x0]

all_enables

biggest_size

215032

1

T1

15

T2

25

T3

211

values[0x1]

all_enables

biggest_size

28695

1

T1

1

T2

2

T3

30