Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	355054576	0	0
DataKnown_AKnownEnable	2147483647	2147483647	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	355054576
T1	260008	4294
T2	33432	775
T3	258384	10653
T4	11241888	274761
T5	243656	3155
T15	0	4436
T17	193480	5994
T19	25256	788
T20	385784	7361
T21	188888	3600
T22	40152	524

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	260008	255136
T2	33432	31472
T3	258384	254184
T4	11241888	11239928
T5	243656	240632
T17	193480	189616
T19	25256	24864
T20	385784	385112
T21	188888	187152
T22	40152	37352

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	260008	255136
T2	33432	31472
T3	258384	254184
T4	11241888	11239928
T5	243656	240632
T17	193480	189616
T19	25256	24864
T20	385784	385112
T21	188888	187152
T22	40152	37352

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	260008	255136
T2	33432	31472
T3	258384	254184
T4	11241888	11239928
T5	243656	240632
T17	193480	189616
T19	25256	24864
T20	385784	385112
T21	188888	187152
T22	40152	37352

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	260008	255136
T2	33432	31472
T3	258384	254184
T4	11241888	11239928
T5	243656	240632
T17	193480	189616
T19	25256	24864
T20	385784	385112
T21	188888	187152
T22	40152	37352

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T17	56	56
T19	56	56
T20	56	56
T21	56	56
T22	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	129232887	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	129232887
T1	4643	1870
T2	597	301
T3	4614	4128
T4	200748	110548
T5	4351	1452
T17	3455	2951
T19	451	197
T20	6889	3164
T21	3373	1611
T22	717	206

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	94473153	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	94473153
T1	4643	573
T2	597	158
T3	4614	2175
T4	200748	54807
T5	4351	412
T17	3455	1509
T19	451	197
T20	6889	995
T21	3373	474
T22	717	106

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1419204	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1419204
T1	4643	3
T2	597	2
T3	4614	76
T4	200748	2773
T5	4351	52
T17	3455	30
T19	451	6
T20	6889	80
T21	3373	28
T22	717	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3458354	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3458354
T1	4643	9
T2	597	2
T3	4614	76
T4	200748	1812
T5	4351	14
T17	3455	30
T19	451	6
T20	6889	22
T21	3373	12
T22	717	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1423356	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1423356
T1	4643	34
T2	597	9
T3	4614	86
T4	200748	2296
T5	4351	79
T17	3455	28
T19	451	9
T20	6889	68
T21	3373	58
T22	717	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	2509880	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	2509880
T1	4643	41
T2	597	9
T3	4614	86
T4	200748	1840
T5	4351	15
T17	3455	28
T19	451	9
T20	6889	30
T21	3373	15
T22	717	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1376305	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1376305
T1	4643	59
T2	597	11
T3	4614	90
T4	200748	3694
T5	4351	15
T17	3455	38
T19	451	7
T20	6889	161
T21	3373	26
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3522888	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3522888
T1	4643	21
T2	597	11
T3	4614	90
T4	200748	3206
T5	4351	3
T17	3455	38
T19	451	7
T20	6889	87
T21	3373	3
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1461429	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1461429
T1	4643	35
T2	597	2
T3	4614	79
T4	200748	1828
T5	4351	43
T17	3455	41
T19	451	8
T20	6889	101
T21	3373	27
T22	717	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3902503	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3902503
T1	4643	8
T2	597	2
T3	4614	79
T4	200748	3297
T5	4351	8
T17	3455	41
T19	451	8
T20	6889	35
T21	3373	22
T22	717	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1411989	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1411989
T1	4643	26
T2	597	4
T3	4614	78
T4	200748	1914
T5	4351	19
T17	3455	38
T19	451	5
T20	6889	33
T21	3373	30
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3653554	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3653554
T1	4643	9
T2	597	4
T3	4614	78
T4	200748	2295
T5	4351	2
T17	3455	38
T19	451	5
T20	6889	14
T21	3373	4
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1360032	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1360032
T1	4643	29
T2	597	7
T3	4614	87
T4	200748	1139
T5	4351	17
T17	3455	23
T19	451	10
T20	6889	42
T21	3373	22
T22	717	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3636598	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3636598
T1	4643	11
T2	597	7
T3	4614	87
T4	200748	713
T5	4351	1
T17	3455	23
T19	451	10
T20	6889	11
T21	3373	16
T22	717	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1394882	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1394882
T1	4643	55
T2	597	8
T3	4614	95
T4	200748	755
T5	4351	111
T17	3455	41
T19	451	8
T20	6889	92
T21	3373	52
T22	717	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	4170340	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	4170340
T1	4643	32
T2	597	8
T3	4614	95
T4	200748	1509
T5	4351	8
T17	3455	41
T19	451	8
T20	6889	35
T21	3373	13
T22	717	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1391135	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1391135
T1	4643	32
T2	597	4
T3	4614	63
T4	200748	1714
T5	4351	28
T17	3455	21
T19	451	7
T20	6889	70
T21	3373	44
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	4004767	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	4004767
T1	4643	15
T2	597	4
T3	4614	63
T4	200748	1921
T5	4351	14
T17	3455	21
T19	451	7
T20	6889	28
T21	3373	39
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1409589	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1409589
T1	4643	23
T2	597	3
T3	4614	85
T4	200748	1335
T5	4351	35
T15	0	12
T17	3455	42
T19	451	2
T20	6889	75
T21	3373	31
T22	717	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3212566	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3212566
T1	4643	19
T2	597	3
T3	4614	85
T4	200748	2629
T5	4351	9
T15	0	1093
T17	3455	42
T19	451	2
T20	6889	27
T21	3373	8
T22	717	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1341409	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1341409
T1	4643	104
T2	597	7
T3	4614	72
T4	200748	403
T5	4351	57
T17	3455	34
T19	451	7
T20	6889	53
T21	3373	17
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3054523	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3054523
T1	4643	40
T2	597	7
T3	4614	72
T4	200748	51
T5	4351	27
T17	3455	34
T19	451	7
T20	6889	21
T21	3373	20
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1400409	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1400409
T1	4643	43
T2	597	9
T3	4614	85
T4	200748	1296
T5	4351	14
T17	3455	26
T19	451	9
T20	6889	73
T21	3373	34
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3495097	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3495097
T1	4643	21
T2	597	9
T3	4614	85
T4	200748	1763
T5	4351	20
T17	3455	26
T19	451	9
T20	6889	34
T21	3373	20
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1354690	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1354690
T1	4643	29
T2	597	14
T3	4614	77
T4	200748	1901
T5	4351	36
T17	3455	27
T19	451	10
T20	6889	106
T21	3373	27
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3377032	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3377032
T1	4643	9
T2	597	14
T3	4614	77
T4	200748	1144
T5	4351	3
T17	3455	27
T19	451	10
T20	6889	22
T21	3373	14
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1414734	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1414734
T1	4643	19
T2	597	5
T3	4614	82
T4	200748	2309
T5	4351	69
T17	3455	30
T19	451	8
T20	6889	58
T21	3373	49
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3152134	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3152134
T1	4643	11
T2	597	5
T3	4614	82
T4	200748	1451
T5	4351	22
T17	3455	30
T19	451	8
T20	6889	66
T21	3373	47
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1447459	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1447459
T1	4643	36
T2	597	6
T3	4614	84
T4	200748	233
T5	4351	29
T17	3455	21
T19	451	5
T20	6889	64
T21	3373	55
T22	717	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3352472	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3352472
T1	4643	14
T2	597	6
T3	4614	84
T4	200748	527
T5	4351	4
T17	3455	21
T19	451	5
T20	6889	33
T21	3373	22
T22	717	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1388732	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1388732
T1	4643	72
T2	597	6
T3	4614	100
T4	200748	1143
T5	4351	39
T17	3455	25
T19	451	9
T20	6889	79
T21	3373	36
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3156963	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3156963
T1	4643	22
T2	597	6
T3	4614	100
T4	200748	2828
T5	4351	11
T17	3455	25
T19	451	9
T20	6889	40
T21	3373	23
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1406123	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1406123
T1	4643	72
T2	597	6
T3	4614	61
T4	200748	2163
T5	4351	36
T17	3455	30
T19	451	5
T20	6889	84
T21	3373	24
T22	717	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3743937	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3743937
T1	4643	35
T2	597	6
T3	4614	61
T4	200748	3009
T5	4351	20
T17	3455	30
T19	451	5
T20	6889	20
T21	3373	8
T22	717	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1373791	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1373791
T1	4643	11
T2	597	3
T3	4614	76
T4	200748	1137
T5	4351	30
T17	3455	29
T19	451	11
T20	6889	79
T21	3373	91
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3498062	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3498062
T1	4643	15
T2	597	3
T3	4614	76
T4	200748	1277
T5	4351	7
T17	3455	29
T19	451	11
T20	6889	45
T21	3373	34
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1377562	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1377562
T1	4643	16
T2	597	6
T3	4614	67
T4	200748	1200
T5	4351	34
T17	3455	21
T19	451	9
T20	6889	47
T21	3373	23
T22	717	1

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3050102	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3050102
T1	4643	2
T2	597	6
T3	4614	67
T4	200748	222
T5	4351	16
T17	3455	21
T19	451	9
T20	6889	17
T21	3373	6
T22	717	1

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1408158	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1408158
T1	4643	25
T2	597	7
T3	4614	80
T4	200748	2370
T5	4351	31
T17	3455	38
T19	451	7
T20	6889	99
T21	3373	21
T22	717	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3199951	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3199951
T1	4643	17
T2	597	7
T3	4614	80
T4	200748	1967
T5	4351	13
T17	3455	38
T19	451	7
T20	6889	51
T21	3373	17
T22	717	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1433890	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1433890
T1	4643	26
T2	597	2
T3	4614	82
T4	200748	2635
T5	4351	12
T17	3455	26
T19	451	3
T20	6889	106
T21	3373	45
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	4146204	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	4146204
T1	4643	8
T2	597	2
T3	4614	82
T4	200748	3131
T5	4351	4
T17	3455	26
T19	451	3
T20	6889	38
T21	3373	13
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1375050	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1375050
T1	4643	53
T2	597	2
T3	4614	85
T4	200748	2748
T5	4351	40
T17	3455	18
T19	451	7
T20	6889	121
T21	3373	34
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3084186	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3084186
T1	4643	15
T2	597	2
T3	4614	85
T4	200748	2610
T5	4351	22
T17	3455	18
T19	451	7
T20	6889	66
T21	3373	15
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1360032	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1360032
T1	4643	33
T2	597	5
T3	4614	79
T4	200748	2419
T5	4351	39
T15	0	28
T17	3455	23
T19	451	7
T20	6889	47
T21	3373	52
T22	717	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3384142	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3384142
T1	4643	29
T2	597	5
T3	4614	79
T4	200748	1388
T5	4351	7
T15	0	1715
T17	3455	23
T19	451	7
T20	6889	28
T21	3373	10
T22	717	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1372118	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1372118
T1	4643	91
T2	597	9
T3	4614	79
T4	200748	2403
T5	4351	0
T15	0	27
T17	3455	20
T19	451	11
T20	6889	59
T21	3373	19
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3282283	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3282283
T1	4643	17
T2	597	9
T3	4614	79
T4	200748	2415
T5	4351	0
T15	0	1561
T17	3455	20
T19	451	11
T20	6889	44
T21	3373	11
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1420045	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1420045
T1	4643	82
T2	597	2
T3	4614	67
T4	200748	4092
T5	4351	29
T17	3455	18
T19	451	6
T20	6889	92
T21	3373	51
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3876342	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3876342
T1	4643	37
T2	597	2
T3	4614	67
T4	200748	3113
T5	4351	6
T17	3455	18
T19	451	6
T20	6889	45
T21	3373	26
T22	717	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1465852	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1465852
T1	4643	27
T2	597	9
T3	4614	75
T4	200748	3967
T5	4351	6
T17	3455	34
T19	451	5
T20	6889	67
T21	3373	46
T22	717	1

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3544535	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3544535
T1	4643	17
T2	597	9
T3	4614	75
T4	200748	2452
T5	4351	14
T17	3455	34
T19	451	5
T20	6889	46
T21	3373	28
T22	717	1

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1390778	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1390778
T1	4643	132
T2	597	5
T3	4614	97
T4	200748	3278
T5	4351	27
T17	3455	26
T19	451	8
T20	6889	88
T21	3373	30
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3518977	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3518977
T1	4643	65
T2	597	5
T3	4614	97
T4	200748	4030
T5	4351	26
T17	3455	26
T19	451	8
T20	6889	34
T21	3373	5
T22	717	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	1397356	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	1397356
T1	4643	111
T2	597	5
T3	4614	88
T4	200748	1454
T5	4351	44
T17	3455	19
T19	451	8
T20	6889	163
T21	3373	69
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	314590747	3584035	0	0
DataKnown_AKnownEnable	314590747	314469941	0	0
DepthKnown_A	314590747	314469941	0	0
RvalidKnown_A	314590747	314469941	0	0
WreadyKnown_A	314590747	314469941	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	314590747	3584035
T1	4643	34
T2	597	5
T3	4614	88
T4	200748	2207
T5	4351	24
T17	3455	19
T19	451	8
T20	6889	56
T21	3373	23
T22	717	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

DepthKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

RvalidKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

WreadyKnown_A

Name	Attempts	Real Successes
Total	314590747	314469941
T1	4643	4556
T2	597	562
T3	4614	4539
T4	200748	200713
T5	4351	4297
T17	3455	3386
T19	451	444
T20	6889	6877
T21	3373	3342
T22	717	667

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T17	1	1
T19	1	1
T20	1	1
T21	1	1
T22	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children