Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1681011	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

264088

1

T1

29

T2

14

T3

93

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	657449	1			T1	63		T2	40		T3	292
values[0x0]	630810	1			T1	76		T2	43		T3	239
values[0x1]	656840	1			T1	50		T2	35		T3	255

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1304455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

640644

1

T1

67

T2

37

T3

262

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6702	1			T4	1		T16	7		T15	1
valid_sources[0x01]	8374	1			T3	18		T19	55		T16	10
valid_sources[0x02]	7596	1			T4	6		T16	9		T21	11
valid_sources[0x03]	7328	1			T3	38		T4	1		T16	1
valid_sources[0x04]	6956	1			T3	10		T4	2		T16	11
valid_sources[0x05]	7574	1			T20	1		T21	6		T17	14
valid_sources[0x06]	6962	1			T16	3		T21	5		T22	5
valid_sources[0x07]	7601	1			T2	1		T18	226		T19	91
valid_sources[0x08]	7312	1			T4	1		T19	3		T16	10
valid_sources[0x09]	7661	1			T2	1		T4	2		T16	5
valid_sources[0x0a]	6986	1			T2	2		T16	5		T15	1
valid_sources[0x0b]	9028	1			T21	8		T17	36		T24	2
valid_sources[0x0c]	7434	1			T2	2		T3	6		T19	7
valid_sources[0x0d]	8748	1			T18	20		T19	67		T16	2
valid_sources[0x0e]	8123	1			T3	10		T19	8		T16	8
valid_sources[0x0f]	7249	1			T3	17		T18	77		T21	6
valid_sources[0x10]	8208	1			T19	6		T15	1		T21	5
valid_sources[0x11]	7722	1			T19	7		T16	5		T20	1
valid_sources[0x12]	7602	1			T2	3		T3	19		T21	7
valid_sources[0x13]	7656	1			T16	5		T15	1		T21	13
valid_sources[0x14]	7637	1			T16	1		T15	1		T21	12
valid_sources[0x15]	7248	1			T3	6		T18	388		T16	8
valid_sources[0x16]	7719	1			T16	2		T20	6		T23	1
valid_sources[0x17]	8666	1			T4	1		T21	4		T17	33
valid_sources[0x18]	7848	1			T2	1		T16	10		T15	2
valid_sources[0x19]	6816	1			T4	4		T16	7		T21	19
valid_sources[0x1a]	6784	1			T15	1		T21	7		T23	1
valid_sources[0x1b]	7370	1			T4	2		T16	8		T21	9
valid_sources[0x1c]	8339	1			T19	16		T16	3		T15	1
valid_sources[0x1d]	7874	1			T21	3		T23	1		T8	6
valid_sources[0x1e]	7568	1			T2	2		T3	18		T19	12
valid_sources[0x1f]	7555	1			T19	32		T21	2		T22	3
valid_sources[0x20]	7324	1			T2	1		T3	15		T15	2
valid_sources[0x21]	7108	1			T2	1		T4	2		T15	1
valid_sources[0x22]	8814	1			T3	7		T16	1		T21	17
valid_sources[0x23]	7970	1			T16	2		T21	8		T23	1
valid_sources[0x24]	7754	1			T20	8		T21	5		T22	2
valid_sources[0x25]	7850	1			T3	6		T19	52		T16	4
valid_sources[0x26]	7788	1			T2	4		T16	11		T21	7
valid_sources[0x27]	7439	1			T4	1		T16	12		T21	9
valid_sources[0x28]	7900	1			T19	5		T16	2		T21	5
valid_sources[0x29]	8709	1			T2	1		T19	28		T16	2
valid_sources[0x2a]	9300	1			T16	3		T21	5		T17	10
valid_sources[0x2b]	8194	1			T2	4		T4	4		T16	2
valid_sources[0x2c]	8275	1			T4	4		T21	23		T24	3
valid_sources[0x2d]	8066	1			T3	15		T21	19		T23	1
valid_sources[0x2e]	6719	1			T2	2		T4	1		T19	16
valid_sources[0x2f]	7793	1			T4	4		T16	1		T20	2
valid_sources[0x30]	6891	1			T2	1		T16	15		T20	1
valid_sources[0x31]	7089	1			T4	1		T20	5		T21	14
valid_sources[0x32]	7388	1			T2	2		T4	3		T16	2
valid_sources[0x33]	8336	1			T16	1		T21	7		T23	3
valid_sources[0x34]	8177	1			T19	4		T16	3		T20	1
valid_sources[0x35]	7621	1			T2	1		T4	2		T16	1
valid_sources[0x36]	7058	1			T2	1		T19	4		T15	1
valid_sources[0x37]	7054	1			T3	11		T4	1		T19	34
valid_sources[0x38]	8285	1			T2	1		T4	1		T19	1
valid_sources[0x39]	8357	1			T18	142		T19	21		T15	1
valid_sources[0x3a]	7005	1			T2	1		T4	2		T21	4
valid_sources[0x3b]	7608	1			T16	4		T21	17		T23	1
valid_sources[0x3c]	7305	1			T3	11		T16	3		T21	13
valid_sources[0x3d]	7219	1			T19	39		T16	1		T15	2
valid_sources[0x3e]	8196	1			T19	47		T16	1		T21	18
valid_sources[0x3f]	7360	1			T3	17		T21	16		T22	1
valid_sources[0x40]	7329	1			T19	7		T20	1		T21	7
valid_sources[0x41]	7414	1			T4	2		T20	6		T21	17
valid_sources[0x42]	8073	1			T2	2		T16	10		T21	3
valid_sources[0x43]	7426	1			T16	3		T21	4		T17	13
valid_sources[0x44]	7849	1			T2	1		T19	5		T20	2
valid_sources[0x45]	6942	1			T2	1		T19	4		T16	4
valid_sources[0x46]	7858	1			T2	1		T19	2		T15	1
valid_sources[0x47]	7617	1			T3	7		T15	1		T20	8
valid_sources[0x48]	7502	1			T2	2		T3	15		T21	1
valid_sources[0x49]	7120	1			T2	1		T19	50		T16	9
valid_sources[0x4a]	7352	1			T19	30		T21	12		T23	1
valid_sources[0x4b]	7535	1			T15	1		T23	1		T25	1
valid_sources[0x4c]	8015	1			T3	13		T4	1		T16	9
valid_sources[0x4d]	7840	1			T15	2		T21	18		T24	3
valid_sources[0x4e]	7001	1			T4	1		T16	1		T21	18
valid_sources[0x4f]	7951	1			T3	15		T18	51		T16	1
valid_sources[0x50]	7933	1			T2	1		T16	5		T21	6
valid_sources[0x51]	7441	1			T2	1		T4	1		T16	4
valid_sources[0x52]	7562	1			T19	4		T16	7		T21	6
valid_sources[0x53]	7015	1			T3	5		T19	13		T21	3
valid_sources[0x54]	7133	1			T3	7		T16	2		T21	4
valid_sources[0x55]	7650	1			T21	2		T23	4		T17	17
valid_sources[0x56]	8475	1			T2	1		T4	1		T20	3
valid_sources[0x57]	7431	1			T2	1		T21	6		T23	2
valid_sources[0x58]	7265	1			T2	1		T16	2		T21	12
valid_sources[0x59]	6875	1			T19	3		T21	23		T17	5
valid_sources[0x5a]	7436	1			T21	18		T23	1		T17	14
valid_sources[0x5b]	7133	1			T19	22		T16	2		T21	20
valid_sources[0x5c]	7357	1			T3	10		T16	1		T21	7
valid_sources[0x5d]	7620	1			T2	1		T19	24		T21	6
valid_sources[0x5e]	7425	1			T19	4		T16	14		T15	1
valid_sources[0x5f]	8055	1			T2	1		T3	14		T20	1
valid_sources[0x60]	7939	1			T19	11		T15	1		T20	4
valid_sources[0x61]	6841	1			T21	13		T17	23		T8	13
valid_sources[0x62]	7674	1			T2	1		T3	9		T16	4
valid_sources[0x63]	8043	1			T2	1		T4	1		T16	2
valid_sources[0x64]	7271	1			T4	1		T19	15		T16	4
valid_sources[0x65]	7768	1			T3	14		T19	18		T16	1
valid_sources[0x66]	7773	1			T4	2		T21	3		T17	7
valid_sources[0x67]	7769	1			T2	1		T19	29		T16	1
valid_sources[0x68]	7499	1			T4	1		T16	4		T21	16
valid_sources[0x69]	7950	1			T3	11		T21	4		T17	13
valid_sources[0x6a]	8303	1			T2	1		T3	7		T16	14
valid_sources[0x6b]	7099	1			T3	15		T21	8		T23	1
valid_sources[0x6c]	7183	1			T21	3		T23	2		T17	32
valid_sources[0x6d]	7524	1			T2	1		T4	6		T21	3
valid_sources[0x6e]	7282	1			T19	29		T16	7		T21	11
valid_sources[0x6f]	7236	1			T2	5		T3	13		T19	2
valid_sources[0x70]	7050	1			T16	9		T21	7		T22	1
valid_sources[0x71]	6997	1			T2	1		T15	1		T21	8
valid_sources[0x72]	7762	1			T18	54		T15	1		T21	6
valid_sources[0x73]	7225	1			T2	1		T4	4		T16	10
valid_sources[0x74]	7475	1			T2	2		T4	1		T16	5
valid_sources[0x75]	6663	1			T4	1		T19	6		T16	3
valid_sources[0x76]	7518	1			T18	74		T16	6		T21	9
valid_sources[0x77]	8301	1			T2	1		T4	8		T19	8
valid_sources[0x78]	7556	1			T4	1		T20	1		T21	12
valid_sources[0x79]	7235	1			T19	6		T16	11		T21	8
valid_sources[0x7a]	7342	1			T2	1		T16	5		T15	2
valid_sources[0x7b]	6932	1			T21	5		T17	6		T24	1
valid_sources[0x7c]	7796	1			T19	14		T16	7		T21	7
valid_sources[0x7d]	7588	1			T19	7		T21	1		T17	17
valid_sources[0x7e]	6861	1			T15	1		T21	6		T17	1
valid_sources[0x7f]	7850	1			T2	2		T19	40		T16	3
valid_sources[0x80]	7454	1			T4	3		T21	10		T23	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27398

1

T1

5

T3

11

T4

4

values[0x0]

all_enables

biggest_size

209149

1

T1

20

T2

14

T3

68

values[0x1]

all_enables

biggest_size

27541

1

T1

4

T3

14

T4

3