Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	320500356	0	0
DataKnown_AKnownEnable	2147483647	2147483647	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	320500356
T1	27664	929
T2	41384	575
T3	1744344	23936
T4	3800720	67008
T15	1543920	23456
T16	756056	10911
T18	196056	7772
T19	183512	7847
T20	10845576	217164
T21	2749880	78626
T22	0	268

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27664	26880
T2	41384	37688
T3	1744344	1742720
T4	3800720	3799488
T15	1543920	1542576
T16	756056	751912
T18	196056	193480
T19	183512	182336
T20	10845576	10841432
T21	2749880	2746968

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27664	26880
T2	41384	37688
T3	1744344	1742720
T4	3800720	3799488
T15	1543920	1542576
T16	756056	751912
T18	196056	193480
T19	183512	182336
T20	10845576	10841432
T21	2749880	2746968

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27664	26880
T2	41384	37688
T3	1744344	1742720
T4	3800720	3799488
T15	1543920	1542576
T16	756056	751912
T18	196056	193480
T19	183512	182336
T20	10845576	10841432
T21	2749880	2746968

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	27664	26880
T2	41384	37688
T3	1744344	1742720
T4	3800720	3799488
T15	1543920	1542576
T16	756056	751912
T18	196056	193480
T19	183512	182336
T20	10845576	10841432
T21	2749880	2746968

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T15	56	56
T16	56	56
T18	56	56
T19	56	56
T20	56	56
T21	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	111884005	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	111884005
T1	494	362
T2	739	221
T3	31149	6226
T4	67870	66015
T15	27570	10651
T16	13501	4929
T18	3501	3007
T19	3277	3047
T20	193671	90263
T21	49105	19238

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	87279723	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	87279723
T1	494	189
T2	739	118
T3	31149	5742
T4	67870	205
T15	27570	3690
T16	13501	1746
T18	3501	1589
T19	3277	1600
T20	193671	39801
T21	49105	20075

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1357530	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1357530
T1	494	8
T2	739	3
T3	31149	178
T4	67870	24
T15	27570	222
T16	13501	108
T18	3501	66
T19	3277	53
T20	193671	1939
T21	49105	4227

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3578013	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3578013
T1	494	8
T2	739	3
T3	31149	145
T4	67870	5
T15	27570	76
T16	13501	39
T18	3501	66
T19	3277	53
T20	193671	2734
T21	49105	4520

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1283178	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1283178
T1	494	4
T2	739	3
T3	31149	254
T4	67870	6
T15	27570	231
T16	13501	61
T18	3501	66
T19	3277	69
T20	193671	1042
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3166621	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3166621
T1	494	4
T2	739	3
T3	31149	207
T4	67870	2
T15	27570	90
T16	13501	62
T18	3501	66
T19	3277	69
T20	193671	458
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1321776	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1321776
T1	494	1
T2	739	7
T3	31149	238
T4	67870	40
T15	27570	226
T16	13501	144
T18	3501	51
T19	3277	56
T20	193671	2800
T21	49105	0
T22	0	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3657826	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3657826
T1	494	1
T2	739	7
T3	31149	249
T4	67870	9
T15	27570	115
T16	13501	64
T18	3501	51
T19	3277	56
T20	193671	1969
T21	49105	0
T22	0	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1330636	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1330636
T1	494	6
T2	739	3
T3	31149	144
T4	67870	14
T15	27570	262
T16	13501	167
T18	3501	51
T19	3277	70
T20	193671	2625
T21	49105	2462

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3620318	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3620318
T1	494	6
T2	739	3
T3	31149	147
T4	67870	4
T15	27570	161
T16	13501	74
T18	3501	51
T19	3277	70
T20	193671	908
T21	49105	2540

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1297568	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1297568
T1	494	6
T2	739	5
T3	31149	283
T4	67870	14
T15	27570	200
T16	13501	121
T18	3501	57
T19	3277	52
T20	193671	2157
T21	49105	1740

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3293609	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3293609
T1	494	6
T2	739	5
T3	31149	224
T4	67870	4
T15	27570	80
T16	13501	41
T18	3501	57
T19	3277	52
T20	193671	569
T21	49105	2383

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1290480	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1290480
T1	494	13
T2	739	3
T3	31149	317
T4	67870	34
T15	27570	207
T16	13501	111
T18	3501	58
T19	3277	66
T20	193671	708
T21	49105	0
T22	0	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2741522	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2741522
T1	494	13
T2	739	3
T3	31149	285
T4	67870	11
T15	27570	113
T16	13501	38
T18	3501	58
T19	3277	66
T20	193671	1049
T21	49105	0
T22	0	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1309212	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1309212
T1	494	10
T2	739	3
T3	31149	163
T4	67870	54
T15	27570	156
T16	13501	97
T18	3501	68
T19	3277	43
T20	193671	2804
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3303296	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3303296
T1	494	10
T2	739	3
T3	31149	143
T4	67870	10
T15	27570	59
T16	13501	56
T18	3501	68
T19	3277	43
T20	193671	2914
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1255892	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1255892
T1	494	11
T2	739	4
T3	31149	184
T4	67870	20
T15	27570	218
T16	13501	122
T18	3501	53
T19	3277	47
T20	193671	2212
T21	49105	0
T22	0	11

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2869672	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2869672
T1	494	11
T2	739	4
T3	31149	226
T4	67870	76
T15	27570	109
T16	13501	28
T18	3501	53
T19	3277	47
T20	193671	2100
T21	49105	0
T22	0	11

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1285953	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1285953
T1	494	5
T2	739	6
T3	31149	147
T4	67870	14
T15	27570	301
T16	13501	98
T18	3501	60
T19	3277	44
T20	193671	633
T21	49105	0
T22	0	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3284737	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3284737
T1	494	5
T2	739	6
T3	31149	155
T4	67870	3
T15	27570	101
T16	13501	62
T18	3501	60
T19	3277	44
T20	193671	122
T21	49105	0
T22	0	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1269951	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1269951
T1	494	9
T2	739	6
T3	31149	322
T4	67870	8
T15	27570	223
T16	13501	91
T18	3501	43
T19	3277	63
T20	193671	1877
T21	49105	0
T22	0	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2666021	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2666021
T1	494	9
T2	739	6
T3	31149	265
T4	67870	3
T15	27570	81
T16	13501	44
T18	3501	43
T19	3277	63
T20	193671	773
T21	49105	0
T22	0	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1276381	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1276381
T1	494	9
T2	739	4
T3	31149	155
T4	67870	15
T15	27570	234
T16	13501	120
T18	3501	62
T19	3277	54
T20	193671	399
T21	49105	0
T22	0	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3214108	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3214108
T1	494	9
T2	739	4
T3	31149	127
T4	67870	3
T15	27570	92
T16	13501	23
T18	3501	62
T19	3277	54
T20	193671	425
T21	49105	0
T22	0	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1259016	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1259016
T1	494	10
T2	739	2
T3	31149	301
T4	67870	16
T15	27570	309
T16	13501	71
T18	3501	58
T19	3277	56
T20	193671	2499
T21	49105	0
T22	0	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2270869	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2270869
T1	494	10
T2	739	2
T3	31149	231
T4	67870	3
T15	27570	109
T16	13501	55
T18	3501	58
T19	3277	56
T20	193671	884
T21	49105	0
T22	0	5

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1282381	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1282381
T1	494	4
T2	739	3
T3	31149	265
T4	67870	4
T15	27570	281
T16	13501	97
T18	3501	40
T19	3277	56
T20	193671	1453
T21	49105	0
T22	0	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3336449	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3336449
T1	494	4
T2	739	3
T3	31149	173
T4	67870	2
T15	27570	120
T16	13501	73
T18	3501	40
T19	3277	56
T20	193671	558
T21	49105	0
T22	0	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1298559	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1298559
T1	494	7
T2	739	8
T3	31149	273
T4	67870	20
T15	27570	186
T16	13501	65
T18	3501	69
T19	3277	60
T20	193671	2105
T21	49105	0
T22	0	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3654680	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3654680
T1	494	7
T2	739	8
T3	31149	253
T4	67870	5
T15	27570	98
T16	13501	44
T18	3501	69
T19	3277	60
T20	193671	2540
T21	49105	0
T22	0	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1266927	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1266927
T1	494	3
T2	739	3
T3	31149	232
T4	67870	27
T15	27570	250
T16	13501	117
T18	3501	55
T19	3277	67
T20	193671	1046
T21	49105	0
T22	0	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3132601	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3132601
T1	494	3
T2	739	3
T3	31149	239
T4	67870	6
T15	27570	126
T16	13501	48
T18	3501	55
T19	3277	67
T20	193671	1847
T21	49105	0
T22	0	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1237208	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1237208
T1	494	6
T2	739	1
T3	31149	243
T4	67870	32
T15	27570	231
T16	13501	110
T18	3501	52
T19	3277	52
T20	193671	1707
T21	49105	0
T22	0	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2858804	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2858804
T1	494	6
T2	739	1
T3	31149	322
T4	67870	5
T15	27570	91
T16	13501	49
T18	3501	52
T19	3277	52
T20	193671	1822
T21	49105	0
T22	0	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1310450	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1310450
T1	494	6
T2	739	1
T3	31149	152
T4	67870	17
T15	27570	178
T16	13501	69
T18	3501	58
T19	3277	48
T20	193671	729
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3465699	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3465699
T1	494	6
T2	739	1
T3	31149	132
T4	67870	4
T15	27570	100
T16	13501	17
T18	3501	58
T19	3277	48
T20	193671	1469
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1245771	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1245771
T1	494	5
T2	739	6
T3	31149	284
T4	67870	24
T15	27570	242
T16	13501	133
T18	3501	60
T19	3277	63
T20	193671	2420
T21	49105	3967

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2973058	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2973058
T1	494	5
T2	739	6
T3	31149	238
T4	67870	6
T15	27570	93
T16	13501	60
T18	3501	60
T19	3277	63
T20	193671	1236
T21	49105	3917

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1300179	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1300179
T1	494	8
T2	739	7
T3	31149	273
T4	67870	38
T15	27570	219
T16	13501	64
T18	3501	67
T19	3277	79
T20	193671	3404
T21	49105	0
T22	0	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2951697	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2951697
T1	494	8
T2	739	7
T3	31149	243
T4	67870	9
T15	27570	133
T16	13501	45
T18	3501	67
T19	3277	79
T20	193671	2504
T21	49105	0
T22	0	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1309052	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1309052
T1	494	8
T2	739	9
T3	31149	205
T4	67870	20
T15	27570	294
T16	13501	96
T18	3501	73
T19	3277	52
T20	193671	1282
T21	49105	0
T22	0	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3715441	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3715441
T1	494	8
T2	739	9
T3	31149	182
T4	67870	5
T15	27570	147
T16	13501	34
T18	3501	73
T19	3277	52
T20	193671	1765
T21	49105	0
T22	0	8

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1239847	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1239847
T1	494	3
T2	739	6
T3	31149	286
T4	67870	16
T15	27570	276
T16	13501	95
T18	3501	61
T19	3277	55
T20	193671	3483
T21	49105	0
T22	0	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3145709	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3145709
T1	494	3
T2	739	6
T3	31149	236
T4	67870	3
T15	27570	141
T16	13501	52
T18	3501	61
T19	3277	55
T20	193671	4054
T21	49105	0
T22	0	4

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1320460	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1320460
T1	494	8
T2	739	4
T3	31149	153
T4	67870	30
T15	27570	255
T16	13501	112
T18	3501	62
T19	3277	65
T20	193671	1603
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2971383	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2971383
T1	494	8
T2	739	4
T3	31149	194
T4	67870	7
T15	27570	101
T16	13501	50
T18	3501	62
T19	3277	65
T20	193671	1100
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1313668	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1313668
T1	494	5
T2	739	5
T3	31149	206
T4	67870	9
T15	27570	234
T16	13501	103
T18	3501	48
T19	3277	71
T20	193671	2247
T21	49105	0
T22	0	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3917405	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3917405
T1	494	5
T2	739	5
T3	31149	255
T4	67870	1
T15	27570	120
T16	13501	66
T18	3501	48
T19	3277	71
T20	193671	1852
T21	49105	0
T22	0	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1296220	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1296220
T1	494	13
T2	739	3
T3	31149	191
T4	67870	13
T15	27570	191
T16	13501	93
T18	3501	48
T19	3277	56
T20	193671	1617
T21	49105	0
T22	0	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3070739	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3070739
T1	494	13
T2	739	3
T3	31149	149
T4	67870	4
T15	27570	108
T16	13501	34
T18	3501	48
T19	3277	56
T20	193671	1080
T21	49105	0
T22	0	9

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1291221	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1291221
T1	494	11
T2	739	3
T3	31149	328
T4	67870	43
T15	27570	246
T16	13501	90
T18	3501	57
T19	3277	70
T20	193671	940
T21	49105	4298

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3640085	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3640085
T1	494	11
T2	739	3
T3	31149	289
T4	67870	9
T15	27570	123
T16	13501	53
T18	3501	57
T19	3277	70
T20	193671	1311
T21	49105	4281

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1318247	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1318247
T1	494	4
T2	739	4
T3	31149	292
T4	67870	3
T15	27570	233
T16	13501	154
T18	3501	69
T19	3277	75
T20	193671	1215
T21	49105	2544

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	2752216	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	2752216
T1	494	4
T2	739	4
T3	31149	247
T4	67870	1
T15	27570	99
T16	13501	84
T18	3501	69
T19	3277	75
T20	193671	1287
T21	49105	2434

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	1353706	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	1353706
T1	494	6
T2	739	6
T3	31149	157
T4	67870	28
T15	27570	139
T16	13501	166
T18	3501	76
T19	3277	58
T20	193671	353
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	296607854	3162581	0	0
DataKnown_AKnownEnable	296607854	296483415	0	0
DepthKnown_A	296607854	296483415	0	0
RvalidKnown_A	296607854	296483415	0	0
WreadyKnown_A	296607854	296483415	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	296607854	3162581
T1	494	6
T2	739	6
T3	31149	186
T4	67870	5
T15	27570	85
T16	13501	66
T18	3501	76
T19	3277	58
T20	193671	471
T21	49105	0
T22	0	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

DepthKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

RvalidKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

WreadyKnown_A

Name	Attempts	Real Successes
Total	296607854	296483415
T1	494	480
T2	739	673
T3	31149	31120
T4	67870	67848
T15	27570	27546
T16	13501	13427
T18	3501	3455
T19	3277	3256
T20	193671	193597
T21	49105	49053

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T15	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1
T21	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children