Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_peri
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.16 100.00 95.80 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tlul_assert_device_adc_ctrl_aon 100.00 100.00 100.00 100.00
tlul_assert_device_alert_handler 100.00 100.00 100.00 100.00
tlul_assert_device_aon_timer_aon 100.00 100.00 100.00 100.00
tlul_assert_device_ast 100.00 100.00 100.00 100.00
tlul_assert_device_clkmgr_aon 100.00 100.00 100.00 100.00
tlul_assert_device_gpio 100.00 100.00 100.00 100.00
tlul_assert_device_i2c0 100.00 100.00 100.00 100.00
tlul_assert_device_i2c1 100.00 100.00 100.00 100.00
tlul_assert_device_i2c2 100.00 100.00 100.00 100.00
tlul_assert_device_lc_ctrl 100.00 100.00 100.00 100.00
tlul_assert_device_otp_ctrl__core 100.00 100.00 100.00 100.00
tlul_assert_device_otp_ctrl__prim 100.00 100.00 100.00 100.00
tlul_assert_device_pattgen 100.00 100.00 100.00 100.00
tlul_assert_device_pinmux_aon 100.00 100.00 100.00 100.00
tlul_assert_device_pwm_aon 100.00 100.00 100.00 100.00
tlul_assert_device_pwrmgr_aon 100.00 100.00 100.00 100.00
tlul_assert_device_rstmgr_aon 100.00 100.00 100.00 100.00
tlul_assert_device_rv_timer 100.00 100.00 100.00 100.00
tlul_assert_device_sensor_ctrl_aon 100.00 100.00 100.00 100.00
tlul_assert_device_spi_device 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_ret_aon__ram 100.00 100.00 100.00 100.00
tlul_assert_device_sram_ctrl_ret_aon__regs 100.00 100.00 100.00 100.00
tlul_assert_device_sysrst_ctrl_aon 100.00 100.00 100.00 100.00
tlul_assert_device_uart0 100.00 100.00 100.00 100.00
tlul_assert_device_uart1 100.00 100.00 100.00 100.00
tlul_assert_device_uart2 100.00 100.00 100.00 100.00
tlul_assert_device_uart3 100.00 100.00 100.00 100.00
tlul_assert_host_main 100.00 100.00 100.00 100.00
u_s1n_28 98.83 100.00 95.32 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : xbar_peri
Line No.TotalCoveredPercent
TOTAL111111100.00
CONT_ASSIGN11200
CONT_ASSIGN12611100.00
CONT_ASSIGN12711100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN15911100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16211100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17711100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18111100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19011100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19611100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN19911100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20211100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20711100.00
CONT_ASSIGN20811100.00
ALWAYS2125555100.00

111 logic unused_scanmode; 112 excluded assign unused_scanmode = ^scanmode_i; 113 114 tl_h2d_t tl_s1n_28_us_h2d ; 115 tl_d2h_t tl_s1n_28_us_d2h ; 116 117 118 tl_h2d_t tl_s1n_28_ds_h2d [27]; 119 tl_d2h_t tl_s1n_28_ds_d2h [27]; 120 121 // Create steering signal 122 logic [4:0] dev_sel_s1n_28; 123 124 125 126 1/1 assign tl_uart0_o = tl_s1n_28_ds_h2d[0]; Tests: T1 T2 T3  127 1/1 assign tl_s1n_28_ds_d2h[0] = tl_uart0_i; Tests: T1 T2 T3  128 129 1/1 assign tl_uart1_o = tl_s1n_28_ds_h2d[1]; Tests: T1 T2 T3  130 1/1 assign tl_s1n_28_ds_d2h[1] = tl_uart1_i; Tests: T1 T2 T3  131 132 1/1 assign tl_uart2_o = tl_s1n_28_ds_h2d[2]; Tests: T1 T2 T3  133 1/1 assign tl_s1n_28_ds_d2h[2] = tl_uart2_i; Tests: T1 T2 T3  134 135 1/1 assign tl_uart3_o = tl_s1n_28_ds_h2d[3]; Tests: T1 T2 T3  136 1/1 assign tl_s1n_28_ds_d2h[3] = tl_uart3_i; Tests: T1 T2 T3  137 138 1/1 assign tl_i2c0_o = tl_s1n_28_ds_h2d[4]; Tests: T1 T2 T3  139 1/1 assign tl_s1n_28_ds_d2h[4] = tl_i2c0_i; Tests: T1 T2 T3  140 141 1/1 assign tl_i2c1_o = tl_s1n_28_ds_h2d[5]; Tests: T1 T2 T3  142 1/1 assign tl_s1n_28_ds_d2h[5] = tl_i2c1_i; Tests: T1 T2 T3  143 144 1/1 assign tl_i2c2_o = tl_s1n_28_ds_h2d[6]; Tests: T1 T2 T3  145 1/1 assign tl_s1n_28_ds_d2h[6] = tl_i2c2_i; Tests: T1 T2 T3  146 147 1/1 assign tl_pattgen_o = tl_s1n_28_ds_h2d[7]; Tests: T1 T2 T3  148 1/1 assign tl_s1n_28_ds_d2h[7] = tl_pattgen_i; Tests: T1 T2 T3  149 150 1/1 assign tl_gpio_o = tl_s1n_28_ds_h2d[8]; Tests: T1 T2 T3  151 1/1 assign tl_s1n_28_ds_d2h[8] = tl_gpio_i; Tests: T1 T2 T3  152 153 1/1 assign tl_spi_device_o = tl_s1n_28_ds_h2d[9]; Tests: T1 T2 T3  154 1/1 assign tl_s1n_28_ds_d2h[9] = tl_spi_device_i; Tests: T1 T2 T3  155 156 1/1 assign tl_rv_timer_o = tl_s1n_28_ds_h2d[10]; Tests: T1 T2 T3  157 1/1 assign tl_s1n_28_ds_d2h[10] = tl_rv_timer_i; Tests: T1 T2 T3  158 159 1/1 assign tl_pwrmgr_aon_o = tl_s1n_28_ds_h2d[11]; Tests: T1 T2 T3  160 1/1 assign tl_s1n_28_ds_d2h[11] = tl_pwrmgr_aon_i; Tests: T1 T2 T3  161 162 1/1 assign tl_rstmgr_aon_o = tl_s1n_28_ds_h2d[12]; Tests: T1 T2 T3  163 1/1 assign tl_s1n_28_ds_d2h[12] = tl_rstmgr_aon_i; Tests: T1 T2 T3  164 165 1/1 assign tl_clkmgr_aon_o = tl_s1n_28_ds_h2d[13]; Tests: T1 T2 T3  166 1/1 assign tl_s1n_28_ds_d2h[13] = tl_clkmgr_aon_i; Tests: T1 T2 T3  167 168 1/1 assign tl_pinmux_aon_o = tl_s1n_28_ds_h2d[14]; Tests: T1 T2 T3  169 1/1 assign tl_s1n_28_ds_d2h[14] = tl_pinmux_aon_i; Tests: T1 T2 T3  170 171 1/1 assign tl_otp_ctrl__core_o = tl_s1n_28_ds_h2d[15]; Tests: T1 T2 T3  172 1/1 assign tl_s1n_28_ds_d2h[15] = tl_otp_ctrl__core_i; Tests: T1 T2 T3  173 174 1/1 assign tl_otp_ctrl__prim_o = tl_s1n_28_ds_h2d[16]; Tests: T1 T2 T3  175 1/1 assign tl_s1n_28_ds_d2h[16] = tl_otp_ctrl__prim_i; Tests: T1 T2 T3  176 177 1/1 assign tl_lc_ctrl_o = tl_s1n_28_ds_h2d[17]; Tests: T1 T2 T3  178 1/1 assign tl_s1n_28_ds_d2h[17] = tl_lc_ctrl_i; Tests: T1 T2 T3  179 180 1/1 assign tl_sensor_ctrl_aon_o = tl_s1n_28_ds_h2d[18]; Tests: T1 T2 T3  181 1/1 assign tl_s1n_28_ds_d2h[18] = tl_sensor_ctrl_aon_i; Tests: T1 T2 T3  182 183 1/1 assign tl_alert_handler_o = tl_s1n_28_ds_h2d[19]; Tests: T1 T2 T3  184 1/1 assign tl_s1n_28_ds_d2h[19] = tl_alert_handler_i; Tests: T1 T2 T3  185 186 1/1 assign tl_ast_o = tl_s1n_28_ds_h2d[20]; Tests: T1 T2 T3  187 1/1 assign tl_s1n_28_ds_d2h[20] = tl_ast_i; Tests: T1 T2 T3  188 189 1/1 assign tl_sram_ctrl_ret_aon__ram_o = tl_s1n_28_ds_h2d[21]; Tests: T1 T2 T3  190 1/1 assign tl_s1n_28_ds_d2h[21] = tl_sram_ctrl_ret_aon__ram_i; Tests: T1 T2 T3  191 192 1/1 assign tl_sram_ctrl_ret_aon__regs_o = tl_s1n_28_ds_h2d[22]; Tests: T1 T2 T3  193 1/1 assign tl_s1n_28_ds_d2h[22] = tl_sram_ctrl_ret_aon__regs_i; Tests: T1 T2 T3  194 195 1/1 assign tl_aon_timer_aon_o = tl_s1n_28_ds_h2d[23]; Tests: T1 T2 T3  196 1/1 assign tl_s1n_28_ds_d2h[23] = tl_aon_timer_aon_i; Tests: T1 T2 T3  197 198 1/1 assign tl_adc_ctrl_aon_o = tl_s1n_28_ds_h2d[24]; Tests: T1 T2 T3  199 1/1 assign tl_s1n_28_ds_d2h[24] = tl_adc_ctrl_aon_i; Tests: T1 T2 T3  200 201 1/1 assign tl_sysrst_ctrl_aon_o = tl_s1n_28_ds_h2d[25]; Tests: T1 T2 T3  202 1/1 assign tl_s1n_28_ds_d2h[25] = tl_sysrst_ctrl_aon_i; Tests: T1 T2 T3  203 204 1/1 assign tl_pwm_aon_o = tl_s1n_28_ds_h2d[26]; Tests: T1 T2 T3  205 1/1 assign tl_s1n_28_ds_d2h[26] = tl_pwm_aon_i; Tests: T1 T2 T3  206 207 1/1 assign tl_s1n_28_us_h2d = tl_main_i; Tests: T1 T2 T3  208 1/1 assign tl_main_o = tl_s1n_28_us_d2h; Tests: T1 T2 T3  209 210 always_comb begin 211 // default steering to generate error response if address is not within the range 212 1/1 dev_sel_s1n_28 = 5'd27; Tests: T1 T2 T3  213 1/1 if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  214 ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin 215 1/1 dev_sel_s1n_28 = 5'd0; Tests: T1 T2 T3  216 217 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  218 ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin 219 1/1 dev_sel_s1n_28 = 5'd1; Tests: T1 T2 T3  220 221 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  222 ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin 223 1/1 dev_sel_s1n_28 = 5'd2; Tests: T1 T2 T3  224 225 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  226 ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin 227 1/1 dev_sel_s1n_28 = 5'd3; Tests: T1 T2 T3  228 229 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  230 ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin 231 1/1 dev_sel_s1n_28 = 5'd4; Tests: T1 T2 T3  232 233 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  234 ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin 235 1/1 dev_sel_s1n_28 = 5'd5; Tests: T1 T2 T3  236 237 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  238 ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin 239 1/1 dev_sel_s1n_28 = 5'd6; Tests: T1 T2 T3  240 241 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  242 ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin 243 1/1 dev_sel_s1n_28 = 5'd7; Tests: T1 T2 T3  244 245 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  246 ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin 247 1/1 dev_sel_s1n_28 = 5'd8; Tests: T1 T2 T3  248 249 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  250 ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin 251 1/1 dev_sel_s1n_28 = 5'd9; Tests: T1 T2 T3  252 253 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  254 ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin 255 1/1 dev_sel_s1n_28 = 5'd10; Tests: T1 T2 T3  256 257 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  258 ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin 259 1/1 dev_sel_s1n_28 = 5'd11; Tests: T1 T2 T3  260 261 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  262 ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin 263 1/1 dev_sel_s1n_28 = 5'd12; Tests: T1 T2 T3  264 265 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  266 ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin 267 1/1 dev_sel_s1n_28 = 5'd13; Tests: T1 T2 T3  268 269 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  270 ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin 271 1/1 dev_sel_s1n_28 = 5'd14; Tests: T1 T2 T3  272 273 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  274 ~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin 275 1/1 dev_sel_s1n_28 = 5'd15; Tests: T1 T2 T3  276 277 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  278 ~(ADDR_MASK_OTP_CTRL__PRIM)) == ADDR_SPACE_OTP_CTRL__PRIM) begin 279 1/1 dev_sel_s1n_28 = 5'd16; Tests: T1 T2 T3  280 281 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  282 ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin 283 1/1 dev_sel_s1n_28 = 5'd17; Tests: T1 T2 T3  284 285 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  286 ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin 287 1/1 dev_sel_s1n_28 = 5'd18; Tests: T1 T2 T3  288 289 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  290 ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin 291 1/1 dev_sel_s1n_28 = 5'd19; Tests: T1 T2 T3  292 293 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  294 ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin 295 1/1 dev_sel_s1n_28 = 5'd20; Tests: T1 T2 T3  296 297 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  298 ~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin 299 1/1 dev_sel_s1n_28 = 5'd21; Tests: T1 T2 T3  300 301 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  302 ~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin 303 1/1 dev_sel_s1n_28 = 5'd22; Tests: T1 T2 T3  304 305 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  306 ~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin 307 1/1 dev_sel_s1n_28 = 5'd23; Tests: T1 T2 T3  308 309 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  310 ~(ADDR_MASK_ADC_CTRL_AON)) == ADDR_SPACE_ADC_CTRL_AON) begin 311 1/1 dev_sel_s1n_28 = 5'd24; Tests: T1 T2 T3  312 313 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  314 ~(ADDR_MASK_SYSRST_CTRL_AON)) == ADDR_SPACE_SYSRST_CTRL_AON) begin 315 1/1 dev_sel_s1n_28 = 5'd25; Tests: T1 T2 T3  316 317 1/1 end else if ((tl_s1n_28_us_h2d.a_address & Tests: T1 T2 T3  318 ~(ADDR_MASK_PWM_AON)) == ADDR_SPACE_PWM_AON) begin 319 1/1 dev_sel_s1n_28 = 5'd26; Tests: T1 T2 T3  320 end MISSING_ELSE

Cond Coverage for Module : xbar_peri
TotalCoveredPercent
Conditions5454100.00
Logical5454100.00
Non-Logical00
Event00

 LINE       213
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART0)) == tl_peri_pkg::ADDR_SPACE_UART0)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       217
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART1)) == tl_peri_pkg::ADDR_SPACE_UART1)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       221
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART2)) == tl_peri_pkg::ADDR_SPACE_UART2)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       225
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_UART3)) == tl_peri_pkg::ADDR_SPACE_UART3)
            ------------------------------------------------1------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       229
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C0)) == tl_peri_pkg::ADDR_SPACE_I2C0)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       233
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C1)) == tl_peri_pkg::ADDR_SPACE_I2C1)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       237
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_I2C2)) == tl_peri_pkg::ADDR_SPACE_I2C2)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PATTGEN)) == tl_peri_pkg::ADDR_SPACE_PATTGEN)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_GPIO)) == tl_peri_pkg::ADDR_SPACE_GPIO)
            -----------------------------------------------1-----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       249
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SPI_DEVICE)) == tl_peri_pkg::ADDR_SPACE_SPI_DEVICE)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       253
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_RV_TIMER)) == tl_peri_pkg::ADDR_SPACE_RV_TIMER)
            ---------------------------------------------------1---------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PWRMGR_AON)) == tl_peri_pkg::ADDR_SPACE_PWRMGR_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       261
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_RSTMGR_AON)) == tl_peri_pkg::ADDR_SPACE_RSTMGR_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       265
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_CLKMGR_AON)) == tl_peri_pkg::ADDR_SPACE_CLKMGR_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       269
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PINMUX_AON)) == tl_peri_pkg::ADDR_SPACE_PINMUX_AON)
            -----------------------------------------------------1-----------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       273
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_OTP_CTRL__CORE)) == tl_peri_pkg::ADDR_SPACE_OTP_CTRL__CORE)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       277
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_OTP_CTRL__PRIM)) == tl_peri_pkg::ADDR_SPACE_OTP_CTRL__PRIM)
            ---------------------------------------------------------1---------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       281
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_LC_CTRL)) == tl_peri_pkg::ADDR_SPACE_LC_CTRL)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       285
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SENSOR_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_SENSOR_CTRL_AON)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       289
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_ALERT_HANDLER)) == tl_peri_pkg::ADDR_SPACE_ALERT_HANDLER)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_AST)) == tl_peri_pkg::ADDR_SPACE_AST)
            ----------------------------------------------1----------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       297
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == tl_peri_pkg::ADDR_SPACE_SRAM_CTRL_RET_AON__RAM)
            -----------------------------------------------------------------1-----------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == tl_peri_pkg::ADDR_SPACE_SRAM_CTRL_RET_AON__REGS)
            ------------------------------------------------------------------1------------------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       305
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_AON_TIMER_AON)) == tl_peri_pkg::ADDR_SPACE_AON_TIMER_AON)
            --------------------------------------------------------1--------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       309
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_ADC_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_ADC_CTRL_AON)
            -------------------------------------------------------1-------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       313
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_SYSRST_CTRL_AON)) == tl_peri_pkg::ADDR_SPACE_SYSRST_CTRL_AON)
            ----------------------------------------------------------1----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       317
 EXPRESSION ((tl_s1n_28_us_h2d.a_address & (~tl_peri_pkg::ADDR_MASK_PWM_AON)) == tl_peri_pkg::ADDR_SPACE_PWM_AON)
            --------------------------------------------------1--------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Toggle Coverage for Module : xbar_peri
TotalCoveredPercent
Totals 618 618 100.00
Total Bits 8218 8218 100.00
Total Bits 0->1 4109 4109 100.00
Total Bits 1->0 4109 4109 100.00

Ports 618 618 100.00
Port Bits 8218 8218 100.00
Port Bits 0->1 4109 4109 100.00
Port Bits 1->0 4109 4109 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_peri_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_peri_ni Yes Yes T25,T271,T272 Yes T1,T2,T3 INPUT
tl_main_i.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_main_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT
tl_main_i.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT
tl_main_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_main_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_main_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_main_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_main_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_main_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart0_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart0_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_address[29:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_uart0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart0_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_uart0_i.d_error Yes Yes T4,T18,T19 Yes T2,T18,T19 INPUT
tl_uart0_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_uart0_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_uart0_i.d_data[31:0] Yes Yes T1,T3,T18 Yes T1,T3,T4 INPUT
tl_uart0_i.d_sink Yes Yes T1,T3,T18 Yes T1,T2,T3 INPUT
tl_uart0_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart0_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart0_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T3,T4 INPUT
tl_uart0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart1_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_address[29:17] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_uart1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart1_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_uart1_i.d_error Yes Yes T1,T3,T18 Yes T1,T2,T3 INPUT
tl_uart1_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart1_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_uart1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart2_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart2_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart2_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[16:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_address[29:18] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_uart2_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart2_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart2_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_uart2_i.d_error Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart2_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart2_i.d_user.rsp_intg[6:0] Yes Yes T3,T4,T18 Yes T2,T3,T4 INPUT
tl_uart2_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart2_i.d_sink Yes Yes T2,T3,T4 Yes T3,T4,T18 INPUT
tl_uart2_i.d_source[7:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_uart2_i.d_size[1:0] Yes Yes T3,T4,T18 Yes T3,T4,T18 INPUT
tl_uart2_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart2_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_uart2_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart2_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart3_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart3_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_uart3_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_address[29:18] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_uart3_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_uart3_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_uart3_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_uart3_i.d_error Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_uart3_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_uart3_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart3_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_uart3_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_uart3_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_uart3_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_uart3_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_uart3_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T3,T4 INPUT
tl_uart3_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_uart3_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c0_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_i2c0_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_i2c0_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[18:7] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_i2c0_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c0_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c0_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_i2c0_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c0_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c0_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c0_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c0_i.d_sink Yes Yes T1,T2,T3 Yes T1,T3,T18 INPUT
tl_i2c0_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c0_i.d_size[1:0] Yes Yes T1,T3,T18 Yes T1,T3,T18 INPUT
tl_i2c0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c0_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T3,T4 INPUT
tl_i2c0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c1_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_i2c1_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_i2c1_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[18:17] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_i2c1_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c1_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c1_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_i2c1_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i2c1_i.d_sink Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_i2c1_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i2c1_i.d_size[1:0] Yes Yes T1,T3,T18 Yes T1,T3,T18 INPUT
tl_i2c1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c1_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_i2c1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c1_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c2_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_i2c2_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_i2c2_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[16:7] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[18] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_i2c2_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_i2c2_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_i2c2_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_i2c2_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i2c2_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i2c2_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i2c2_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i2c2_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i2c2_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_i2c2_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pattgen_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pattgen_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[16:6] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_address[19:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_address[29:20] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_pattgen_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pattgen_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pattgen_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_size[1:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_pattgen_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pattgen_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_pattgen_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pattgen_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pwm_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_pwm_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwm_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwm_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_sink Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_pwm_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pwm_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_pwm_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pwm_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_gpio_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_gpio_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[17:6] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_address[29:19] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_gpio_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_gpio_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_gpio_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_gpio_i.d_error Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_gpio_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_gpio_i.d_sink Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_gpio_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_gpio_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_gpio_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_gpio_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_gpio_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_spi_device_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_spi_device_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[12:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[15:13] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_address[29:19] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_spi_device_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_device_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_spi_device_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_error Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_spi_device_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_device_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_spi_device_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_device_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_rv_timer_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[8:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[19:9] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_rv_timer_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_timer_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_timer_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_error Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_rv_timer_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_rv_timer_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_rv_timer_i.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_timer_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_timer_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T3,T4 INPUT
tl_rv_timer_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_timer_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pwrmgr_aon_o.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[21:7] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_pwrmgr_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pwrmgr_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_error Yes Yes T1,T3,T18 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T18 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T18 INPUT
tl_pwrmgr_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T3,T18 INPUT
tl_pwrmgr_aon_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T3,T18 INPUT
tl_pwrmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pwrmgr_aon_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_pwrmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pwrmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_rstmgr_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[21:17] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_rstmgr_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rstmgr_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T3,T4 INPUT
tl_rstmgr_aon_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_rstmgr_aon_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T18 INPUT
tl_rstmgr_aon_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T3,T4,T18 INPUT
tl_rstmgr_aon_i.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_rstmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rstmgr_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T3,T4,T18 INPUT
tl_rstmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rstmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_clkmgr_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[16:7] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[21:18] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_clkmgr_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_clkmgr_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_clkmgr_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_clkmgr_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_clkmgr_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_pinmux_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[16:12] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_address[18:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_pinmux_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_pinmux_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_pinmux_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_sink Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_pinmux_aon_i.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_pinmux_aon_i.d_opcode[0] Yes Yes *T1,*T3,*T4 Yes T1,T2,T3 INPUT
tl_pinmux_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_pinmux_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_otp_ctrl__core_o.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[15:12] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_otp_ctrl__core_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__core_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_error Yes Yes T3,T4,T18 Yes T2,T3,T4 INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T3,T4,T18 Yes T1,T3,T18 INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_otp_ctrl__core_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_otp_ctrl__core_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_size[1:0] Yes Yes T2,T3,T18 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__core_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[4:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[14:5] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_address[17:15] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[19:18] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_otp_ctrl__prim_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_otp_ctrl__prim_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_error Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_data[31:0] Yes Yes T1,T3,T18 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_otp_ctrl__prim_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_otp_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__prim_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T3,T18 INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otp_ctrl__prim_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_lc_ctrl_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_lc_ctrl_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[17:8] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_lc_ctrl_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_lc_ctrl_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_lc_ctrl_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_lc_ctrl_i.d_error Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_lc_ctrl_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_lc_ctrl_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_lc_ctrl_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_lc_ctrl_i.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_lc_ctrl_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_lc_ctrl_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_lc_ctrl_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_lc_ctrl_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[15:7] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[18:17] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[21:20] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_sensor_ctrl_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sensor_ctrl_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_error Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sensor_ctrl_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sensor_ctrl_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_alert_handler_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[10:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[15:11] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[17] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[19] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_address[29:21] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_alert_handler_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_alert_handler_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_alert_handler_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_error Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_alert_handler_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_alert_handler_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_alert_handler_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_alert_handler_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0] Yes Yes T1,T3,T18 Yes T1,T3,T18 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[19:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[21] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[11:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[20:12] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[22:21] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_aon_timer_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[15:6] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_aon_timer_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_aon_timer_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_i.d_data[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_i.d_sink Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_aon_timer_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T3,T4 INPUT
tl_aon_timer_aon_i.d_size[1:0] Yes Yes T1,T3,T18 Yes T1,T2,T3 INPUT
tl_aon_timer_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aon_timer_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T3,T4 INPUT
tl_aon_timer_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aon_timer_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[15:8] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[21:18] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sysrst_ctrl_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T3,T18 INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_source[7:0] Yes Yes T2,T3,T18 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sysrst_ctrl_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[17:7] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_address[18] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[21:19] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_adc_ctrl_aon_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_adc_ctrl_aon_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_adc_ctrl_aon_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_adc_ctrl_aon_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_o.d_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_user.instr_type[3:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_ast_o.a_user.rsvd[4:0] Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
tl_ast_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[9:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[18:10] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[21:20] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_address[29:23] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_address[30] Yes Yes *T1,*T3,*T18 Yes T3,T18,T16 OUTPUT
tl_ast_o.a_address[31] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_ast_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_ast_i.a_ready Yes Yes T3,T4,T16 Yes T1,T2,T3 INPUT
tl_ast_i.d_error Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_ast_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_ast_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_ast_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : xbar_peri
Line No.TotalCoveredPercent
Branches 28 28 100.00
IF 213 28 28 100.00


213 if ((tl_s1n_28_us_h2d.a_address & -1- 214 ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin 215 dev_sel_s1n_28 = 5'd0; ==> 216 217 end else if ((tl_s1n_28_us_h2d.a_address & -2- 218 ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin 219 dev_sel_s1n_28 = 5'd1; ==> 220 221 end else if ((tl_s1n_28_us_h2d.a_address & -3- 222 ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin 223 dev_sel_s1n_28 = 5'd2; ==> 224 225 end else if ((tl_s1n_28_us_h2d.a_address & -4- 226 ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin 227 dev_sel_s1n_28 = 5'd3; ==> 228 229 end else if ((tl_s1n_28_us_h2d.a_address & -5- 230 ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin 231 dev_sel_s1n_28 = 5'd4; ==> 232 233 end else if ((tl_s1n_28_us_h2d.a_address & -6- 234 ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin 235 dev_sel_s1n_28 = 5'd5; ==> 236 237 end else if ((tl_s1n_28_us_h2d.a_address & -7- 238 ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin 239 dev_sel_s1n_28 = 5'd6; ==> 240 241 end else if ((tl_s1n_28_us_h2d.a_address & -8- 242 ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin 243 dev_sel_s1n_28 = 5'd7; ==> 244 245 end else if ((tl_s1n_28_us_h2d.a_address & -9- 246 ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin 247 dev_sel_s1n_28 = 5'd8; ==> 248 249 end else if ((tl_s1n_28_us_h2d.a_address & -10- 250 ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin 251 dev_sel_s1n_28 = 5'd9; ==> 252 253 end else if ((tl_s1n_28_us_h2d.a_address & -11- 254 ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin 255 dev_sel_s1n_28 = 5'd10; ==> 256 257 end else if ((tl_s1n_28_us_h2d.a_address & -12- 258 ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin 259 dev_sel_s1n_28 = 5'd11; ==> 260 261 end else if ((tl_s1n_28_us_h2d.a_address & -13- 262 ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin 263 dev_sel_s1n_28 = 5'd12; ==> 264 265 end else if ((tl_s1n_28_us_h2d.a_address & -14- 266 ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin 267 dev_sel_s1n_28 = 5'd13; ==> 268 269 end else if ((tl_s1n_28_us_h2d.a_address & -15- 270 ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin 271 dev_sel_s1n_28 = 5'd14; ==> 272 273 end else if ((tl_s1n_28_us_h2d.a_address & -16- 274 ~(ADDR_MASK_OTP_CTRL__CORE)) == ADDR_SPACE_OTP_CTRL__CORE) begin 275 dev_sel_s1n_28 = 5'd15; ==> 276 277 end else if ((tl_s1n_28_us_h2d.a_address & -17- 278 ~(ADDR_MASK_OTP_CTRL__PRIM)) == ADDR_SPACE_OTP_CTRL__PRIM) begin 279 dev_sel_s1n_28 = 5'd16; ==> 280 281 end else if ((tl_s1n_28_us_h2d.a_address & -18- 282 ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin 283 dev_sel_s1n_28 = 5'd17; ==> 284 285 end else if ((tl_s1n_28_us_h2d.a_address & -19- 286 ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin 287 dev_sel_s1n_28 = 5'd18; ==> 288 289 end else if ((tl_s1n_28_us_h2d.a_address & -20- 290 ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin 291 dev_sel_s1n_28 = 5'd19; ==> 292 293 end else if ((tl_s1n_28_us_h2d.a_address & -21- 294 ~(ADDR_MASK_AST)) == ADDR_SPACE_AST) begin 295 dev_sel_s1n_28 = 5'd20; ==> 296 297 end else if ((tl_s1n_28_us_h2d.a_address & -22- 298 ~(ADDR_MASK_SRAM_CTRL_RET_AON__RAM)) == ADDR_SPACE_SRAM_CTRL_RET_AON__RAM) begin 299 dev_sel_s1n_28 = 5'd21; ==> 300 301 end else if ((tl_s1n_28_us_h2d.a_address & -23- 302 ~(ADDR_MASK_SRAM_CTRL_RET_AON__REGS)) == ADDR_SPACE_SRAM_CTRL_RET_AON__REGS) begin 303 dev_sel_s1n_28 = 5'd22; ==> 304 305 end else if ((tl_s1n_28_us_h2d.a_address & -24- 306 ~(ADDR_MASK_AON_TIMER_AON)) == ADDR_SPACE_AON_TIMER_AON) begin 307 dev_sel_s1n_28 = 5'd23; ==> 308 309 end else if ((tl_s1n_28_us_h2d.a_address & -25- 310 ~(ADDR_MASK_ADC_CTRL_AON)) == ADDR_SPACE_ADC_CTRL_AON) begin 311 dev_sel_s1n_28 = 5'd24; ==> 312 313 end else if ((tl_s1n_28_us_h2d.a_address & -26- 314 ~(ADDR_MASK_SYSRST_CTRL_AON)) == ADDR_SPACE_SYSRST_CTRL_AON) begin 315 dev_sel_s1n_28 = 5'd25; ==> 316 317 end else if ((tl_s1n_28_us_h2d.a_address & -27- 318 ~(ADDR_MASK_PWM_AON)) == ADDR_SPACE_PWM_AON) begin 319 dev_sel_s1n_28 = 5'd26; ==> 320 end MISSING_ELSE ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16--17--18--19--20--21--22--23--24--25--26--27-StatusTests
1 - - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 1 - - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 1 - - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%