Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1600231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252177

1

T1

29

T2

17

T3

70

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	627418	1			T1	48		T2	52		T3	140
values[0x0]	597059	1			T1	52		T2	41		T3	146
values[0x1]	627931	1			T1	60		T2	44		T3	137

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1239291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

613117

1

T1

57

T2

37

T3

141

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7284	1			T3	1		T21	3		T17	8
valid_sources[0x01]	7870	1			T3	3		T16	4		T18	1
valid_sources[0x02]	7512	1			T3	5		T4	2		T17	10
valid_sources[0x03]	7216	1			T3	1		T21	1		T17	7
valid_sources[0x04]	7124	1			T3	2		T21	3		T17	7
valid_sources[0x05]	7605	1			T3	2		T4	4		T5	1
valid_sources[0x06]	6579	1			T4	1		T18	1		T23	1
valid_sources[0x07]	6241	1			T2	2		T3	1		T21	2
valid_sources[0x08]	7136	1			T2	1		T3	1		T4	1
valid_sources[0x09]	7164	1			T3	1		T4	1		T21	1
valid_sources[0x0a]	7435	1			T3	3		T4	3		T17	21
valid_sources[0x0b]	7137	1			T2	4		T3	2		T4	3
valid_sources[0x0c]	7137	1			T3	3		T5	1		T16	2
valid_sources[0x0d]	7195	1			T3	1		T4	3		T17	10
valid_sources[0x0e]	7731	1			T3	2		T17	5		T19	12
valid_sources[0x0f]	7752	1			T3	3		T4	1		T17	1
valid_sources[0x10]	7403	1			T3	3		T17	27		T18	1
valid_sources[0x11]	7982	1			T16	1		T17	12		T26	9
valid_sources[0x12]	7155	1			T3	2		T4	1		T16	2
valid_sources[0x13]	7316	1			T3	2		T4	1		T17	8
valid_sources[0x14]	6950	1			T2	6		T3	1		T16	6
valid_sources[0x15]	8245	1			T3	1		T21	1		T17	1
valid_sources[0x16]	7077	1			T2	1		T4	2		T17	11
valid_sources[0x17]	6633	1			T2	1		T4	2		T17	1
valid_sources[0x18]	6735	1			T2	2		T3	2		T17	2
valid_sources[0x19]	6568	1			T17	12		T18	1		T19	10
valid_sources[0x1a]	7101	1			T3	4		T4	1		T21	1
valid_sources[0x1b]	6870	1			T4	6		T17	4		T19	11
valid_sources[0x1c]	6994	1			T3	1		T21	2		T16	4
valid_sources[0x1d]	7775	1			T2	1		T3	2		T18	1
valid_sources[0x1e]	7100	1			T2	1		T3	3		T17	24
valid_sources[0x1f]	6970	1			T3	2		T17	2		T19	8
valid_sources[0x20]	7348	1			T3	1		T16	2		T17	19
valid_sources[0x21]	6859	1			T2	1		T3	2		T21	1
valid_sources[0x22]	8436	1			T3	2		T17	6		T23	2
valid_sources[0x23]	7298	1			T3	3		T4	3		T21	1
valid_sources[0x24]	7499	1			T3	3		T21	1		T17	15
valid_sources[0x25]	7231	1			T2	3		T3	1		T5	1
valid_sources[0x26]	7037	1			T3	1		T4	2		T17	9
valid_sources[0x27]	7567	1			T4	3		T16	1		T17	7
valid_sources[0x28]	6971	1			T3	2		T4	1		T17	1
valid_sources[0x29]	7484	1			T3	2		T17	12		T18	1
valid_sources[0x2a]	6799	1			T2	3		T5	1		T17	5
valid_sources[0x2b]	6810	1			T3	4		T4	2		T16	1
valid_sources[0x2c]	7353	1			T3	2		T4	4		T5	1
valid_sources[0x2d]	7653	1			T3	3		T17	7		T19	3
valid_sources[0x2e]	6960	1			T3	1		T4	6		T17	43
valid_sources[0x2f]	6625	1			T2	2		T3	1		T21	1
valid_sources[0x30]	7641	1			T3	2		T4	7		T21	1
valid_sources[0x31]	7240	1			T2	1		T4	1		T21	2
valid_sources[0x32]	7415	1			T3	4		T4	4		T17	2
valid_sources[0x33]	7910	1			T2	1		T16	1		T17	6
valid_sources[0x34]	7289	1			T3	1		T17	4		T18	1
valid_sources[0x35]	6404	1			T3	2		T18	1		T19	5
valid_sources[0x36]	7708	1			T4	3		T16	3		T17	7
valid_sources[0x37]	7243	1			T3	4		T21	1		T17	2
valid_sources[0x38]	7209	1			T2	2		T4	5		T16	3
valid_sources[0x39]	6690	1			T2	1		T3	4		T23	1
valid_sources[0x3a]	6914	1			T3	1		T19	5		T26	1
valid_sources[0x3b]	7410	1			T3	3		T16	2		T17	2
valid_sources[0x3c]	6642	1			T4	2		T16	2		T17	2
valid_sources[0x3d]	7370	1			T17	12		T18	3		T19	2
valid_sources[0x3e]	6666	1			T3	1		T4	4		T17	5
valid_sources[0x3f]	6398	1			T3	1		T16	4		T17	4
valid_sources[0x40]	7713	1			T3	2		T17	8		T18	2
valid_sources[0x41]	7450	1			T17	1		T23	1		T19	4
valid_sources[0x42]	7230	1			T3	2		T19	9		T26	7
valid_sources[0x43]	7210	1			T2	1		T3	3		T4	2
valid_sources[0x44]	6525	1			T3	1		T5	1		T17	6
valid_sources[0x45]	7050	1			T3	1		T4	6		T16	1
valid_sources[0x46]	6727	1			T3	3		T5	1		T21	1
valid_sources[0x47]	6947	1			T21	1		T17	21		T19	2
valid_sources[0x48]	7399	1			T1	80		T16	4		T17	2
valid_sources[0x49]	6764	1			T2	1		T3	1		T21	2
valid_sources[0x4a]	6931	1			T3	3		T4	2		T5	1
valid_sources[0x4b]	8071	1			T2	2		T3	3		T4	5
valid_sources[0x4c]	7313	1			T16	1		T17	3		T23	1
valid_sources[0x4d]	6968	1			T3	2		T17	4		T23	1
valid_sources[0x4e]	7079	1			T4	1		T21	1		T16	10
valid_sources[0x4f]	7906	1			T3	5		T4	3		T21	1
valid_sources[0x50]	6468	1			T21	1		T17	29		T23	1
valid_sources[0x51]	7449	1			T3	3		T4	13		T18	1
valid_sources[0x52]	7846	1			T3	3		T4	3		T16	1
valid_sources[0x53]	7708	1			T3	1		T16	1		T17	11
valid_sources[0x54]	6746	1			T3	1		T21	1		T17	1
valid_sources[0x55]	7140	1			T5	2		T17	1		T22	65
valid_sources[0x56]	7462	1			T3	2		T4	2		T16	1
valid_sources[0x57]	7189	1			T2	2		T3	1		T21	2
valid_sources[0x58]	7553	1			T5	1		T16	5		T17	4
valid_sources[0x59]	7066	1			T2	1		T3	3		T17	2
valid_sources[0x5a]	7177	1			T3	1		T17	6		T23	1
valid_sources[0x5b]	7984	1			T3	2		T21	1		T17	24
valid_sources[0x5c]	7252	1			T3	3		T4	1		T17	2
valid_sources[0x5d]	6857	1			T3	1		T5	1		T17	3
valid_sources[0x5e]	8072	1			T2	7		T3	3		T17	15
valid_sources[0x5f]	6829	1			T2	2		T17	8		T18	1
valid_sources[0x60]	7226	1			T3	3		T4	1		T21	1
valid_sources[0x61]	6769	1			T2	2		T4	1		T17	2
valid_sources[0x62]	7562	1			T3	1		T5	1		T19	13
valid_sources[0x63]	7853	1			T3	1		T17	5		T19	3
valid_sources[0x64]	6782	1			T3	3		T4	1		T17	14
valid_sources[0x65]	8696	1			T2	1		T3	2		T5	1
valid_sources[0x66]	7645	1			T3	3		T5	1		T17	13
valid_sources[0x67]	7175	1			T3	8		T5	1		T16	6
valid_sources[0x68]	7795	1			T2	3		T3	1		T17	7
valid_sources[0x69]	7438	1			T4	2		T17	22		T19	11
valid_sources[0x6a]	6723	1			T3	3		T4	4		T21	2
valid_sources[0x6b]	7202	1			T3	1		T21	1		T17	1
valid_sources[0x6c]	6673	1			T3	1		T5	1		T17	13
valid_sources[0x6d]	6672	1			T3	1		T5	1		T21	3
valid_sources[0x6e]	7214	1			T3	2		T21	1		T17	2
valid_sources[0x6f]	6972	1			T3	1		T17	10		T18	2
valid_sources[0x70]	7004	1			T3	1		T17	2		T19	7
valid_sources[0x71]	7037	1			T17	11		T18	1		T19	2
valid_sources[0x72]	7351	1			T3	3		T4	2		T17	9
valid_sources[0x73]	6666	1			T3	3		T4	3		T16	2
valid_sources[0x74]	7168	1			T3	3		T4	1		T21	1
valid_sources[0x75]	6972	1			T3	1		T17	1		T23	1
valid_sources[0x76]	7284	1			T3	4		T4	2		T16	2
valid_sources[0x77]	6938	1			T4	1		T17	9		T23	2
valid_sources[0x78]	6482	1			T23	2		T19	7		T26	4
valid_sources[0x79]	6920	1			T17	7		T18	2		T23	1
valid_sources[0x7a]	6880	1			T3	1		T16	3		T17	3
valid_sources[0x7b]	7997	1			T3	2		T4	3		T21	1
valid_sources[0x7c]	7578	1			T3	2		T16	4		T17	8
valid_sources[0x7d]	7367	1			T3	7		T17	15		T19	4
valid_sources[0x7e]	7029	1			T3	1		T21	1		T16	2
valid_sources[0x7f]	8251	1			T3	1		T17	4		T23	1
valid_sources[0x80]	7086	1			T3	1		T4	3		T16	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26686

1

T1

3

T2

2

T3

6

values[0x0]

all_enables

biggest_size

198773

1

T1

24

T2

12

T3

57

values[0x1]

all_enables

biggest_size

26718

1

T1

2

T2

3

T3

7