Unified Coverage Report :: Module

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	209746397	0	0
DataKnown_AKnownEnable	2147483647	2147483647	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	50400	50400	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	2147483647	209746397
T1	48048	788
T2	38696	670
T3	55832	2075
T4	515032	12049
T5	1006880	18630
T16	243600	4856
T17	1729336	45248
T18	296072	9538
T19	0	709
T21	5601008	96405
T22	43512	638
T23	0	38771
T24	0	62

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	48048	43344
T2	38696	35840
T3	55832	54600
T4	515032	514472
T5	1006880	1003632
T16	243600	241864
T17	1729336	1727544
T18	296072	292656
T21	5601008	5598208
T22	43512	39200

DepthKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	48048	43344
T2	38696	35840
T3	55832	54600
T4	515032	514472
T5	1006880	1003632
T16	243600	241864
T17	1729336	1727544
T18	296072	292656
T21	5601008	5598208
T22	43512	39200

RvalidKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	48048	43344
T2	38696	35840
T3	55832	54600
T4	515032	514472
T5	1006880	1003632
T16	243600	241864
T17	1729336	1727544
T18	296072	292656
T21	5601008	5598208
T22	43512	39200

WreadyKnown_A

Name	Attempts	Real Successes
Total	2147483647	2147483647
T1	48048	43344
T2	38696	35840
T3	55832	54600
T4	515032	514472
T5	1006880	1003632
T16	243600	241864
T17	1729336	1727544
T18	296072	292656
T21	5601008	5598208
T22	43512	39200

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	50400	50400
T1	56	56
T2	56	56
T3	56	56
T4	56	56
T5	56	56
T16	56	56
T17	56	56
T18	56	56
T21	56	56
T22	56	56

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	80172540	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	80172540
T1	858	308
T2	691	259
T3	997	806
T4	9197	4935
T5	17980	8417
T16	4350	2099
T17	30881	12033
T18	5287	4728
T21	100018	41532
T22	777	248

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	50803633	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	50803633
T1	858	160
T2	691	137
T3	997	423
T4	9197	2423
T5	17980	2383
T16	4350	733
T17	30881	10591
T18	5287	2416
T21	100018	12865
T22	777	130

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1079391	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1079391
T1	858	6
T2	691	9
T3	997	16
T4	9197	69
T5	17980	239
T16	4350	58
T17	30881	0
T18	5287	42
T21	100018	633
T22	777	2
T23	0	21

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1241935	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1241935
T1	858	6
T2	691	9
T3	997	16
T4	9197	73
T5	17980	105
T16	4350	21
T17	30881	0
T18	5287	42
T21	100018	30
T22	777	2
T23	0	1939

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1109047	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1109047
T1	858	5
T2	691	3
T3	997	8
T4	9197	74
T5	17980	203
T16	4350	52
T17	30881	1690
T18	5287	47
T21	100018	4007
T22	777	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1932814	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1932814
T1	858	5
T2	691	3
T3	997	8
T4	9197	98
T5	17980	68
T16	4350	24
T17	30881	1281
T18	5287	47
T21	100018	2009
T22	777	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1117024	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1117024
T1	858	5
T2	691	4
T3	997	16
T4	9197	109
T5	17980	196
T16	4350	64
T17	30881	0
T18	5287	48
T21	100018	171
T22	777	5
T23	0	44

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1852553	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1852553
T1	858	5
T2	691	4
T3	997	16
T4	9197	203
T5	17980	75
T16	4350	43
T17	30881	0
T18	5287	48
T21	100018	568
T22	777	5
T23	0	2836

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1041467	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1041467
T1	858	9
T2	691	2
T3	997	16
T4	9197	155
T5	17980	226
T16	4350	42
T17	30881	0
T18	5287	50
T21	100018	793
T22	777	6
T23	0	3

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[3].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1678630	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1678630
T1	858	9
T2	691	2
T3	997	16
T4	9197	132
T5	17980	80
T16	4350	30
T17	30881	0
T18	5287	50
T21	100018	483
T22	777	6
T23	0	472

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1110808	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1110808
T1	858	9
T2	691	6
T3	997	17
T4	9197	70
T5	17980	150
T16	4350	38
T17	30881	0
T18	5287	44
T21	100018	1086
T22	777	8
T23	0	29

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[4].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1705487	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1705487
T1	858	9
T2	691	6
T3	997	17
T4	9197	48
T5	17980	86
T16	4350	4
T17	30881	0
T18	5287	44
T21	100018	572
T22	777	8
T23	0	3006

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1027576	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1027576
T1	858	5
T2	691	5
T3	997	16
T4	9197	117
T5	17980	210
T16	4350	87
T17	30881	0
T18	5287	40
T21	100018	745
T22	777	4
T23	0	26

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[5].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1570004	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1570004
T1	858	5
T2	691	5
T3	997	16
T4	9197	124
T5	17980	90
T16	4350	28
T17	30881	0
T18	5287	40
T21	100018	692
T22	777	4
T23	0	1692

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1100152	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1100152
T1	858	8
T2	691	2
T3	997	17
T4	9197	87
T5	17980	120
T16	4350	40
T17	30881	1846
T18	5287	42
T21	100018	2791
T22	777	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[6].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2069246	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2069246
T1	858	8
T2	691	2
T3	997	17
T4	9197	64
T5	17980	45
T16	4350	28
T17	30881	1343
T18	5287	42
T21	100018	109
T22	777	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1080411	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1080411
T1	858	8
T2	691	2
T3	997	13
T4	9197	77
T5	17980	176
T16	4350	66
T17	30881	0
T18	5287	56
T19	0	237
T21	100018	253
T22	777	0
T23	0	38

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[7].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2115514	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2115514
T1	858	8
T2	691	2
T3	997	13
T4	9197	76
T5	17980	81
T16	4350	29
T17	30881	0
T18	5287	56
T19	0	139
T21	100018	517
T22	777	0
T23	0	2350

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1102778	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1102778
T1	858	6
T2	691	4
T3	997	24
T4	9197	75
T5	17980	225
T16	4350	57
T17	30881	0
T18	5287	40
T21	100018	1322
T22	777	7
T23	0	20

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[8].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1952164	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1952164
T1	858	6
T2	691	4
T3	997	24
T4	9197	105
T5	17980	74
T16	4350	56
T17	30881	0
T18	5287	40
T21	100018	60
T22	777	7
T23	0	1695

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1068009	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1068009
T1	858	6
T2	691	3
T3	997	10
T4	9197	112
T5	17980	207
T16	4350	46
T17	30881	1504
T18	5287	38
T21	100018	505
T22	777	10

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[9].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2002441	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2002441
T1	858	6
T2	691	3
T3	997	10
T4	9197	167
T5	17980	84
T16	4350	23
T17	30881	1236
T18	5287	38
T21	100018	255
T22	777	10

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1048661	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1048661
T1	858	2
T2	691	7
T3	997	17
T4	9197	91
T5	17980	213
T16	4350	23
T17	30881	0
T18	5287	46
T19	0	203
T21	100018	0
T22	777	0
T23	0	23
T24	0	31

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[10].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1631997	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1631997
T1	858	2
T2	691	7
T3	997	17
T4	9197	87
T5	17980	98
T16	4350	6
T17	30881	0
T18	5287	46
T19	0	130
T21	100018	0
T22	777	0
T23	0	1078
T24	0	31

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1073114	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1073114
T1	858	3
T2	691	1
T3	997	13
T4	9197	101
T5	17980	184
T16	4350	39
T17	30881	0
T18	5287	53
T21	100018	1706
T22	777	5
T23	0	31

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[11].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2339583	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2339583
T1	858	3
T2	691	1
T3	997	13
T4	9197	100
T5	17980	56
T16	4350	28
T17	30881	0
T18	5287	53
T21	100018	644
T22	777	5
T23	0	2162

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1053292	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1053292
T1	858	4
T2	691	3
T3	997	18
T4	9197	83
T5	17980	149
T16	4350	16
T17	30881	2368
T18	5287	44
T21	100018	667
T22	777	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[12].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2287907	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2287907
T1	858	4
T2	691	3
T3	997	18
T4	9197	80
T5	17980	79
T16	4350	20
T17	30881	1946
T18	5287	44
T21	100018	657
T22	777	2

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1048978	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1048978
T1	858	4
T2	691	6
T3	997	13
T4	9197	88
T5	17980	223
T16	4350	46
T17	30881	0
T18	5287	45
T21	100018	1710
T22	777	3
T23	0	40

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[13].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1789594	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1789594
T1	858	4
T2	691	6
T3	997	13
T4	9197	92
T5	17980	96
T16	4350	8
T17	30881	0
T18	5287	45
T21	100018	829
T22	777	3
T23	0	3540

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1094075	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1094075
T1	858	6
T2	691	4
T3	997	21
T4	9197	67
T5	17980	168
T16	4350	39
T17	30881	1392
T18	5287	48
T21	100018	1623
T22	777	10

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[14].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1808699	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1808699
T1	858	6
T2	691	4
T3	997	21
T4	9197	50
T5	17980	76
T16	4350	18
T17	30881	1505
T18	5287	48
T21	100018	721
T22	777	10

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1050631	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1050631
T1	858	4
T2	691	5
T3	997	18
T4	9197	87
T5	17980	222
T16	4350	103
T17	30881	0
T18	5287	42
T21	100018	335
T22	777	4
T23	0	18

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[15].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1810212	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1810212
T1	858	4
T2	691	5
T3	997	18
T4	9197	89
T5	17980	105
T16	4350	36
T17	30881	0
T18	5287	42
T21	100018	140
T22	777	4
T23	0	664

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1058073	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1058073
T1	858	5
T2	691	4
T3	997	19
T4	9197	48
T5	17980	250
T16	4350	37
T17	30881	0
T18	5287	38
T21	100018	223
T22	777	4
T23	0	25

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[16].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1755067	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1755067
T1	858	5
T2	691	4
T3	997	19
T4	9197	66
T5	17980	119
T16	4350	22
T17	30881	0
T18	5287	38
T21	100018	153
T22	777	4
T23	0	2070

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1077830	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1077830
T1	858	9
T2	691	7
T3	997	11
T4	9197	41
T5	17980	202
T16	4350	57
T17	30881	0
T18	5287	50
T21	100018	306
T22	777	4
T23	0	26

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[17].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2076158	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2076158
T1	858	9
T2	691	7
T3	997	11
T4	9197	68
T5	17980	78
T16	4350	17
T17	30881	0
T18	5287	50
T21	100018	54
T22	777	4
T23	0	1543

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1052773	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1052773
T1	858	5
T2	691	4
T3	997	14
T4	9197	114
T5	17980	195
T16	4350	77
T17	30881	0
T18	5287	40
T21	100018	3934
T22	777	9
T23	0	27

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[18].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1455158	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1455158
T1	858	5
T2	691	4
T3	997	14
T4	9197	93
T5	17980	136
T16	4350	65
T17	30881	0
T18	5287	40
T21	100018	1788
T22	777	9
T23	0	1938

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1109807	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1109807
T1	858	9
T2	691	6
T3	997	14
T4	9197	56
T5	17980	209
T16	4350	56
T17	30881	0
T18	5287	44
T21	100018	600
T22	777	4
T23	0	19

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[19].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2067807	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2067807
T1	858	9
T2	691	6
T3	997	14
T4	9197	73
T5	17980	103
T16	4350	46
T17	30881	0
T18	5287	44
T21	100018	464
T22	777	4
T23	0	1503

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1094433	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1094433
T1	858	12
T2	691	4
T3	997	17
T4	9197	87
T5	17980	305
T16	4350	20
T17	30881	0
T18	5287	35
T21	100018	459
T22	777	4
T23	0	25

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[20].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1605605	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1605605
T1	858	12
T2	691	4
T3	997	17
T4	9197	83
T5	17980	153
T16	4350	16
T17	30881	0
T18	5287	35
T21	100018	2
T22	777	4
T23	0	1669

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1020861	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1020861
T1	858	6
T2	691	6
T3	997	13
T4	9197	73
T5	17980	143
T16	4350	72
T17	30881	0
T18	5287	43
T21	100018	833
T22	777	5
T23	0	18

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[21].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1787279	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1787279
T1	858	6
T2	691	6
T3	997	13
T4	9197	68
T5	17980	83
T16	4350	67
T17	30881	0
T18	5287	43
T21	100018	520
T22	777	5
T23	0	1312

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1119223	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1119223
T1	858	8
T2	691	9
T3	997	20
T4	9197	73
T5	17980	214
T16	4350	36
T17	30881	1443
T18	5287	30
T21	100018	418
T22	777	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[22].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1808479	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1808479
T1	858	8
T2	691	9
T3	997	20
T4	9197	121
T5	17980	87
T16	4350	39
T17	30881	1299
T18	5287	30
T21	100018	192
T22	777	7

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1041762	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1041762
T1	858	4
T2	691	5
T3	997	15
T4	9197	106
T5	17980	248
T16	4350	30
T17	30881	0
T18	5287	52
T21	100018	515
T22	777	6
T23	0	11

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[23].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1706406	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1706406
T1	858	4
T2	691	5
T3	997	15
T4	9197	101
T5	17980	88
T16	4350	11
T17	30881	0
T18	5287	52
T21	100018	61
T22	777	6
T23	0	2137

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1053448	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1053448
T1	858	6
T2	691	8
T3	997	20
T4	9197	99
T5	17980	172
T16	4350	25
T17	30881	0
T18	5287	43
T21	100018	622
T22	777	3
T23	0	22

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[24].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1782937	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1782937
T1	858	6
T2	691	8
T3	997	20
T4	9197	93
T5	17980	81
T16	4350	3
T17	30881	0
T18	5287	43
T21	100018	414
T22	777	3
T23	0	3533

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1068538	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1068538
T1	858	3
T2	691	12
T3	997	13
T4	9197	43
T5	17980	138
T16	4350	35
T17	30881	1790
T18	5287	49
T21	100018	696
T22	777	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[25].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1933526	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1933526
T1	858	3
T2	691	12
T3	997	13
T4	9197	28
T5	17980	50
T16	4350	20
T17	30881	1981
T18	5287	49
T21	100018	404
T22	777	6

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	1069724	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	1069724
T1	858	3
T2	691	6
T3	997	14
T4	9197	66
T5	17980	260
T16	4350	30
T17	30881	0
T18	5287	48
T21	100018	2191
T22	777	4
T23	0	11

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

Line Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0



43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

Assert Coverage for Instance : tb.dut.u_s1n_28.gen_dfifo[26].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	186351847	2031136	0	0
DataKnown_AKnownEnable	186351847	186221015	0	0
DepthKnown_A	186351847	186221015	0	0
RvalidKnown_A	186351847	186221015	0	0
WreadyKnown_A	186351847	186221015	0	0
gen_passthru_fifo.paramCheckPass	900	900	0	0

DataKnown_A

Name	Attempts	Real Successes
Total	186351847	2031136
T1	858	3
T2	691	6
T3	997	14
T4	9197	41
T5	17980	107
T16	4350	25
T17	30881	0
T18	5287	48
T21	100018	526
T22	777	4
T23	0	1155

DataKnown_AKnownEnable

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

DepthKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

RvalidKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

WreadyKnown_A

Name	Attempts	Real Successes
Total	186351847	186221015
T1	858	774
T2	691	640
T3	997	975
T4	9197	9187
T5	17980	17922
T16	4350	4319
T17	30881	30849
T18	5287	5226
T21	100018	99968
T22	777	700

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes
Total	900	900
T1	1	1
T2	1	1
T3	1	1
T4	1	1
T5	1	1
T16	1	1
T17	1	1
T18	1	1
T21	1	1
T22	1	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children