Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1599598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

252206

1

T1

21

T2

17

T3

75

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	626917	1			T1	54		T2	44		T3	217
values[0x0]	598359	1			T1	61		T2	53		T3	199
values[0x1]	626528	1			T1	63		T2	45		T3	190

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1240300	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

611504

1

T1

47

T2

43

T3

188

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7592	1			T20	2		T21	4		T15	17
valid_sources[0x01]	7098	1			T2	2		T20	2		T21	2
valid_sources[0x02]	7272	1			T1	5		T21	7		T16	3
valid_sources[0x03]	6653	1			T20	2		T21	8		T23	1
valid_sources[0x04]	7575	1			T20	2		T21	2		T23	19
valid_sources[0x05]	6738	1			T3	18		T21	5		T23	28
valid_sources[0x06]	7265	1			T3	15		T4	1		T19	1
valid_sources[0x07]	6683	1			T2	1		T4	2		T20	2
valid_sources[0x08]	7170	1			T19	1		T21	2		T15	2
valid_sources[0x09]	7044	1			T2	2		T20	2		T21	2
valid_sources[0x0a]	7541	1			T3	11		T19	1		T20	1
valid_sources[0x0b]	6841	1			T2	1		T20	5		T21	4
valid_sources[0x0c]	7035	1			T19	2		T20	1		T21	4
valid_sources[0x0d]	7087	1			T4	1		T20	2		T21	2
valid_sources[0x0e]	7490	1			T5	20		T20	1		T21	2
valid_sources[0x0f]	7810	1			T2	1		T20	4		T21	5
valid_sources[0x10]	8017	1			T1	5		T2	1		T4	2
valid_sources[0x11]	6842	1			T19	1		T21	7		T15	2
valid_sources[0x12]	7511	1			T2	2		T19	2		T20	1
valid_sources[0x13]	6736	1			T21	4		T17	7		T18	291
valid_sources[0x14]	7057	1			T4	1		T19	1		T20	5
valid_sources[0x15]	6692	1			T19	1		T20	3		T21	4
valid_sources[0x16]	6308	1			T20	3		T21	3		T15	7
valid_sources[0x17]	7197	1			T2	4		T4	1		T20	1
valid_sources[0x18]	6419	1			T2	1		T20	3		T23	2
valid_sources[0x19]	8026	1			T1	3		T20	1		T21	7
valid_sources[0x1a]	7113	1			T2	5		T4	2		T19	1
valid_sources[0x1b]	6927	1			T2	1		T20	3		T21	6
valid_sources[0x1c]	8019	1			T1	8		T20	2		T21	9
valid_sources[0x1d]	9780	1			T2	2		T19	2		T20	6
valid_sources[0x1e]	7130	1			T3	10		T4	1		T21	14
valid_sources[0x1f]	7132	1			T2	4		T4	1		T23	7
valid_sources[0x20]	7340	1			T19	2		T20	1		T21	4
valid_sources[0x21]	6506	1			T1	3		T21	8		T23	12
valid_sources[0x22]	6922	1			T2	2		T20	2		T21	3
valid_sources[0x23]	6496	1			T20	1		T21	8		T23	12
valid_sources[0x24]	6986	1			T1	2		T2	1		T20	4
valid_sources[0x25]	6984	1			T20	2		T21	3		T23	4
valid_sources[0x26]	7450	1			T3	13		T19	1		T20	2
valid_sources[0x27]	6685	1			T2	1		T3	16		T20	2
valid_sources[0x28]	7078	1			T2	4		T20	3		T21	4
valid_sources[0x29]	7527	1			T1	2		T20	1		T21	7
valid_sources[0x2a]	7640	1			T1	4		T19	1		T20	6
valid_sources[0x2b]	8093	1			T1	1		T2	1		T4	1
valid_sources[0x2c]	6891	1			T20	1		T21	4		T15	6
valid_sources[0x2d]	7538	1			T4	1		T21	7		T15	2
valid_sources[0x2e]	8179	1			T20	1		T21	9		T23	1
valid_sources[0x2f]	7574	1			T3	32		T19	1		T21	6
valid_sources[0x30]	7415	1			T20	1		T21	2		T23	16
valid_sources[0x31]	7848	1			T5	205		T20	1		T21	4
valid_sources[0x32]	8148	1			T4	1		T19	1		T20	4
valid_sources[0x33]	6842	1			T19	1		T20	2		T21	5
valid_sources[0x34]	6234	1			T1	1		T2	4		T4	1
valid_sources[0x35]	9075	1			T20	3		T21	9		T23	2
valid_sources[0x36]	6462	1			T19	1		T20	3		T21	5
valid_sources[0x37]	7486	1			T1	1		T4	1		T19	2
valid_sources[0x38]	6880	1			T19	1		T20	2		T21	3
valid_sources[0x39]	7561	1			T1	4		T2	1		T19	2
valid_sources[0x3a]	7808	1			T2	2		T4	1		T21	8
valid_sources[0x3b]	7338	1			T1	1		T4	2		T19	1
valid_sources[0x3c]	7538	1			T3	7		T20	2		T21	5
valid_sources[0x3d]	6701	1			T3	6		T21	2		T23	2
valid_sources[0x3e]	6979	1			T3	9		T5	53		T21	2
valid_sources[0x3f]	7683	1			T3	16		T4	2		T20	5
valid_sources[0x40]	7583	1			T1	1		T20	1		T21	3
valid_sources[0x41]	7941	1			T2	2		T3	15		T21	1
valid_sources[0x42]	6858	1			T1	7		T2	1		T4	1
valid_sources[0x43]	7120	1			T20	2		T21	5		T23	2
valid_sources[0x44]	6746	1			T2	1		T3	14		T19	1
valid_sources[0x45]	7045	1			T20	3		T21	1		T23	6
valid_sources[0x46]	7744	1			T19	1		T21	2		T23	6
valid_sources[0x47]	6936	1			T2	1		T3	6		T21	1
valid_sources[0x48]	6829	1			T1	1		T2	1		T19	1
valid_sources[0x49]	8011	1			T2	1		T20	2		T21	5
valid_sources[0x4a]	7134	1			T1	2		T19	1		T20	2
valid_sources[0x4b]	6750	1			T4	1		T20	1		T21	4
valid_sources[0x4c]	6380	1			T19	1		T20	1		T21	4
valid_sources[0x4d]	6782	1			T2	3		T21	3		T15	1
valid_sources[0x4e]	7047	1			T1	1		T20	1		T21	2
valid_sources[0x4f]	7710	1			T1	1		T19	1		T21	4
valid_sources[0x50]	6737	1			T2	2		T21	1		T15	3
valid_sources[0x51]	8069	1			T2	2		T20	7		T21	5
valid_sources[0x52]	7558	1			T4	2		T21	2		T23	7
valid_sources[0x53]	7971	1			T3	13		T4	1		T21	1
valid_sources[0x54]	6372	1			T19	1		T20	3		T21	7
valid_sources[0x55]	8798	1			T2	1		T21	1		T23	4
valid_sources[0x56]	7473	1			T4	1		T20	3		T21	2
valid_sources[0x57]	7217	1			T2	1		T3	10		T19	1
valid_sources[0x58]	7700	1			T19	1		T20	1		T21	12
valid_sources[0x59]	7023	1			T2	2		T3	10		T19	1
valid_sources[0x5a]	6987	1			T5	173		T20	3		T21	4
valid_sources[0x5b]	6531	1			T1	3		T20	1		T21	9
valid_sources[0x5c]	6721	1			T2	1		T4	3		T19	1
valid_sources[0x5d]	7310	1			T3	5		T4	1		T21	3
valid_sources[0x5e]	6949	1			T19	2		T20	10		T21	3
valid_sources[0x5f]	6802	1			T1	3		T19	1		T20	1
valid_sources[0x60]	6598	1			T1	3		T4	1		T21	1
valid_sources[0x61]	6765	1			T2	1		T21	4		T23	8
valid_sources[0x62]	7082	1			T1	2		T4	1		T21	5
valid_sources[0x63]	6311	1			T2	1		T3	16		T4	3
valid_sources[0x64]	7091	1			T2	1		T20	4		T23	5
valid_sources[0x65]	7654	1			T2	1		T21	2		T23	7
valid_sources[0x66]	7221	1			T1	1		T2	1		T4	1
valid_sources[0x67]	6645	1			T3	19		T20	2		T21	4
valid_sources[0x68]	7431	1			T1	2		T2	1		T3	12
valid_sources[0x69]	7516	1			T20	8		T21	2		T16	6
valid_sources[0x6a]	6753	1			T21	3		T23	5		T17	4
valid_sources[0x6b]	6604	1			T19	2		T21	12		T23	15
valid_sources[0x6c]	7322	1			T20	5		T21	7		T23	16
valid_sources[0x6d]	6843	1			T2	3		T20	3		T21	3
valid_sources[0x6e]	6487	1			T4	2		T20	4		T21	2
valid_sources[0x6f]	9546	1			T1	3		T2	1		T20	1
valid_sources[0x70]	7014	1			T3	8		T20	15		T21	1
valid_sources[0x71]	8043	1			T1	4		T3	13		T19	1
valid_sources[0x72]	7605	1			T3	7		T4	2		T20	2
valid_sources[0x73]	7029	1			T2	1		T21	6		T23	2
valid_sources[0x74]	7295	1			T23	2		T17	8		T18	38
valid_sources[0x75]	7677	1			T4	1		T21	8		T15	5
valid_sources[0x76]	6885	1			T1	10		T19	2		T21	3
valid_sources[0x77]	6893	1			T4	1		T20	6		T21	2
valid_sources[0x78]	6284	1			T20	14		T21	2		T23	2
valid_sources[0x79]	6723	1			T1	4		T2	1		T4	1
valid_sources[0x7a]	6180	1			T20	1		T21	3		T23	1
valid_sources[0x7b]	7372	1			T3	25		T20	2		T21	5
valid_sources[0x7c]	8168	1			T2	1		T3	8		T20	4
valid_sources[0x7d]	7400	1			T2	2		T19	2		T21	3
valid_sources[0x7e]	7405	1			T3	12		T21	2		T23	9
valid_sources[0x7f]	7759	1			T20	9		T21	4		T17	11
valid_sources[0x80]	6437	1			T1	1		T20	5		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26705

1

T1

4

T2

1

T3

11

values[0x0]

all_enables

biggest_size

198739

1

T1

15

T2

16

T3

60

values[0x1]

all_enables

biggest_size

26762

1

T1

2

T3

4

T5

7