Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1619718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

255302

1

T1

9

T2

14

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	634573	1			T1	30		T2	51		T3	50
values[0x0]	605901	1			T1	32		T2	32		T3	36
values[0x1]	634546	1			T1	39		T2	42		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1255040	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

619980

1

T1

32

T2

38

T3

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7427	1			T22	5		T23	1		T216	2
valid_sources[0x01]	6965	1			T4	2		T5	2		T16	2
valid_sources[0x02]	7376	1			T16	4		T17	6		T22	3
valid_sources[0x03]	9223	1			T19	1		T22	3		T23	2
valid_sources[0x04]	7717	1			T5	4		T16	8		T22	5
valid_sources[0x05]	7847	1			T20	7		T22	2		T23	2
valid_sources[0x06]	7635	1			T5	3		T16	3		T18	2
valid_sources[0x07]	6871	1			T16	1		T19	1		T22	7
valid_sources[0x08]	7031	1			T4	3		T17	1		T22	3
valid_sources[0x09]	6701	1			T2	3		T4	1		T5	1
valid_sources[0x0a]	7799	1			T3	1		T4	1		T5	5
valid_sources[0x0b]	7652	1			T4	1		T16	15		T22	4
valid_sources[0x0c]	7412	1			T4	2		T16	18		T20	7
valid_sources[0x0d]	7057	1			T3	3		T16	4		T17	2
valid_sources[0x0e]	7729	1			T2	4		T3	14		T4	1
valid_sources[0x0f]	8687	1			T4	1		T5	1		T16	3
valid_sources[0x10]	7698	1			T5	1		T22	1		T23	3
valid_sources[0x11]	7117	1			T16	1		T20	8		T22	2
valid_sources[0x12]	7875	1			T4	3		T5	15		T16	18
valid_sources[0x13]	7925	1			T4	3		T5	3		T16	4
valid_sources[0x14]	6815	1			T2	1		T3	5		T5	3
valid_sources[0x15]	6904	1			T4	1		T5	18		T17	6
valid_sources[0x16]	7687	1			T2	1		T5	4		T16	9
valid_sources[0x17]	6873	1			T16	24		T22	5		T23	1
valid_sources[0x18]	7749	1			T4	2		T16	15		T19	4
valid_sources[0x19]	7260	1			T4	3		T12	5		T22	7
valid_sources[0x1a]	7604	1			T5	4		T19	1		T22	1
valid_sources[0x1b]	7758	1			T16	54		T20	7		T22	3
valid_sources[0x1c]	6858	1			T19	1		T23	1		T24	1
valid_sources[0x1d]	6911	1			T2	2		T4	3		T16	6
valid_sources[0x1e]	7036	1			T16	1		T22	4		T23	4
valid_sources[0x1f]	8253	1			T17	1		T22	2		T23	2
valid_sources[0x20]	7346	1			T2	6		T3	6		T4	2
valid_sources[0x21]	6916	1			T4	3		T16	1		T19	1
valid_sources[0x22]	6756	1			T4	1		T5	4		T16	5
valid_sources[0x23]	7353	1			T4	1		T16	9		T19	1
valid_sources[0x24]	7911	1			T16	21		T17	9		T22	4
valid_sources[0x25]	6564	1			T4	6		T5	3		T16	9
valid_sources[0x26]	7110	1			T3	4		T4	1		T16	30
valid_sources[0x27]	7422	1			T4	1		T5	6		T16	41
valid_sources[0x28]	7570	1			T4	2		T5	14		T16	13
valid_sources[0x29]	6487	1			T2	2		T4	2		T22	2
valid_sources[0x2a]	8687	1			T16	26		T17	2		T22	1
valid_sources[0x2b]	7626	1			T2	2		T16	3		T18	9
valid_sources[0x2c]	6910	1			T2	6		T5	11		T16	20
valid_sources[0x2d]	7828	1			T4	1		T16	9		T22	4
valid_sources[0x2e]	6981	1			T16	20		T20	10		T22	2
valid_sources[0x2f]	7194	1			T2	4		T4	1		T16	1
valid_sources[0x30]	8102	1			T5	3		T16	10		T18	4
valid_sources[0x31]	8292	1			T5	3		T16	6		T19	4
valid_sources[0x32]	7945	1			T5	1		T16	11		T22	3
valid_sources[0x33]	6905	1			T4	1		T16	3		T20	12
valid_sources[0x34]	6440	1			T18	3		T22	4		T23	6
valid_sources[0x35]	6603	1			T3	17		T4	2		T5	1
valid_sources[0x36]	7256	1			T5	6		T16	18		T18	11
valid_sources[0x37]	7141	1			T16	22		T19	1		T22	3
valid_sources[0x38]	6926	1			T5	6		T20	33		T15	3
valid_sources[0x39]	6729	1			T16	24		T18	14		T19	1
valid_sources[0x3a]	7718	1			T16	5		T19	1		T12	36
valid_sources[0x3b]	7305	1			T5	18		T16	11		T19	2
valid_sources[0x3c]	7734	1			T16	1		T20	25		T23	3
valid_sources[0x3d]	7031	1			T2	2		T5	1		T16	18
valid_sources[0x3e]	6750	1			T5	7		T16	47		T19	1
valid_sources[0x3f]	6998	1			T4	3		T16	19		T18	1
valid_sources[0x40]	6897	1			T5	1		T16	20		T17	3
valid_sources[0x41]	7552	1			T5	11		T18	2		T20	38
valid_sources[0x42]	6857	1			T5	7		T16	1		T22	5
valid_sources[0x43]	7038	1			T2	2		T16	4		T20	19
valid_sources[0x44]	6416	1			T4	3		T16	36		T20	9
valid_sources[0x45]	6901	1			T16	1		T20	16		T22	5
valid_sources[0x46]	7203	1			T4	1		T5	20		T16	31
valid_sources[0x47]	7179	1			T2	1		T5	6		T16	21
valid_sources[0x48]	7869	1			T3	39		T4	1		T16	1
valid_sources[0x49]	7298	1			T5	1		T16	18		T20	15
valid_sources[0x4a]	7325	1			T2	1		T16	11		T22	2
valid_sources[0x4b]	7084	1			T5	5		T16	19		T20	6
valid_sources[0x4c]	7412	1			T4	1		T5	4		T22	2
valid_sources[0x4d]	6598	1			T2	1		T4	4		T5	6
valid_sources[0x4e]	8151	1			T17	2		T22	1		T23	1
valid_sources[0x4f]	6813	1			T4	1		T16	16		T17	2
valid_sources[0x50]	7699	1			T4	1		T20	10		T22	2
valid_sources[0x51]	6957	1			T5	4		T16	32		T22	1
valid_sources[0x52]	7467	1			T4	1		T5	1		T16	37
valid_sources[0x53]	7340	1			T2	1		T16	1		T19	2
valid_sources[0x54]	7217	1			T4	1		T5	7		T16	6
valid_sources[0x55]	8726	1			T5	5		T16	43		T22	6
valid_sources[0x56]	6462	1			T2	7		T4	2		T16	54
valid_sources[0x57]	6619	1			T5	2		T16	4		T17	1
valid_sources[0x58]	6131	1			T4	1		T16	44		T22	4
valid_sources[0x59]	7100	1			T3	12		T4	2		T5	7
valid_sources[0x5a]	7712	1			T16	14		T19	2		T20	42
valid_sources[0x5b]	7314	1			T4	6		T22	7		T23	1
valid_sources[0x5c]	7124	1			T17	1		T22	3		T14	1
valid_sources[0x5d]	7155	1			T16	1		T20	5		T22	3
valid_sources[0x5e]	6731	1			T4	1		T16	2		T20	13
valid_sources[0x5f]	7381	1			T5	3		T16	10		T19	4
valid_sources[0x60]	8059	1			T4	2		T5	4		T16	45
valid_sources[0x61]	7366	1			T2	1		T4	3		T16	7
valid_sources[0x62]	8006	1			T3	2		T16	2		T22	3
valid_sources[0x63]	7576	1			T4	3		T16	16		T17	1
valid_sources[0x64]	7059	1			T4	4		T5	4		T16	30
valid_sources[0x65]	6823	1			T2	1		T4	2		T20	11
valid_sources[0x66]	7426	1			T3	2		T4	1		T5	3
valid_sources[0x67]	7731	1			T1	51		T16	5		T20	15
valid_sources[0x68]	8096	1			T16	7		T17	1		T22	4
valid_sources[0x69]	7436	1			T4	1		T5	3		T16	11
valid_sources[0x6a]	7828	1			T2	2		T5	3		T16	2
valid_sources[0x6b]	8232	1			T5	10		T16	25		T18	1
valid_sources[0x6c]	7623	1			T4	1		T16	1		T18	6
valid_sources[0x6d]	7334	1			T3	4		T4	2		T16	19
valid_sources[0x6e]	8230	1			T4	2		T16	10		T22	2
valid_sources[0x6f]	7450	1			T22	2		T23	4		T51	1
valid_sources[0x70]	7098	1			T4	2		T5	1		T16	4
valid_sources[0x71]	6798	1			T16	5		T22	2		T23	5
valid_sources[0x72]	7198	1			T1	50		T4	2		T16	15
valid_sources[0x73]	7166	1			T2	2		T3	1		T5	6
valid_sources[0x74]	7952	1			T4	1		T5	5		T16	17
valid_sources[0x75]	7152	1			T4	2		T16	11		T19	2
valid_sources[0x76]	7578	1			T2	5		T5	14		T16	2
valid_sources[0x77]	7890	1			T4	2		T5	5		T16	6
valid_sources[0x78]	6978	1			T16	11		T22	2		T23	4
valid_sources[0x79]	8655	1			T4	1		T16	25		T22	5
valid_sources[0x7a]	7513	1			T4	3		T16	3		T12	5
valid_sources[0x7b]	7151	1			T2	5		T4	2		T16	23
valid_sources[0x7c]	6827	1			T2	2		T4	4		T16	17
valid_sources[0x7d]	6801	1			T16	16		T19	1		T22	1
valid_sources[0x7e]	6909	1			T4	1		T16	23		T19	1
valid_sources[0x7f]	6839	1			T2	1		T4	3		T5	7
valid_sources[0x80]	7230	1			T2	2		T16	10		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26853

1

T1

1

T2

4

T4

6

values[0x0]

all_enables

biggest_size

201391

1

T1

6

T2

10

T3

15

values[0x1]

all_enables

biggest_size

27058

1

T1

2

T3

2

T4

4