Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.main_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1658009	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

262109

1

T1

19

T2

17

T3

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	649142	1			T1	52		T2	39		T3	56
values[0x0]	621382	1			T1	44		T2	40		T3	64
values[0x1]	649594	1			T1	50		T2	39		T3	71

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1285371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

634747

1

T1

47

T2

40

T3

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7412	1			T14	5		T20	35		T21	4
valid_sources[0x01]	6983	1			T1	4		T2	1		T4	2
valid_sources[0x02]	8409	1			T18	15		T14	2		T20	21
valid_sources[0x03]	6608	1			T1	5		T5	1		T14	11
valid_sources[0x04]	7372	1			T3	1		T4	1		T14	4
valid_sources[0x05]	6966	1			T3	1		T14	5		T21	8
valid_sources[0x06]	7949	1			T5	1		T14	5		T13	1
valid_sources[0x07]	6859	1			T3	1		T4	1		T14	6
valid_sources[0x08]	7010	1			T18	14		T14	6		T21	6
valid_sources[0x09]	7986	1			T2	2		T3	1		T5	4
valid_sources[0x0a]	7726	1			T4	1		T14	8		T21	7
valid_sources[0x0b]	8264	1			T2	1		T3	1		T4	2
valid_sources[0x0c]	7020	1			T3	1		T14	7		T17	17
valid_sources[0x0d]	7507	1			T19	1		T14	5		T20	5
valid_sources[0x0e]	7830	1			T1	3		T3	1		T4	3
valid_sources[0x0f]	6819	1			T3	2		T14	6		T17	20
valid_sources[0x10]	8004	1			T18	15		T5	2		T19	1
valid_sources[0x11]	7329	1			T3	2		T14	7		T17	10
valid_sources[0x12]	7421	1			T2	4		T4	1		T14	6
valid_sources[0x13]	8030	1			T1	5		T4	1		T19	1
valid_sources[0x14]	7153	1			T4	2		T14	6		T21	8
valid_sources[0x15]	7559	1			T3	2		T19	1		T14	7
valid_sources[0x16]	7568	1			T14	4		T17	9		T20	10
valid_sources[0x17]	8872	1			T3	2		T4	1		T19	1
valid_sources[0x18]	7486	1			T14	4		T17	15		T20	5
valid_sources[0x19]	6802	1			T2	3		T5	1		T14	6
valid_sources[0x1a]	8616	1			T4	1		T5	2		T19	2
valid_sources[0x1b]	8339	1			T3	1		T4	1		T19	2
valid_sources[0x1c]	8116	1			T1	2		T3	1		T4	2
valid_sources[0x1d]	9380	1			T3	1		T14	8		T20	5
valid_sources[0x1e]	8281	1			T5	3		T14	4		T17	5
valid_sources[0x1f]	7486	1			T4	1		T14	5		T21	12
valid_sources[0x20]	6546	1			T2	2		T3	1		T14	6
valid_sources[0x21]	6751	1			T3	1		T5	1		T14	4
valid_sources[0x22]	7906	1			T1	1		T2	1		T19	1
valid_sources[0x23]	7053	1			T1	1		T14	4		T13	1
valid_sources[0x24]	8799	1			T2	1		T3	2		T5	3
valid_sources[0x25]	7941	1			T1	4		T19	1		T14	5
valid_sources[0x26]	7468	1			T4	1		T5	1		T14	8
valid_sources[0x27]	7732	1			T3	2		T4	1		T19	1
valid_sources[0x28]	7924	1			T2	1		T3	1		T4	2
valid_sources[0x29]	7439	1			T2	2		T3	2		T4	1
valid_sources[0x2a]	7606	1			T3	1		T19	1		T14	1
valid_sources[0x2b]	7993	1			T14	7		T20	18		T21	7
valid_sources[0x2c]	6999	1			T1	1		T2	1		T3	1
valid_sources[0x2d]	6774	1			T2	1		T3	2		T4	1
valid_sources[0x2e]	6961	1			T1	1		T4	1		T14	10
valid_sources[0x2f]	7161	1			T1	1		T5	2		T14	5
valid_sources[0x30]	7316	1			T1	1		T3	1		T5	4
valid_sources[0x31]	7186	1			T1	1		T3	1		T19	1
valid_sources[0x32]	7820	1			T3	1		T4	1		T14	5
valid_sources[0x33]	7619	1			T2	1		T14	8		T13	2
valid_sources[0x34]	7172	1			T1	2		T2	1		T3	1
valid_sources[0x35]	7265	1			T1	2		T2	1		T3	1
valid_sources[0x36]	6738	1			T3	1		T4	1		T5	6
valid_sources[0x37]	7275	1			T2	2		T4	2		T18	20
valid_sources[0x38]	9248	1			T1	1		T19	1		T14	6
valid_sources[0x39]	7739	1			T5	1		T19	1		T14	6
valid_sources[0x3a]	7809	1			T14	5		T20	28		T21	9
valid_sources[0x3b]	7128	1			T14	4		T20	8		T15	51
valid_sources[0x3c]	6842	1			T3	2		T4	1		T14	4
valid_sources[0x3d]	8332	1			T5	1		T19	1		T14	8
valid_sources[0x3e]	9013	1			T2	1		T3	3		T14	6
valid_sources[0x3f]	7129	1			T1	2		T3	4		T4	2
valid_sources[0x40]	7430	1			T1	2		T2	2		T3	1
valid_sources[0x41]	7759	1			T5	1		T19	2		T14	6
valid_sources[0x42]	7201	1			T5	1		T14	6		T17	11
valid_sources[0x43]	7527	1			T2	2		T3	1		T4	1
valid_sources[0x44]	7094	1			T1	3		T19	1		T14	7
valid_sources[0x45]	7205	1			T3	1		T4	1		T19	2
valid_sources[0x46]	6874	1			T3	3		T14	5		T20	10
valid_sources[0x47]	7567	1			T2	1		T3	1		T6	16
valid_sources[0x48]	8000	1			T2	10		T3	2		T4	1
valid_sources[0x49]	7341	1			T19	1		T14	4		T13	1
valid_sources[0x4a]	7127	1			T1	1		T3	2		T19	4
valid_sources[0x4b]	7651	1			T3	1		T4	1		T14	11
valid_sources[0x4c]	6854	1			T1	4		T14	5		T13	1
valid_sources[0x4d]	8730	1			T19	2		T14	5		T17	11
valid_sources[0x4e]	7552	1			T19	2		T14	9		T20	18
valid_sources[0x4f]	7175	1			T19	1		T14	10		T20	12
valid_sources[0x50]	8471	1			T1	2		T4	2		T14	10
valid_sources[0x51]	6559	1			T3	1		T5	1		T19	1
valid_sources[0x52]	7224	1			T4	1		T19	1		T14	7
valid_sources[0x53]	6739	1			T3	2		T14	7		T13	1
valid_sources[0x54]	7695	1			T1	1		T3	1		T4	1
valid_sources[0x55]	7241	1			T1	1		T3	3		T4	1
valid_sources[0x56]	7089	1			T1	1		T3	2		T14	5
valid_sources[0x57]	7773	1			T1	3		T14	9		T13	1
valid_sources[0x58]	8177	1			T1	2		T3	1		T4	1
valid_sources[0x59]	7129	1			T3	1		T4	1		T14	9
valid_sources[0x5a]	7831	1			T3	1		T14	4		T13	1
valid_sources[0x5b]	7313	1			T2	3		T3	1		T5	1
valid_sources[0x5c]	7459	1			T3	1		T14	7		T17	18
valid_sources[0x5d]	6892	1			T19	1		T14	3		T13	1
valid_sources[0x5e]	8290	1			T1	1		T5	4		T14	5
valid_sources[0x5f]	8127	1			T2	3		T4	1		T19	1
valid_sources[0x60]	7039	1			T1	1		T5	1		T19	1
valid_sources[0x61]	7585	1			T4	1		T19	1		T14	9
valid_sources[0x62]	7608	1			T1	2		T14	3		T13	1
valid_sources[0x63]	8541	1			T3	2		T4	1		T19	1
valid_sources[0x64]	7190	1			T2	1		T3	1		T4	1
valid_sources[0x65]	7575	1			T3	2		T5	3		T14	9
valid_sources[0x66]	6962	1			T14	8		T20	15		T21	8
valid_sources[0x67]	8087	1			T4	1		T14	6		T13	1
valid_sources[0x68]	7586	1			T19	1		T14	4		T15	37
valid_sources[0x69]	7192	1			T1	4		T3	1		T4	2
valid_sources[0x6a]	10119	1			T2	5		T14	5		T13	1
valid_sources[0x6b]	8020	1			T4	1		T14	5		T20	18
valid_sources[0x6c]	7129	1			T3	3		T4	1		T14	4
valid_sources[0x6d]	6740	1			T2	4		T3	1		T19	1
valid_sources[0x6e]	7364	1			T14	6		T17	6		T20	26
valid_sources[0x6f]	8137	1			T1	1		T3	1		T4	1
valid_sources[0x70]	8112	1			T3	3		T4	1		T14	5
valid_sources[0x71]	8212	1			T2	2		T3	1		T4	2
valid_sources[0x72]	7049	1			T4	1		T19	1		T14	4
valid_sources[0x73]	7286	1			T19	1		T14	4		T21	8
valid_sources[0x74]	7553	1			T1	1		T3	1		T14	1
valid_sources[0x75]	7365	1			T1	7		T2	1		T3	2
valid_sources[0x76]	9198	1			T4	2		T19	1		T14	13
valid_sources[0x77]	6971	1			T3	1		T14	5		T20	13
valid_sources[0x78]	6961	1			T3	2		T4	1		T5	2
valid_sources[0x79]	6823	1			T14	9		T21	7		T23	10
valid_sources[0x7a]	7457	1			T4	1		T5	1		T14	8
valid_sources[0x7b]	7773	1			T1	2		T2	1		T4	1
valid_sources[0x7c]	8560	1			T2	1		T3	3		T6	69
valid_sources[0x7d]	7026	1			T3	1		T4	1		T19	1
valid_sources[0x7e]	7795	1			T4	2		T19	1		T14	7
valid_sources[0x7f]	9197	1			T4	1		T5	1		T14	7
valid_sources[0x80]	7642	1			T14	10		T17	13		T20	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27858

1

T1

1

T2

2

T3

3

values[0x0]

all_enables

biggest_size

206451

1

T1

13

T2

15

T3

20

values[0x1]

all_enables

biggest_size

27800

1

T1

5

T6

4

T4

2