SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
99.24 | 100.00 | 95.42 | 100.00 | 100.00 | 100.00 | 100.00 |
T781 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.629109046 | Feb 08 08:51:10 AM UTC 25 | Feb 08 08:51:20 AM UTC 25 | 511976170 ps | ||
T782 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1685836122 | Feb 08 08:48:08 AM UTC 25 | Feb 08 08:51:21 AM UTC 25 | 29420300584 ps | ||
T783 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.85592239 | Feb 08 08:51:15 AM UTC 25 | Feb 08 08:51:21 AM UTC 25 | 133069311 ps | ||
T34 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3528461306 | Feb 08 08:51:09 AM UTC 25 | Feb 08 08:51:21 AM UTC 25 | 2735015210 ps | ||
T784 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2007908029 | Feb 08 08:50:52 AM UTC 25 | Feb 08 08:51:21 AM UTC 25 | 443315488 ps | ||
T785 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.520927130 | Feb 08 08:49:46 AM UTC 25 | Feb 08 08:51:23 AM UTC 25 | 10426564493 ps | ||
T786 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2892653604 | Feb 08 08:51:20 AM UTC 25 | Feb 08 08:51:23 AM UTC 25 | 184047917 ps | ||
T787 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3542487383 | Feb 08 08:51:20 AM UTC 25 | Feb 08 08:51:23 AM UTC 25 | 10262074 ps | ||
T788 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.3346442285 | Feb 08 08:50:58 AM UTC 25 | Feb 08 08:51:25 AM UTC 25 | 1115807096 ps | ||
T789 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.56043150 | Feb 08 08:51:01 AM UTC 25 | Feb 08 08:51:25 AM UTC 25 | 1983321349 ps | ||
T790 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3670608786 | Feb 08 08:49:37 AM UTC 25 | Feb 08 08:51:25 AM UTC 25 | 738806818 ps | ||
T791 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2437707742 | Feb 08 08:51:10 AM UTC 25 | Feb 08 08:51:26 AM UTC 25 | 1328220869 ps | ||
T792 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4193476921 | Feb 08 08:51:17 AM UTC 25 | Feb 08 08:51:26 AM UTC 25 | 87198426 ps | ||
T793 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1065048212 | Feb 08 08:51:22 AM UTC 25 | Feb 08 08:51:27 AM UTC 25 | 437453821 ps | ||
T794 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2093692314 | Feb 08 08:51:22 AM UTC 25 | Feb 08 08:51:28 AM UTC 25 | 28818187 ps | ||
T795 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2200785447 | Feb 08 08:51:17 AM UTC 25 | Feb 08 08:51:29 AM UTC 25 | 2184106905 ps | ||
T113 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1308091532 | Feb 08 08:49:25 AM UTC 25 | Feb 08 08:51:29 AM UTC 25 | 65799191453 ps | ||
T796 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1952773822 | Feb 08 08:51:22 AM UTC 25 | Feb 08 08:51:30 AM UTC 25 | 727694605 ps | ||
T797 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3536654318 | Feb 08 08:51:25 AM UTC 25 | Feb 08 08:51:30 AM UTC 25 | 119007515 ps | ||
T798 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.712167308 | Feb 08 08:48:44 AM UTC 25 | Feb 08 08:51:31 AM UTC 25 | 44290656138 ps | ||
T799 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.490450352 | Feb 08 08:50:52 AM UTC 25 | Feb 08 08:51:31 AM UTC 25 | 2851843648 ps | ||
T800 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2855263030 | Feb 08 08:51:27 AM UTC 25 | Feb 08 08:51:32 AM UTC 25 | 60004502 ps | ||
T801 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2427704136 | Feb 08 08:51:25 AM UTC 25 | Feb 08 08:51:32 AM UTC 25 | 55262219 ps | ||
T802 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.331097081 | Feb 08 08:51:20 AM UTC 25 | Feb 08 08:51:33 AM UTC 25 | 1428651851 ps | ||
T803 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3928273893 | Feb 08 08:51:29 AM UTC 25 | Feb 08 08:51:33 AM UTC 25 | 103577058 ps | ||
T804 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1668267057 | Feb 08 08:51:30 AM UTC 25 | Feb 08 08:51:34 AM UTC 25 | 11071760 ps | ||
T805 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.491512412 | Feb 08 08:51:23 AM UTC 25 | Feb 08 08:51:36 AM UTC 25 | 973245748 ps | ||
T222 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.4161410989 | Feb 08 08:51:27 AM UTC 25 | Feb 08 08:51:38 AM UTC 25 | 479776020 ps | ||
T806 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2098624876 | Feb 08 08:51:33 AM UTC 25 | Feb 08 08:51:39 AM UTC 25 | 24368026 ps | ||
T807 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.3227620102 | Feb 08 08:51:35 AM UTC 25 | Feb 08 08:51:39 AM UTC 25 | 25085998 ps | ||
T808 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2674965251 | Feb 08 08:51:18 AM UTC 25 | Feb 08 08:51:40 AM UTC 25 | 316027382 ps | ||
T809 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1086955331 | Feb 08 08:51:32 AM UTC 25 | Feb 08 08:51:40 AM UTC 25 | 198935898 ps | ||
T114 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.819344140 | Feb 08 08:49:43 AM UTC 25 | Feb 08 08:51:40 AM UTC 25 | 34666612872 ps | ||
T810 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.510879132 | Feb 08 08:51:34 AM UTC 25 | Feb 08 08:51:41 AM UTC 25 | 485613947 ps | ||
T115 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.159227906 | Feb 08 08:44:07 AM UTC 25 | Feb 08 08:51:42 AM UTC 25 | 60052448913 ps | ||
T256 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2543860618 | Feb 08 08:47:45 AM UTC 25 | Feb 08 08:51:42 AM UTC 25 | 180242218186 ps | ||
T267 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1652006509 | Feb 08 08:48:45 AM UTC 25 | Feb 08 08:51:43 AM UTC 25 | 19564849703 ps | ||
T811 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2891312589 | Feb 08 08:51:36 AM UTC 25 | Feb 08 08:51:43 AM UTC 25 | 321340240 ps | ||
T812 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2169928848 | Feb 08 08:51:40 AM UTC 25 | Feb 08 08:51:44 AM UTC 25 | 18422805 ps | ||
T813 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2597467829 | Feb 08 08:51:06 AM UTC 25 | Feb 08 08:51:44 AM UTC 25 | 287060976 ps | ||
T268 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.192019905 | Feb 08 08:50:23 AM UTC 25 | Feb 08 08:51:45 AM UTC 25 | 12080995731 ps | ||
T814 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2435526313 | Feb 08 08:51:31 AM UTC 25 | Feb 08 08:51:46 AM UTC 25 | 6228042799 ps | ||
T815 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.882714405 | Feb 08 08:51:43 AM UTC 25 | Feb 08 08:51:46 AM UTC 25 | 10353211 ps | ||
T816 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.387587857 | Feb 08 08:51:43 AM UTC 25 | Feb 08 08:51:46 AM UTC 25 | 128851821 ps | ||
T817 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1184741986 | Feb 08 08:51:35 AM UTC 25 | Feb 08 08:51:46 AM UTC 25 | 1176477364 ps | ||
T818 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3469637710 | Feb 08 08:51:45 AM UTC 25 | Feb 08 08:51:51 AM UTC 25 | 190290652 ps | ||
T819 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.760401938 | Feb 08 08:51:31 AM UTC 25 | Feb 08 08:51:52 AM UTC 25 | 3607502634 ps | ||
T820 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.422296762 | Feb 08 08:50:27 AM UTC 25 | Feb 08 08:51:54 AM UTC 25 | 712202988 ps | ||
T821 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.114372270 | Feb 08 08:51:45 AM UTC 25 | Feb 08 08:51:54 AM UTC 25 | 181594225 ps | ||
T822 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.530894284 | Feb 08 08:50:52 AM UTC 25 | Feb 08 08:51:56 AM UTC 25 | 624692310 ps | ||
T823 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1432392491 | Feb 08 08:51:48 AM UTC 25 | Feb 08 08:51:57 AM UTC 25 | 329306492 ps | ||
T824 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1573353587 | Feb 08 08:51:48 AM UTC 25 | Feb 08 08:51:57 AM UTC 25 | 260497142 ps | ||
T825 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3744379567 | Feb 08 08:50:34 AM UTC 25 | Feb 08 08:51:58 AM UTC 25 | 13967118089 ps | ||
T826 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1371868708 | Feb 08 08:51:27 AM UTC 25 | Feb 08 08:51:59 AM UTC 25 | 7795110060 ps | ||
T827 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.795177831 | Feb 08 08:51:52 AM UTC 25 | Feb 08 08:52:01 AM UTC 25 | 369230918 ps | ||
T828 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1253744554 | Feb 08 08:50:43 AM UTC 25 | Feb 08 08:52:01 AM UTC 25 | 130496173528 ps | ||
T829 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.24906034 | Feb 08 08:51:58 AM UTC 25 | Feb 08 08:52:02 AM UTC 25 | 56744202 ps | ||
T830 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1266860352 | Feb 08 08:51:43 AM UTC 25 | Feb 08 08:52:02 AM UTC 25 | 3258229652 ps | ||
T831 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1180730061 | Feb 08 08:51:41 AM UTC 25 | Feb 08 08:52:03 AM UTC 25 | 272563110 ps | ||
T832 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2255497205 | Feb 08 08:50:58 AM UTC 25 | Feb 08 08:52:03 AM UTC 25 | 19221630238 ps | ||
T833 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.960489946 | Feb 08 08:51:59 AM UTC 25 | Feb 08 08:52:03 AM UTC 25 | 10109861 ps | ||
T116 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2260641196 | Feb 08 08:51:48 AM UTC 25 | Feb 08 08:52:03 AM UTC 25 | 704451667 ps | ||
T834 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.820429525 | Feb 08 08:51:55 AM UTC 25 | Feb 08 08:52:06 AM UTC 25 | 19921680 ps | ||
T835 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3067119160 | Feb 08 08:51:45 AM UTC 25 | Feb 08 08:52:06 AM UTC 25 | 2768018108 ps | ||
T836 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.643148616 | Feb 08 08:51:48 AM UTC 25 | Feb 08 08:52:06 AM UTC 25 | 3744501321 ps | ||
T837 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1292742607 | Feb 08 08:50:14 AM UTC 25 | Feb 08 08:52:08 AM UTC 25 | 14437369841 ps | ||
T838 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.665968569 | Feb 08 08:52:02 AM UTC 25 | Feb 08 08:52:08 AM UTC 25 | 34251405 ps | ||
T839 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.464348339 | Feb 08 08:51:17 AM UTC 25 | Feb 08 08:52:08 AM UTC 25 | 4058571849 ps | ||
T840 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.398776515 | Feb 08 08:49:46 AM UTC 25 | Feb 08 08:52:09 AM UTC 25 | 5735669952 ps | ||
T841 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2502326929 | Feb 08 08:51:55 AM UTC 25 | Feb 08 08:52:09 AM UTC 25 | 146807860 ps | ||
T117 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.341795756 | Feb 08 08:49:33 AM UTC 25 | Feb 08 08:52:10 AM UTC 25 | 47893806960 ps | ||
T842 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.546802501 | Feb 08 08:52:05 AM UTC 25 | Feb 08 08:52:12 AM UTC 25 | 48467767 ps | ||
T269 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1876516369 | Feb 08 08:47:37 AM UTC 25 | Feb 08 08:52:12 AM UTC 25 | 241036724629 ps | ||
T843 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1893838112 | Feb 08 08:52:03 AM UTC 25 | Feb 08 08:52:12 AM UTC 25 | 144798431 ps | ||
T844 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1659548446 | Feb 08 08:51:45 AM UTC 25 | Feb 08 08:52:13 AM UTC 25 | 2757497392 ps | ||
T845 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2706195800 | Feb 08 08:52:06 AM UTC 25 | Feb 08 08:52:13 AM UTC 25 | 41034421 ps | ||
T35 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3168589442 | Feb 08 08:52:07 AM UTC 25 | Feb 08 08:52:15 AM UTC 25 | 362104044 ps | ||
T846 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3985087283 | Feb 08 08:51:27 AM UTC 25 | Feb 08 08:52:15 AM UTC 25 | 15023346240 ps | ||
T847 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.3880170468 | Feb 08 08:52:12 AM UTC 25 | Feb 08 08:52:16 AM UTC 25 | 9232481 ps | ||
T848 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3933543616 | Feb 08 08:52:12 AM UTC 25 | Feb 08 08:52:16 AM UTC 25 | 9606885 ps | ||
T849 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.4245887473 | Feb 08 08:52:07 AM UTC 25 | Feb 08 08:52:16 AM UTC 25 | 480070459 ps | ||
T850 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.885310039 | Feb 08 08:52:00 AM UTC 25 | Feb 08 08:52:16 AM UTC 25 | 3875342912 ps | ||
T851 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.4225565916 | Feb 08 08:51:59 AM UTC 25 | Feb 08 08:52:18 AM UTC 25 | 5075799358 ps | ||
T852 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2903737202 | Feb 08 08:51:53 AM UTC 25 | Feb 08 08:52:20 AM UTC 25 | 247441177 ps | ||
T853 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3310626799 | Feb 08 08:50:38 AM UTC 25 | Feb 08 08:52:20 AM UTC 25 | 760739026 ps | ||
T118 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.290990370 | Feb 08 08:49:13 AM UTC 25 | Feb 08 08:52:23 AM UTC 25 | 25535791453 ps | ||
T854 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2388803541 | Feb 08 08:51:40 AM UTC 25 | Feb 08 08:52:23 AM UTC 25 | 2797802191 ps | ||
T855 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1580422132 | Feb 08 08:52:13 AM UTC 25 | Feb 08 08:52:24 AM UTC 25 | 66855579 ps | ||
T856 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1703675207 | Feb 08 08:52:18 AM UTC 25 | Feb 08 08:52:24 AM UTC 25 | 81919359 ps | ||
T857 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1406004206 | Feb 08 08:52:18 AM UTC 25 | Feb 08 08:52:25 AM UTC 25 | 202523215 ps | ||
T858 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2417274280 | Feb 08 08:51:22 AM UTC 25 | Feb 08 08:52:25 AM UTC 25 | 27642895936 ps | ||
T859 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1883969293 | Feb 08 08:52:17 AM UTC 25 | Feb 08 08:52:25 AM UTC 25 | 401533638 ps | ||
T860 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3271145322 | Feb 08 08:52:13 AM UTC 25 | Feb 08 08:52:25 AM UTC 25 | 328305775 ps | ||
T261 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1039489808 | Feb 08 08:45:31 AM UTC 25 | Feb 08 08:52:26 AM UTC 25 | 46458532261 ps | ||
T861 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3019520565 | Feb 08 08:52:13 AM UTC 25 | Feb 08 08:52:26 AM UTC 25 | 1737128731 ps | ||
T862 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4092554039 | Feb 08 08:52:19 AM UTC 25 | Feb 08 08:52:27 AM UTC 25 | 379666785 ps | ||
T10 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1058386541 | Feb 08 08:51:18 AM UTC 25 | Feb 08 08:52:27 AM UTC 25 | 9173105708 ps | ||
T863 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2059392483 | Feb 08 08:52:12 AM UTC 25 | Feb 08 08:52:27 AM UTC 25 | 4156698544 ps | ||
T864 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3362634852 | Feb 08 08:50:58 AM UTC 25 | Feb 08 08:52:27 AM UTC 25 | 38626849861 ps | ||
T865 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3309921712 | Feb 08 08:52:05 AM UTC 25 | Feb 08 08:52:29 AM UTC 25 | 881164808 ps | ||
T866 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.4037111909 | Feb 08 08:52:18 AM UTC 25 | Feb 08 08:52:30 AM UTC 25 | 402917371 ps | ||
T867 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1314334649 | Feb 08 08:52:15 AM UTC 25 | Feb 08 08:52:31 AM UTC 25 | 1747297901 ps | ||
T868 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.909873314 | Feb 08 08:52:21 AM UTC 25 | Feb 08 08:52:35 AM UTC 25 | 315615675 ps | ||
T869 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3050486216 | Feb 08 08:52:09 AM UTC 25 | Feb 08 08:52:36 AM UTC 25 | 193801123 ps | ||
T224 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.16713253 | Feb 08 08:50:32 AM UTC 25 | Feb 08 08:52:46 AM UTC 25 | 31664531186 ps | ||
T870 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.2675349428 | Feb 08 08:51:33 AM UTC 25 | Feb 08 08:52:47 AM UTC 25 | 41607601245 ps | ||
T871 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1877567003 | Feb 08 08:50:38 AM UTC 25 | Feb 08 08:52:50 AM UTC 25 | 4674771886 ps | ||
T264 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3824239429 | Feb 08 08:46:50 AM UTC 25 | Feb 08 08:52:54 AM UTC 25 | 52672183422 ps | ||
T167 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3480139526 | Feb 08 08:51:02 AM UTC 25 | Feb 08 08:52:57 AM UTC 25 | 4462284121 ps | ||
T872 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.784549886 | Feb 08 08:52:09 AM UTC 25 | Feb 08 08:52:58 AM UTC 25 | 3064813820 ps | ||
T36 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3914650077 | Feb 08 08:51:27 AM UTC 25 | Feb 08 08:52:59 AM UTC 25 | 5693687554 ps | ||
T152 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4245057672 | Feb 08 08:50:20 AM UTC 25 | Feb 08 08:53:00 AM UTC 25 | 30951807590 ps | ||
T7 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.687184715 | Feb 08 08:51:41 AM UTC 25 | Feb 08 08:53:01 AM UTC 25 | 2265999358 ps | ||
T873 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1831790606 | Feb 08 08:51:34 AM UTC 25 | Feb 08 08:53:01 AM UTC 25 | 24391428080 ps | ||
T874 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2928076213 | Feb 08 08:52:09 AM UTC 25 | Feb 08 08:53:07 AM UTC 25 | 548885414 ps | ||
T875 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1620145974 | Feb 08 08:52:19 AM UTC 25 | Feb 08 08:53:08 AM UTC 25 | 672630089 ps | ||
T876 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1383334098 | Feb 08 08:51:12 AM UTC 25 | Feb 08 08:53:09 AM UTC 25 | 37299579763 ps | ||
T131 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4036960352 | Feb 08 08:47:57 AM UTC 25 | Feb 08 08:53:14 AM UTC 25 | 222577199334 ps | ||
T11 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.50884342 | Feb 08 08:49:35 AM UTC 25 | Feb 08 08:53:14 AM UTC 25 | 1031797601 ps | ||
T132 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.4098749218 | Feb 08 08:52:07 AM UTC 25 | Feb 08 08:53:14 AM UTC 25 | 12308341326 ps | ||
T210 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3204684865 | Feb 08 08:51:22 AM UTC 25 | Feb 08 08:53:15 AM UTC 25 | 24917096407 ps | ||
T877 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.557228505 | Feb 08 08:51:58 AM UTC 25 | Feb 08 08:53:24 AM UTC 25 | 2664654468 ps | ||
T878 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1329995813 | Feb 08 08:50:26 AM UTC 25 | Feb 08 08:53:25 AM UTC 25 | 1932659729 ps | ||
T879 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.592859059 | Feb 08 08:51:12 AM UTC 25 | Feb 08 08:53:28 AM UTC 25 | 21038273584 ps | ||
T880 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3029284283 | Feb 08 08:51:18 AM UTC 25 | Feb 08 08:53:35 AM UTC 25 | 6356819068 ps | ||
T881 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1003293765 | Feb 08 08:51:41 AM UTC 25 | Feb 08 08:53:37 AM UTC 25 | 656321050 ps | ||
T882 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3372302198 | Feb 08 08:51:48 AM UTC 25 | Feb 08 08:53:41 AM UTC 25 | 50442768504 ps | ||
T883 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.594426496 | Feb 08 08:52:17 AM UTC 25 | Feb 08 08:53:42 AM UTC 25 | 12691569636 ps | ||
T884 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3501689263 | Feb 08 08:49:35 AM UTC 25 | Feb 08 08:53:44 AM UTC 25 | 38035203063 ps | ||
T885 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1422739915 | Feb 08 08:50:44 AM UTC 25 | Feb 08 08:53:53 AM UTC 25 | 20906651228 ps | ||
T886 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.459856499 | Feb 08 08:52:25 AM UTC 25 | Feb 08 08:54:05 AM UTC 25 | 752586134 ps | ||
T887 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3397271519 | Feb 08 08:52:05 AM UTC 25 | Feb 08 08:54:06 AM UTC 25 | 14253194374 ps | ||
T888 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4248642899 | Feb 08 08:51:34 AM UTC 25 | Feb 08 08:54:23 AM UTC 25 | 17655847199 ps | ||
T889 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3293878519 | Feb 08 08:52:15 AM UTC 25 | Feb 08 08:54:24 AM UTC 25 | 36676956904 ps | ||
T890 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3437195388 | Feb 08 08:51:07 AM UTC 25 | Feb 08 08:54:37 AM UTC 25 | 16285601905 ps | ||
T891 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.755119942 | Feb 08 08:52:21 AM UTC 25 | Feb 08 08:54:41 AM UTC 25 | 574584652 ps | ||
T282 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3617492274 | Feb 08 08:48:20 AM UTC 25 | Feb 08 08:54:50 AM UTC 25 | 59841472819 ps | ||
T133 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1903665134 | Feb 08 08:51:15 AM UTC 25 | Feb 08 08:54:52 AM UTC 25 | 153305730060 ps | ||
T892 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1752849060 | Feb 08 08:51:45 AM UTC 25 | Feb 08 08:54:59 AM UTC 25 | 78931764252 ps | ||
T893 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3074832375 | Feb 08 08:48:34 AM UTC 25 | Feb 08 08:55:19 AM UTC 25 | 88489401557 ps | ||
T119 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2043092815 | Feb 08 08:50:58 AM UTC 25 | Feb 08 08:55:21 AM UTC 25 | 40284928644 ps | ||
T894 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1300275359 | Feb 08 08:51:29 AM UTC 25 | Feb 08 08:55:48 AM UTC 25 | 1369500362 ps | ||
T895 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1243814011 | Feb 08 08:49:00 AM UTC 25 | Feb 08 08:55:52 AM UTC 25 | 48034443859 ps | ||
T896 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2430008703 | Feb 08 08:50:34 AM UTC 25 | Feb 08 08:55:59 AM UTC 25 | 168425835324 ps | ||
T240 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3792727644 | Feb 08 08:50:05 AM UTC 25 | Feb 08 08:56:02 AM UTC 25 | 41803704099 ps | ||
T897 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3447938586 | Feb 08 08:51:25 AM UTC 25 | Feb 08 08:56:07 AM UTC 25 | 96810347271 ps | ||
T898 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1539092083 | Feb 08 08:52:03 AM UTC 25 | Feb 08 08:56:10 AM UTC 25 | 53909528225 ps | ||
T899 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4006487376 | Feb 08 08:52:03 AM UTC 25 | Feb 08 08:56:10 AM UTC 25 | 75971030680 ps | ||
T900 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.4069976296 | Feb 08 08:49:54 AM UTC 25 | Feb 08 08:56:20 AM UTC 25 | 72785308436 ps | ||
T142 | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1286536423 | Feb 08 08:50:44 AM UTC 25 | Feb 08 08:58:55 AM UTC 25 | 213811362683 ps |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.2488732088 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 236996168 ps |
CPU time | 5.72 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:36 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488732088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2488732088 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.159227906 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 60052448913 ps |
CPU time | 448.32 seconds |
Started | Feb 08 08:44:07 AM UTC 25 |
Finished | Feb 08 08:51:42 AM UTC 25 |
Peak memory | 218128 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159227906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.159227906 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.3824239429 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 52672183422 ps |
CPU time | 359.08 seconds |
Started | Feb 08 08:46:50 AM UTC 25 |
Finished | Feb 08 08:52:54 AM UTC 25 |
Peak memory | 220116 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824239429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.3824239429 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.812444690 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 577453150 ps |
CPU time | 8.45 seconds |
Started | Feb 08 08:42:53 AM UTC 25 |
Finished | Feb 08 08:43:05 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812444690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.812444690 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1057527998 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 73130509588 ps |
CPU time | 326.82 seconds |
Started | Feb 08 08:44:41 AM UTC 25 |
Finished | Feb 08 08:50:14 AM UTC 25 |
Peak memory | 216172 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057527998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1057527998 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.2119691235 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 16559800610 ps |
CPU time | 132.25 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:44:47 AM UTC 25 |
Peak memory | 212376 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119691235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.2119691235 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.1876516369 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 241036724629 ps |
CPU time | 270.7 seconds |
Started | Feb 08 08:47:37 AM UTC 25 |
Finished | Feb 08 08:52:12 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876516369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.1876516369 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.1837395317 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 3268282083 ps |
CPU time | 65.06 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:43:46 AM UTC 25 |
Peak memory | 214424 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837395317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1837395317 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.651000805 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 110643295 ps |
CPU time | 16.36 seconds |
Started | Feb 08 08:42:56 AM UTC 25 |
Finished | Feb 08 08:43:15 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651000805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.651000805 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.3107911452 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 4480687812 ps |
CPU time | 22.34 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:52 AM UTC 25 |
Peak memory | 212552 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107911452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.3107911452 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.3196003166 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 42497737 ps |
CPU time | 5.52 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:36 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196003166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3196003166 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.2692585815 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 18467225223 ps |
CPU time | 193.11 seconds |
Started | Feb 08 08:44:21 AM UTC 25 |
Finished | Feb 08 08:47:37 AM UTC 25 |
Peak memory | 214604 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692585815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.2692585815 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.3420363657 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 2825237841 ps |
CPU time | 12.53 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:45 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420363657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3420363657 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.446675411 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 1813852234 ps |
CPU time | 10.04 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:43 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446675411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.446675411 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.284492892 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 2654068586 ps |
CPU time | 66.15 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:43:40 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284492892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.284492892 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.3901390668 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 21638976318 ps |
CPU time | 172.64 seconds |
Started | Feb 08 08:47:16 AM UTC 25 |
Finished | Feb 08 08:50:12 AM UTC 25 |
Peak memory | 214196 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901390668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.3901390668 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.2469751985 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 1050446273 ps |
CPU time | 87.2 seconds |
Started | Feb 08 08:49:06 AM UTC 25 |
Finished | Feb 08 08:50:36 AM UTC 25 |
Peak memory | 216584 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469751985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.2469751985 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.1058386541 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 9173105708 ps |
CPU time | 66.33 seconds |
Started | Feb 08 08:51:18 AM UTC 25 |
Finished | Feb 08 08:52:27 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058386541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.1058386541 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.687184715 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 2265999358 ps |
CPU time | 77.02 seconds |
Started | Feb 08 08:51:41 AM UTC 25 |
Finished | Feb 08 08:53:01 AM UTC 25 |
Peak memory | 214420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687184715 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.687184715 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.50884342 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 1031797601 ps |
CPU time | 214.78 seconds |
Started | Feb 08 08:49:35 AM UTC 25 |
Finished | Feb 08 08:53:14 AM UTC 25 |
Peak memory | 218380 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50884342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.50884342 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.1776546601 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 6195344025 ps |
CPU time | 59.51 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:43:33 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776546601 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1776546601 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.3654043334 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 11034868121 ps |
CPU time | 145.82 seconds |
Started | Feb 08 08:42:30 AM UTC 25 |
Finished | Feb 08 08:45:00 AM UTC 25 |
Peak memory | 216460 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654043334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.3654043334 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.1286536423 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 213811362683 ps |
CPU time | 484.64 seconds |
Started | Feb 08 08:50:44 AM UTC 25 |
Finished | Feb 08 08:58:55 AM UTC 25 |
Peak memory | 218128 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286536423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.1286536423 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.3550894077 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 592636827 ps |
CPU time | 77.03 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:43:58 AM UTC 25 |
Peak memory | 216528 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550894077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.3550894077 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1082888110 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1186834153 ps |
CPU time | 13.25 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:43 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082888110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1082888110 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.1711034000 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1494595997 ps |
CPU time | 107.28 seconds |
Started | Feb 08 08:44:47 AM UTC 25 |
Finished | Feb 08 08:46:37 AM UTC 25 |
Peak memory | 216404 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711034000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.1711034000 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.3898974779 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1338377236 ps |
CPU time | 27.89 seconds |
Started | Feb 08 08:44:20 AM UTC 25 |
Finished | Feb 08 08:44:50 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898974779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3898974779 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2064278127 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 1209358246 ps |
CPU time | 185.16 seconds |
Started | Feb 08 08:45:11 AM UTC 25 |
Finished | Feb 08 08:48:20 AM UTC 25 |
Peak memory | 216396 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064278127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2064278127 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.53336796 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 161380352 ps |
CPU time | 23.5 seconds |
Started | Feb 08 08:42:56 AM UTC 25 |
Finished | Feb 08 08:43:22 AM UTC 25 |
Peak memory | 214344 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53336796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.53336796 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.3072857547 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 51061658 ps |
CPU time | 6.24 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:36 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072857547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.3072857547 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.2787683369 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 29575020709 ps |
CPU time | 169.01 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:45:24 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787683369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2787683369 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.3459450738 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 245293525 ps |
CPU time | 86.02 seconds |
Started | Feb 08 08:45:35 AM UTC 25 |
Finished | Feb 08 08:47:04 AM UTC 25 |
Peak memory | 216724 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459450738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.3459450738 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.2340284834 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 20454746683 ps |
CPU time | 194.61 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:45:46 AM UTC 25 |
Peak memory | 218132 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340284834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.2340284834 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.1146305754 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 9235042 ps |
CPU time | 1.34 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:31 AM UTC 25 |
Peak memory | 211848 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146305754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.1146305754 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.1110595120 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 22163005576 ps |
CPU time | 77.88 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:43:48 AM UTC 25 |
Peak memory | 214144 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110595120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1110595120 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.1418733252 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 37507194944 ps |
CPU time | 174.48 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:45:26 AM UTC 25 |
Peak memory | 216072 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418733252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1418733252 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.1326942980 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 2001165163 ps |
CPU time | 10.97 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:41 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326942980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1326942980 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.1862742974 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 36701501 ps |
CPU time | 1.61 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:31 AM UTC 25 |
Peak memory | 211324 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862742974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1862742974 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.1358997630 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 3146932723 ps |
CPU time | 17.91 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:48 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358997630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.1358997630 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3158294543 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 2043372665 ps |
CPU time | 10.15 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:40 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158294543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3158294543 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.4089717152 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 11973275 ps |
CPU time | 1.56 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:42:31 AM UTC 25 |
Peak memory | 211304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089717152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.4089717152 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.2598202605 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 2907831768 ps |
CPU time | 62.74 seconds |
Started | Feb 08 08:42:28 AM UTC 25 |
Finished | Feb 08 08:43:34 AM UTC 25 |
Peak memory | 214612 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598202605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2598202605 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.1729754868 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 2141454738 ps |
CPU time | 43.94 seconds |
Started | Feb 08 08:42:30 AM UTC 25 |
Finished | Feb 08 08:43:17 AM UTC 25 |
Peak memory | 214344 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729754868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.1729754868 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.2091621034 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 573176194 ps |
CPU time | 78.58 seconds |
Started | Feb 08 08:42:30 AM UTC 25 |
Finished | Feb 08 08:43:52 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091621034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.2091621034 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.628317776 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 23150526 ps |
CPU time | 4.06 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:37 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628317776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.628317776 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.3763565936 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 3338436066 ps |
CPU time | 8.96 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:42 AM UTC 25 |
Peak memory | 212572 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763565936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.3763565936 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.534732133 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 1454965034 ps |
CPU time | 4.07 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:37 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534732133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.534732133 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.2661378650 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 16409282703 ps |
CPU time | 74.82 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:43:49 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661378650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2661378650 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.3060290899 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 45708155 ps |
CPU time | 7.57 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:40 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060290899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.3060290899 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.2815066112 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 12498198 ps |
CPU time | 1.87 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:35 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815066112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.2815066112 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.1077627791 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 9482097 ps |
CPU time | 1.44 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:34 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077627791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1077627791 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.799559761 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1295371561 ps |
CPU time | 11.06 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:44 AM UTC 25 |
Peak memory | 212312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799559761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.799559761 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.1143876157 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 10365446 ps |
CPU time | 1.49 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:34 AM UTC 25 |
Peak memory | 211348 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143876157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.1143876157 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.936572300 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 161271993 ps |
CPU time | 26.45 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:43:00 AM UTC 25 |
Peak memory | 214540 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936572300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.936572300 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.399206235 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 7170260710 ps |
CPU time | 121.21 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:44:36 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399206235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.399206235 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.3387192972 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 77882250 ps |
CPU time | 3.65 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:37 AM UTC 25 |
Peak memory | 212276 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387192972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3387192972 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3994152584 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 1024074694 ps |
CPU time | 16.35 seconds |
Started | Feb 08 08:43:51 AM UTC 25 |
Finished | Feb 08 08:44:09 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994152584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3994152584 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.3769490941 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 33444431692 ps |
CPU time | 216.58 seconds |
Started | Feb 08 08:43:51 AM UTC 25 |
Finished | Feb 08 08:47:32 AM UTC 25 |
Peak memory | 214608 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769490941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.3769490941 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.2026160533 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 711690618 ps |
CPU time | 12.39 seconds |
Started | Feb 08 08:43:54 AM UTC 25 |
Finished | Feb 08 08:44:08 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026160533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.2026160533 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.597180557 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 367236841 ps |
CPU time | 8.89 seconds |
Started | Feb 08 08:43:53 AM UTC 25 |
Finished | Feb 08 08:44:04 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597180557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.597180557 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.2414362089 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 5317535405 ps |
CPU time | 17.17 seconds |
Started | Feb 08 08:43:48 AM UTC 25 |
Finished | Feb 08 08:44:08 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414362089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.2414362089 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.221820319 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 23098806028 ps |
CPU time | 196.02 seconds |
Started | Feb 08 08:43:50 AM UTC 25 |
Finished | Feb 08 08:47:10 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221820319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.221820319 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.1457341058 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 3323939296 ps |
CPU time | 21.91 seconds |
Started | Feb 08 08:43:50 AM UTC 25 |
Finished | Feb 08 08:44:14 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457341058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1457341058 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.1994813558 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 33280916 ps |
CPU time | 3.58 seconds |
Started | Feb 08 08:43:50 AM UTC 25 |
Finished | Feb 08 08:43:55 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994813558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.1994813558 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1106200919 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 90133350 ps |
CPU time | 1.93 seconds |
Started | Feb 08 08:43:52 AM UTC 25 |
Finished | Feb 08 08:43:56 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106200919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1106200919 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.3976115942 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 106919279 ps |
CPU time | 2.11 seconds |
Started | Feb 08 08:43:46 AM UTC 25 |
Finished | Feb 08 08:43:50 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976115942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3976115942 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.75523759 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 6753276679 ps |
CPU time | 12.05 seconds |
Started | Feb 08 08:43:47 AM UTC 25 |
Finished | Feb 08 08:44:01 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75523759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.75523759 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3331102404 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 5226727095 ps |
CPU time | 12.5 seconds |
Started | Feb 08 08:43:47 AM UTC 25 |
Finished | Feb 08 08:44:02 AM UTC 25 |
Peak memory | 212424 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331102404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3331102404 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.2894764488 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 9634068 ps |
CPU time | 1.85 seconds |
Started | Feb 08 08:43:46 AM UTC 25 |
Finished | Feb 08 08:43:50 AM UTC 25 |
Peak memory | 211420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894764488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.2894764488 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.319486434 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 903996055 ps |
CPU time | 64.16 seconds |
Started | Feb 08 08:43:55 AM UTC 25 |
Finished | Feb 08 08:45:02 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319486434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.319486434 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.1899015472 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 454195071 ps |
CPU time | 57.76 seconds |
Started | Feb 08 08:43:56 AM UTC 25 |
Finished | Feb 08 08:44:57 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899015472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.1899015472 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.680288685 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 95347513 ps |
CPU time | 9.63 seconds |
Started | Feb 08 08:43:55 AM UTC 25 |
Finished | Feb 08 08:44:06 AM UTC 25 |
Peak memory | 214360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680288685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.680288685 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.1752050323 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 163735666 ps |
CPU time | 24.23 seconds |
Started | Feb 08 08:43:56 AM UTC 25 |
Finished | Feb 08 08:44:23 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752050323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.1752050323 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.3991305743 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 36497299 ps |
CPU time | 4.39 seconds |
Started | Feb 08 08:43:54 AM UTC 25 |
Finished | Feb 08 08:44:00 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991305743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3991305743 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.4004944672 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 26476351 ps |
CPU time | 3.27 seconds |
Started | Feb 08 08:44:05 AM UTC 25 |
Finished | Feb 08 08:44:10 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004944672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.4004944672 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.2932885577 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 208365427 ps |
CPU time | 3.09 seconds |
Started | Feb 08 08:44:10 AM UTC 25 |
Finished | Feb 08 08:44:15 AM UTC 25 |
Peak memory | 212252 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932885577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.2932885577 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.1010038950 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 113401552 ps |
CPU time | 5.86 seconds |
Started | Feb 08 08:44:08 AM UTC 25 |
Finished | Feb 08 08:44:16 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010038950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1010038950 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.714720167 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 65355504 ps |
CPU time | 4.28 seconds |
Started | Feb 08 08:44:03 AM UTC 25 |
Finished | Feb 08 08:44:09 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714720167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.714720167 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.2756146133 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 6431829181 ps |
CPU time | 46.09 seconds |
Started | Feb 08 08:44:03 AM UTC 25 |
Finished | Feb 08 08:44:51 AM UTC 25 |
Peak memory | 212616 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756146133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2756146133 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.421683673 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 22783345827 ps |
CPU time | 170.94 seconds |
Started | Feb 08 08:44:04 AM UTC 25 |
Finished | Feb 08 08:46:58 AM UTC 25 |
Peak memory | 212376 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421683673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.421683673 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.660995306 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 29455303 ps |
CPU time | 3.4 seconds |
Started | Feb 08 08:44:03 AM UTC 25 |
Finished | Feb 08 08:44:08 AM UTC 25 |
Peak memory | 212484 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660995306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.660995306 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.3816173735 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 2963992240 ps |
CPU time | 10.82 seconds |
Started | Feb 08 08:44:08 AM UTC 25 |
Finished | Feb 08 08:44:21 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816173735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3816173735 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.1239511419 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 88312192 ps |
CPU time | 2.36 seconds |
Started | Feb 08 08:43:59 AM UTC 25 |
Finished | Feb 08 08:44:02 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239511419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1239511419 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.3842628645 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 3594126028 ps |
CPU time | 10.06 seconds |
Started | Feb 08 08:44:01 AM UTC 25 |
Finished | Feb 08 08:44:12 AM UTC 25 |
Peak memory | 212428 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842628645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.3842628645 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3459151649 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 1021129553 ps |
CPU time | 10.92 seconds |
Started | Feb 08 08:44:02 AM UTC 25 |
Finished | Feb 08 08:44:14 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459151649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3459151649 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.70894793 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 10458710 ps |
CPU time | 1.67 seconds |
Started | Feb 08 08:43:59 AM UTC 25 |
Finished | Feb 08 08:44:02 AM UTC 25 |
Peak memory | 211304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70894793 -assert nopostproc +UVM_TESTNAME=xbar_base_test + UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.70894793 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.311450502 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 665943294 ps |
CPU time | 65.37 seconds |
Started | Feb 08 08:44:11 AM UTC 25 |
Finished | Feb 08 08:45:19 AM UTC 25 |
Peak memory | 214548 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311450502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.311450502 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.1324281194 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 3197131199 ps |
CPU time | 52.77 seconds |
Started | Feb 08 08:44:11 AM UTC 25 |
Finished | Feb 08 08:45:06 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324281194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1324281194 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.490024294 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 128698517 ps |
CPU time | 29.18 seconds |
Started | Feb 08 08:44:11 AM UTC 25 |
Finished | Feb 08 08:44:42 AM UTC 25 |
Peak memory | 214356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490024294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.490024294 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.540517174 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 83387807 ps |
CPU time | 26.28 seconds |
Started | Feb 08 08:44:12 AM UTC 25 |
Finished | Feb 08 08:44:41 AM UTC 25 |
Peak memory | 214612 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540517174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.540517174 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.3580375590 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 465314547 ps |
CPU time | 10.57 seconds |
Started | Feb 08 08:44:10 AM UTC 25 |
Finished | Feb 08 08:44:22 AM UTC 25 |
Peak memory | 212184 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580375590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3580375590 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.1893839948 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 327573731 ps |
CPU time | 3.74 seconds |
Started | Feb 08 08:44:24 AM UTC 25 |
Finished | Feb 08 08:44:29 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893839948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.1893839948 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.3736946029 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 462043232 ps |
CPU time | 5.85 seconds |
Started | Feb 08 08:44:23 AM UTC 25 |
Finished | Feb 08 08:44:30 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736946029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.3736946029 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.2594953928 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 390521322 ps |
CPU time | 7.08 seconds |
Started | Feb 08 08:44:17 AM UTC 25 |
Finished | Feb 08 08:44:26 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594953928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.2594953928 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.2383160939 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 2814405068 ps |
CPU time | 20.84 seconds |
Started | Feb 08 08:44:17 AM UTC 25 |
Finished | Feb 08 08:44:40 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383160939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2383160939 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2481708532 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 16345978045 ps |
CPU time | 167.73 seconds |
Started | Feb 08 08:44:18 AM UTC 25 |
Finished | Feb 08 08:47:10 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481708532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2481708532 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.1868940382 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 63933678 ps |
CPU time | 8.61 seconds |
Started | Feb 08 08:44:17 AM UTC 25 |
Finished | Feb 08 08:44:28 AM UTC 25 |
Peak memory | 212288 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868940382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.1868940382 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.2342562499 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1116316604 ps |
CPU time | 8.18 seconds |
Started | Feb 08 08:44:22 AM UTC 25 |
Finished | Feb 08 08:44:32 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342562499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2342562499 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.3421521074 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 72028758 ps |
CPU time | 2.22 seconds |
Started | Feb 08 08:44:13 AM UTC 25 |
Finished | Feb 08 08:44:17 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421521074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3421521074 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.3133095981 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 5563335581 ps |
CPU time | 15.43 seconds |
Started | Feb 08 08:44:15 AM UTC 25 |
Finished | Feb 08 08:44:33 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133095981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3133095981 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.590372797 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2607175286 ps |
CPU time | 10.31 seconds |
Started | Feb 08 08:44:15 AM UTC 25 |
Finished | Feb 08 08:44:28 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590372797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.590372797 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.316898608 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 11089629 ps |
CPU time | 1.57 seconds |
Started | Feb 08 08:44:15 AM UTC 25 |
Finished | Feb 08 08:44:19 AM UTC 25 |
Peak memory | 211292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316898608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.316898608 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.2859239351 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 2314297389 ps |
CPU time | 48.16 seconds |
Started | Feb 08 08:44:26 AM UTC 25 |
Finished | Feb 08 08:45:17 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859239351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2859239351 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1718137474 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 5062340261 ps |
CPU time | 81.02 seconds |
Started | Feb 08 08:44:28 AM UTC 25 |
Finished | Feb 08 08:45:52 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718137474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1718137474 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.4040829976 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 10893886654 ps |
CPU time | 189.65 seconds |
Started | Feb 08 08:44:27 AM UTC 25 |
Finished | Feb 08 08:47:41 AM UTC 25 |
Peak memory | 216660 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040829976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.4040829976 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.2707499195 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 1744610736 ps |
CPU time | 62.01 seconds |
Started | Feb 08 08:44:28 AM UTC 25 |
Finished | Feb 08 08:45:33 AM UTC 25 |
Peak memory | 214604 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707499195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.2707499195 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.2216401221 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 159662262 ps |
CPU time | 6.03 seconds |
Started | Feb 08 08:44:24 AM UTC 25 |
Finished | Feb 08 08:44:32 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216401221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2216401221 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.63458233 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 746427048 ps |
CPU time | 10.45 seconds |
Started | Feb 08 08:44:37 AM UTC 25 |
Finished | Feb 08 08:44:49 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63458233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.63458233 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.4260249749 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 2362483069 ps |
CPU time | 8.88 seconds |
Started | Feb 08 08:44:44 AM UTC 25 |
Finished | Feb 08 08:44:55 AM UTC 25 |
Peak memory | 212288 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260249749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.4260249749 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.715014331 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 30550077 ps |
CPU time | 3.56 seconds |
Started | Feb 08 08:44:42 AM UTC 25 |
Finished | Feb 08 08:44:47 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715014331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.715014331 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1860816522 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 516511487 ps |
CPU time | 12.15 seconds |
Started | Feb 08 08:44:33 AM UTC 25 |
Finished | Feb 08 08:44:47 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860816522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1860816522 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.1117547459 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 28357475205 ps |
CPU time | 192.63 seconds |
Started | Feb 08 08:44:35 AM UTC 25 |
Finished | Feb 08 08:47:51 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117547459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1117547459 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.4021236792 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 1091860887 ps |
CPU time | 15.01 seconds |
Started | Feb 08 08:44:36 AM UTC 25 |
Finished | Feb 08 08:44:53 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021236792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.4021236792 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.58003131 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 121207855 ps |
CPU time | 7.32 seconds |
Started | Feb 08 08:44:34 AM UTC 25 |
Finished | Feb 08 08:44:43 AM UTC 25 |
Peak memory | 212552 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58003131 -assert nopostproc +UVM_TESTNAME=xbar_base_test + UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.58003131 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.2482554815 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 2509530155 ps |
CPU time | 17.12 seconds |
Started | Feb 08 08:44:42 AM UTC 25 |
Finished | Feb 08 08:45:01 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482554815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2482554815 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3998145412 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 40387762 ps |
CPU time | 1.94 seconds |
Started | Feb 08 08:44:31 AM UTC 25 |
Finished | Feb 08 08:44:34 AM UTC 25 |
Peak memory | 211296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998145412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3998145412 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.754253683 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 7502727430 ps |
CPU time | 11.07 seconds |
Started | Feb 08 08:44:33 AM UTC 25 |
Finished | Feb 08 08:44:46 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754253683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.754253683 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2080666362 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 1083704184 ps |
CPU time | 15.65 seconds |
Started | Feb 08 08:44:33 AM UTC 25 |
Finished | Feb 08 08:44:50 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080666362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2080666362 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.364713703 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 12928457 ps |
CPU time | 1.43 seconds |
Started | Feb 08 08:44:32 AM UTC 25 |
Finished | Feb 08 08:44:35 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364713703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.364713703 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.3860274932 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 12385981829 ps |
CPU time | 125.8 seconds |
Started | Feb 08 08:44:44 AM UTC 25 |
Finished | Feb 08 08:46:53 AM UTC 25 |
Peak memory | 214572 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860274932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3860274932 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.2607222359 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 274448711 ps |
CPU time | 27.86 seconds |
Started | Feb 08 08:44:47 AM UTC 25 |
Finished | Feb 08 08:45:17 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607222359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2607222359 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.217222245 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 1776090819 ps |
CPU time | 143.58 seconds |
Started | Feb 08 08:44:48 AM UTC 25 |
Finished | Feb 08 08:47:15 AM UTC 25 |
Peak memory | 218452 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217222245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.217222245 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.3843443365 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 189587389 ps |
CPU time | 5.17 seconds |
Started | Feb 08 08:44:43 AM UTC 25 |
Finished | Feb 08 08:44:50 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843443365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3843443365 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.958678583 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 66215239 ps |
CPU time | 10.47 seconds |
Started | Feb 08 08:44:53 AM UTC 25 |
Finished | Feb 08 08:45:05 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958678583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.958678583 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2207947230 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 12377875005 ps |
CPU time | 65.03 seconds |
Started | Feb 08 08:44:54 AM UTC 25 |
Finished | Feb 08 08:46:01 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207947230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.2207947230 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.2812033163 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 41694934 ps |
CPU time | 1.74 seconds |
Started | Feb 08 08:44:57 AM UTC 25 |
Finished | Feb 08 08:45:01 AM UTC 25 |
Peak memory | 211412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812033163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.2812033163 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.1780806860 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 79995543 ps |
CPU time | 3.59 seconds |
Started | Feb 08 08:44:56 AM UTC 25 |
Finished | Feb 08 08:45:01 AM UTC 25 |
Peak memory | 212444 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780806860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1780806860 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.491494132 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 590316002 ps |
CPU time | 8.95 seconds |
Started | Feb 08 08:44:50 AM UTC 25 |
Finished | Feb 08 08:45:01 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491494132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.491494132 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.3972000016 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 51560689413 ps |
CPU time | 149.74 seconds |
Started | Feb 08 08:44:51 AM UTC 25 |
Finished | Feb 08 08:47:24 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972000016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3972000016 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.4267830872 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 4916113133 ps |
CPU time | 32.95 seconds |
Started | Feb 08 08:44:53 AM UTC 25 |
Finished | Feb 08 08:45:27 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267830872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.4267830872 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.3023448676 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 10281316 ps |
CPU time | 1.57 seconds |
Started | Feb 08 08:44:51 AM UTC 25 |
Finished | Feb 08 08:44:55 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023448676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.3023448676 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.1538608413 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 874309229 ps |
CPU time | 13.04 seconds |
Started | Feb 08 08:44:56 AM UTC 25 |
Finished | Feb 08 08:45:11 AM UTC 25 |
Peak memory | 212232 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538608413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1538608413 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.2320568656 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 22874690 ps |
CPU time | 1.54 seconds |
Started | Feb 08 08:44:48 AM UTC 25 |
Finished | Feb 08 08:44:51 AM UTC 25 |
Peak memory | 211292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320568656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2320568656 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1005853432 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 2459787916 ps |
CPU time | 12.61 seconds |
Started | Feb 08 08:44:50 AM UTC 25 |
Finished | Feb 08 08:45:05 AM UTC 25 |
Peak memory | 212312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005853432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1005853432 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.1423148423 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 4127932142 ps |
CPU time | 19.72 seconds |
Started | Feb 08 08:44:50 AM UTC 25 |
Finished | Feb 08 08:45:12 AM UTC 25 |
Peak memory | 212312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423148423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1423148423 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.969923062 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 8124920 ps |
CPU time | 1.29 seconds |
Started | Feb 08 08:44:48 AM UTC 25 |
Finished | Feb 08 08:44:51 AM UTC 25 |
Peak memory | 211408 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969923062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.969923062 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.4126364571 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 3681863520 ps |
CPU time | 72.32 seconds |
Started | Feb 08 08:44:57 AM UTC 25 |
Finished | Feb 08 08:46:12 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126364571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4126364571 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.1313162638 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 4052637143 ps |
CPU time | 85.65 seconds |
Started | Feb 08 08:45:01 AM UTC 25 |
Finished | Feb 08 08:46:29 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313162638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1313162638 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.319716283 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 14423500030 ps |
CPU time | 281.48 seconds |
Started | Feb 08 08:44:58 AM UTC 25 |
Finished | Feb 08 08:49:45 AM UTC 25 |
Peak memory | 218912 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319716283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.319716283 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.1717592283 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 154424961 ps |
CPU time | 23.52 seconds |
Started | Feb 08 08:45:01 AM UTC 25 |
Finished | Feb 08 08:45:26 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717592283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.1717592283 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.245620248 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 56280091 ps |
CPU time | 6.2 seconds |
Started | Feb 08 08:44:56 AM UTC 25 |
Finished | Feb 08 08:45:04 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245620248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.245620248 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.2824091401 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 50018766 ps |
CPU time | 8.24 seconds |
Started | Feb 08 08:45:06 AM UTC 25 |
Finished | Feb 08 08:45:15 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824091401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.2824091401 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.2627403812 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 46631454632 ps |
CPU time | 249.38 seconds |
Started | Feb 08 08:45:06 AM UTC 25 |
Finished | Feb 08 08:49:19 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627403812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.2627403812 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.2253492318 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 1131852155 ps |
CPU time | 6.27 seconds |
Started | Feb 08 08:45:07 AM UTC 25 |
Finished | Feb 08 08:45:15 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253492318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.2253492318 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.3521261324 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 55931228 ps |
CPU time | 4.12 seconds |
Started | Feb 08 08:45:06 AM UTC 25 |
Finished | Feb 08 08:45:12 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521261324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3521261324 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.4056800150 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 1144327248 ps |
CPU time | 11.69 seconds |
Started | Feb 08 08:45:02 AM UTC 25 |
Finished | Feb 08 08:45:16 AM UTC 25 |
Peak memory | 212132 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056800150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4056800150 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1500685194 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 79779854584 ps |
CPU time | 187.66 seconds |
Started | Feb 08 08:45:03 AM UTC 25 |
Finished | Feb 08 08:48:14 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500685194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1500685194 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1218691987 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 10074361225 ps |
CPU time | 115.29 seconds |
Started | Feb 08 08:45:04 AM UTC 25 |
Finished | Feb 08 08:47:03 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218691987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1218691987 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.3151050644 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 9268705 ps |
CPU time | 1.59 seconds |
Started | Feb 08 08:45:02 AM UTC 25 |
Finished | Feb 08 08:45:05 AM UTC 25 |
Peak memory | 211416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151050644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.3151050644 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.1381196512 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 3404171749 ps |
CPU time | 20.56 seconds |
Started | Feb 08 08:45:06 AM UTC 25 |
Finished | Feb 08 08:45:28 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381196512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1381196512 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.1261747506 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 15747893 ps |
CPU time | 1.54 seconds |
Started | Feb 08 08:45:01 AM UTC 25 |
Finished | Feb 08 08:45:04 AM UTC 25 |
Peak memory | 211356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261747506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1261747506 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1396151424 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 3244828424 ps |
CPU time | 16.61 seconds |
Started | Feb 08 08:45:02 AM UTC 25 |
Finished | Feb 08 08:45:20 AM UTC 25 |
Peak memory | 212432 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396151424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1396151424 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3048378716 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 1305249673 ps |
CPU time | 12.22 seconds |
Started | Feb 08 08:45:02 AM UTC 25 |
Finished | Feb 08 08:45:16 AM UTC 25 |
Peak memory | 212264 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048378716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3048378716 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.180277496 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 11886952 ps |
CPU time | 1.51 seconds |
Started | Feb 08 08:45:01 AM UTC 25 |
Finished | Feb 08 08:45:04 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180277496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.180277496 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.1743709993 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 134273013 ps |
CPU time | 18.6 seconds |
Started | Feb 08 08:45:08 AM UTC 25 |
Finished | Feb 08 08:45:28 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743709993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1743709993 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.11586183 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 3660826264 ps |
CPU time | 72.26 seconds |
Started | Feb 08 08:45:10 AM UTC 25 |
Finished | Feb 08 08:46:25 AM UTC 25 |
Peak memory | 212436 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11586183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.11586183 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.2464300013 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 1599139891 ps |
CPU time | 128.86 seconds |
Started | Feb 08 08:45:10 AM UTC 25 |
Finished | Feb 08 08:47:22 AM UTC 25 |
Peak memory | 216400 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464300013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.2464300013 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3969103717 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 126072883 ps |
CPU time | 2.95 seconds |
Started | Feb 08 08:45:07 AM UTC 25 |
Finished | Feb 08 08:45:12 AM UTC 25 |
Peak memory | 212624 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969103717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3969103717 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.227298393 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 62977316 ps |
CPU time | 12.39 seconds |
Started | Feb 08 08:45:18 AM UTC 25 |
Finished | Feb 08 08:45:32 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227298393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.227298393 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.3240178458 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 13512613899 ps |
CPU time | 89.46 seconds |
Started | Feb 08 08:45:18 AM UTC 25 |
Finished | Feb 08 08:46:50 AM UTC 25 |
Peak memory | 212624 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240178458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.3240178458 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3079860992 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 38598580 ps |
CPU time | 4.87 seconds |
Started | Feb 08 08:45:21 AM UTC 25 |
Finished | Feb 08 08:45:28 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079860992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3079860992 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.3961282335 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 1012356502 ps |
CPU time | 15.11 seconds |
Started | Feb 08 08:45:20 AM UTC 25 |
Finished | Feb 08 08:45:37 AM UTC 25 |
Peak memory | 212276 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961282335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3961282335 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.3807130113 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 352183335 ps |
CPU time | 6.5 seconds |
Started | Feb 08 08:45:17 AM UTC 25 |
Finished | Feb 08 08:45:25 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807130113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.3807130113 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.469268823 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 3452851295 ps |
CPU time | 23.75 seconds |
Started | Feb 08 08:45:17 AM UTC 25 |
Finished | Feb 08 08:45:42 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469268823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.469268823 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1929395768 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 6160715694 ps |
CPU time | 63.22 seconds |
Started | Feb 08 08:45:18 AM UTC 25 |
Finished | Feb 08 08:46:24 AM UTC 25 |
Peak memory | 212512 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929395768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1929395768 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.1284215486 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 14437447 ps |
CPU time | 2.52 seconds |
Started | Feb 08 08:45:17 AM UTC 25 |
Finished | Feb 08 08:45:22 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284215486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.1284215486 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.3104500669 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 2944216553 ps |
CPU time | 15.74 seconds |
Started | Feb 08 08:45:18 AM UTC 25 |
Finished | Feb 08 08:45:36 AM UTC 25 |
Peak memory | 212312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104500669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3104500669 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.3283149536 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 77302344 ps |
CPU time | 2.67 seconds |
Started | Feb 08 08:45:12 AM UTC 25 |
Finished | Feb 08 08:45:17 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283149536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3283149536 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.313746125 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 4328039692 ps |
CPU time | 9.91 seconds |
Started | Feb 08 08:45:13 AM UTC 25 |
Finished | Feb 08 08:45:25 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313746125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.313746125 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.2876058769 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 2437267803 ps |
CPU time | 16.37 seconds |
Started | Feb 08 08:45:15 AM UTC 25 |
Finished | Feb 08 08:45:34 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876058769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2876058769 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.3681650429 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 12631958 ps |
CPU time | 1.7 seconds |
Started | Feb 08 08:45:12 AM UTC 25 |
Finished | Feb 08 08:45:16 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681650429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.3681650429 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.3420008106 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 335153367 ps |
CPU time | 49.17 seconds |
Started | Feb 08 08:45:22 AM UTC 25 |
Finished | Feb 08 08:46:14 AM UTC 25 |
Peak memory | 214348 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420008106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3420008106 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.2131038191 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 860136733 ps |
CPU time | 34.43 seconds |
Started | Feb 08 08:45:24 AM UTC 25 |
Finished | Feb 08 08:46:01 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131038191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2131038191 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.157264633 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 629481202 ps |
CPU time | 58.14 seconds |
Started | Feb 08 08:45:22 AM UTC 25 |
Finished | Feb 08 08:46:23 AM UTC 25 |
Peak memory | 214548 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157264633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.157264633 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.4255084571 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 253179374 ps |
CPU time | 26.94 seconds |
Started | Feb 08 08:45:26 AM UTC 25 |
Finished | Feb 08 08:45:55 AM UTC 25 |
Peak memory | 214668 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255084571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.4255084571 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.693033392 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 139799638 ps |
CPU time | 7.95 seconds |
Started | Feb 08 08:45:20 AM UTC 25 |
Finished | Feb 08 08:45:30 AM UTC 25 |
Peak memory | 212136 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693033392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.693033392 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2783399861 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 57598555 ps |
CPU time | 8.98 seconds |
Started | Feb 08 08:45:31 AM UTC 25 |
Finished | Feb 08 08:45:42 AM UTC 25 |
Peak memory | 212224 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783399861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2783399861 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.1039489808 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 46458532261 ps |
CPU time | 409.25 seconds |
Started | Feb 08 08:45:31 AM UTC 25 |
Finished | Feb 08 08:52:26 AM UTC 25 |
Peak memory | 220128 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039489808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.1039489808 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.3669678043 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 455294833 ps |
CPU time | 7.87 seconds |
Started | Feb 08 08:45:34 AM UTC 25 |
Finished | Feb 08 08:45:44 AM UTC 25 |
Peak memory | 211876 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669678043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.3669678043 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.2669477534 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 119355067 ps |
CPU time | 9.23 seconds |
Started | Feb 08 08:45:33 AM UTC 25 |
Finished | Feb 08 08:45:44 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669477534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2669477534 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2579983116 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 174772732 ps |
CPU time | 5.25 seconds |
Started | Feb 08 08:45:29 AM UTC 25 |
Finished | Feb 08 08:45:36 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579983116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2579983116 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.1424535009 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 34745284299 ps |
CPU time | 107.62 seconds |
Started | Feb 08 08:45:29 AM UTC 25 |
Finished | Feb 08 08:47:19 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424535009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1424535009 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.2708432807 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 12109165861 ps |
CPU time | 138.01 seconds |
Started | Feb 08 08:45:30 AM UTC 25 |
Finished | Feb 08 08:47:51 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708432807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2708432807 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.4128798990 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 11520743 ps |
CPU time | 1.61 seconds |
Started | Feb 08 08:45:29 AM UTC 25 |
Finished | Feb 08 08:45:32 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128798990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.4128798990 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.4127012532 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 105462519 ps |
CPU time | 6.11 seconds |
Started | Feb 08 08:45:31 AM UTC 25 |
Finished | Feb 08 08:45:39 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127012532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.4127012532 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.3283383944 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 162628804 ps |
CPU time | 2.14 seconds |
Started | Feb 08 08:45:26 AM UTC 25 |
Finished | Feb 08 08:45:30 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283383944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3283383944 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.4264079418 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 2161873599 ps |
CPU time | 12.62 seconds |
Started | Feb 08 08:45:27 AM UTC 25 |
Finished | Feb 08 08:45:41 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264079418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.4264079418 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.41241689 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 1651442406 ps |
CPU time | 20.29 seconds |
Started | Feb 08 08:45:28 AM UTC 25 |
Finished | Feb 08 08:45:50 AM UTC 25 |
Peak memory | 212504 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41241689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_ SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.41241689 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2839763440 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 13598610 ps |
CPU time | 1.31 seconds |
Started | Feb 08 08:45:26 AM UTC 25 |
Finished | Feb 08 08:45:30 AM UTC 25 |
Peak memory | 211292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839763440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2839763440 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.2029318006 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 981475825 ps |
CPU time | 21.55 seconds |
Started | Feb 08 08:45:34 AM UTC 25 |
Finished | Feb 08 08:45:58 AM UTC 25 |
Peak memory | 212096 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029318006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2029318006 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1040437193 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 12666828165 ps |
CPU time | 47.58 seconds |
Started | Feb 08 08:45:35 AM UTC 25 |
Finished | Feb 08 08:46:25 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040437193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1040437193 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.3153443312 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 250116174 ps |
CPU time | 26.76 seconds |
Started | Feb 08 08:45:37 AM UTC 25 |
Finished | Feb 08 08:46:05 AM UTC 25 |
Peak memory | 212016 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153443312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.3153443312 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.3062905651 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 1678889403 ps |
CPU time | 13.24 seconds |
Started | Feb 08 08:45:33 AM UTC 25 |
Finished | Feb 08 08:45:48 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062905651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3062905651 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.2068058141 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 8662336 ps |
CPU time | 2.01 seconds |
Started | Feb 08 08:45:43 AM UTC 25 |
Finished | Feb 08 08:45:47 AM UTC 25 |
Peak memory | 211364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068058141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.2068058141 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.3133119393 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 14264871683 ps |
CPU time | 88.4 seconds |
Started | Feb 08 08:45:45 AM UTC 25 |
Finished | Feb 08 08:47:15 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133119393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.3133119393 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3406406266 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 56664913 ps |
CPU time | 6.09 seconds |
Started | Feb 08 08:45:48 AM UTC 25 |
Finished | Feb 08 08:45:55 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406406266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3406406266 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.3346958360 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 160109823 ps |
CPU time | 7.3 seconds |
Started | Feb 08 08:45:46 AM UTC 25 |
Finished | Feb 08 08:45:55 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346958360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3346958360 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.2204695514 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 1743176655 ps |
CPU time | 13.77 seconds |
Started | Feb 08 08:45:41 AM UTC 25 |
Finished | Feb 08 08:45:57 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204695514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.2204695514 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.461538683 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 16535630578 ps |
CPU time | 129.35 seconds |
Started | Feb 08 08:45:42 AM UTC 25 |
Finished | Feb 08 08:47:55 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461538683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.461538683 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.2123589202 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 41162385659 ps |
CPU time | 216.2 seconds |
Started | Feb 08 08:45:42 AM UTC 25 |
Finished | Feb 08 08:49:22 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123589202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2123589202 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.3813567691 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 84558669 ps |
CPU time | 8.3 seconds |
Started | Feb 08 08:45:41 AM UTC 25 |
Finished | Feb 08 08:45:51 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813567691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3813567691 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.283363244 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 513998604 ps |
CPU time | 4.12 seconds |
Started | Feb 08 08:45:45 AM UTC 25 |
Finished | Feb 08 08:45:50 AM UTC 25 |
Peak memory | 212432 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283363244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.283363244 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.312846585 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 95313980 ps |
CPU time | 2.06 seconds |
Started | Feb 08 08:45:37 AM UTC 25 |
Finished | Feb 08 08:45:40 AM UTC 25 |
Peak memory | 212284 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312846585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.312846585 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.905012529 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 1255295880 ps |
CPU time | 13.29 seconds |
Started | Feb 08 08:45:40 AM UTC 25 |
Finished | Feb 08 08:45:55 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905012529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.905012529 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.1902241974 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 721942740 ps |
CPU time | 8 seconds |
Started | Feb 08 08:45:40 AM UTC 25 |
Finished | Feb 08 08:45:50 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902241974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1902241974 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.346010468 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 8322785 ps |
CPU time | 1.46 seconds |
Started | Feb 08 08:45:38 AM UTC 25 |
Finished | Feb 08 08:45:41 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346010468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.346010468 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.841623838 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 20887995461 ps |
CPU time | 69.16 seconds |
Started | Feb 08 08:45:49 AM UTC 25 |
Finished | Feb 08 08:47:01 AM UTC 25 |
Peak memory | 214420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841623838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.841623838 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.372538394 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 2796126743 ps |
CPU time | 42.47 seconds |
Started | Feb 08 08:45:51 AM UTC 25 |
Finished | Feb 08 08:46:36 AM UTC 25 |
Peak memory | 211480 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372538394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.372538394 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1342848489 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 777698931 ps |
CPU time | 143.76 seconds |
Started | Feb 08 08:45:50 AM UTC 25 |
Finished | Feb 08 08:48:17 AM UTC 25 |
Peak memory | 216404 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342848489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1342848489 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.426714501 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 3455309636 ps |
CPU time | 86.37 seconds |
Started | Feb 08 08:45:51 AM UTC 25 |
Finished | Feb 08 08:47:20 AM UTC 25 |
Peak memory | 216292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426714501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.426714501 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.1746587005 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 336805534 ps |
CPU time | 3.21 seconds |
Started | Feb 08 08:45:48 AM UTC 25 |
Finished | Feb 08 08:45:52 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746587005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1746587005 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.3218107936 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 2066966008 ps |
CPU time | 26.4 seconds |
Started | Feb 08 08:45:58 AM UTC 25 |
Finished | Feb 08 08:46:26 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218107936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.3218107936 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.1714030944 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 2402056080 ps |
CPU time | 33.14 seconds |
Started | Feb 08 08:45:58 AM UTC 25 |
Finished | Feb 08 08:46:33 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714030944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.1714030944 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.2762336007 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 92674329 ps |
CPU time | 4.94 seconds |
Started | Feb 08 08:46:05 AM UTC 25 |
Finished | Feb 08 08:46:11 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762336007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.2762336007 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.3166283999 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 93238233 ps |
CPU time | 2.79 seconds |
Started | Feb 08 08:46:01 AM UTC 25 |
Finished | Feb 08 08:46:06 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166283999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3166283999 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.642640644 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 265104498 ps |
CPU time | 6.04 seconds |
Started | Feb 08 08:45:56 AM UTC 25 |
Finished | Feb 08 08:46:03 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642640644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.642640644 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.1071954065 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 70747193196 ps |
CPU time | 93.42 seconds |
Started | Feb 08 08:45:57 AM UTC 25 |
Finished | Feb 08 08:47:33 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071954065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.1071954065 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.1687918106 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 34221174767 ps |
CPU time | 185.59 seconds |
Started | Feb 08 08:45:58 AM UTC 25 |
Finished | Feb 08 08:49:07 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687918106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1687918106 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.2674835482 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 76247010 ps |
CPU time | 10.99 seconds |
Started | Feb 08 08:45:57 AM UTC 25 |
Finished | Feb 08 08:46:10 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674835482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2674835482 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.3315481582 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 336957068 ps |
CPU time | 6.69 seconds |
Started | Feb 08 08:45:59 AM UTC 25 |
Finished | Feb 08 08:46:08 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315481582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.3315481582 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2335736407 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 446268355 ps |
CPU time | 2.55 seconds |
Started | Feb 08 08:45:52 AM UTC 25 |
Finished | Feb 08 08:45:57 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335736407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2335736407 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.600038100 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 2223922524 ps |
CPU time | 12.71 seconds |
Started | Feb 08 08:45:53 AM UTC 25 |
Finished | Feb 08 08:46:08 AM UTC 25 |
Peak memory | 212624 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600038100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.600038100 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.206608421 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 2461946403 ps |
CPU time | 13.52 seconds |
Started | Feb 08 08:45:56 AM UTC 25 |
Finished | Feb 08 08:46:11 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206608421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.206608421 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1546340269 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 9801237 ps |
CPU time | 1.68 seconds |
Started | Feb 08 08:45:53 AM UTC 25 |
Finished | Feb 08 08:45:57 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546340269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1546340269 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.32529177 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 6694090858 ps |
CPU time | 89.4 seconds |
Started | Feb 08 08:46:06 AM UTC 25 |
Finished | Feb 08 08:47:38 AM UTC 25 |
Peak memory | 214676 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32529177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bu ild_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.32529177 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.4143910691 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 14312394500 ps |
CPU time | 113.02 seconds |
Started | Feb 08 08:46:07 AM UTC 25 |
Finished | Feb 08 08:48:03 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143910691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.4143910691 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.2129412754 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 645542731 ps |
CPU time | 87.09 seconds |
Started | Feb 08 08:46:07 AM UTC 25 |
Finished | Feb 08 08:47:37 AM UTC 25 |
Peak memory | 216596 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129412754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.2129412754 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.228843129 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 443400002 ps |
CPU time | 85.56 seconds |
Started | Feb 08 08:46:07 AM UTC 25 |
Finished | Feb 08 08:47:35 AM UTC 25 |
Peak memory | 216596 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228843129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.228843129 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.3606215269 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 109948360 ps |
CPU time | 2.62 seconds |
Started | Feb 08 08:46:02 AM UTC 25 |
Finished | Feb 08 08:46:07 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606215269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3606215269 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.661959853 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 48878903 ps |
CPU time | 9.04 seconds |
Started | Feb 08 08:42:34 AM UTC 25 |
Finished | Feb 08 08:42:45 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661959853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.661959853 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.4214122707 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 37212621828 ps |
CPU time | 159.83 seconds |
Started | Feb 08 08:42:35 AM UTC 25 |
Finished | Feb 08 08:45:19 AM UTC 25 |
Peak memory | 212320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214122707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.4214122707 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.3551437016 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 466874458 ps |
CPU time | 11.67 seconds |
Started | Feb 08 08:42:36 AM UTC 25 |
Finished | Feb 08 08:42:49 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551437016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.3551437016 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.1325237863 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 37219737 ps |
CPU time | 3.17 seconds |
Started | Feb 08 08:42:36 AM UTC 25 |
Finished | Feb 08 08:42:40 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325237863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1325237863 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.2021561722 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 62466248 ps |
CPU time | 4.51 seconds |
Started | Feb 08 08:42:34 AM UTC 25 |
Finished | Feb 08 08:42:40 AM UTC 25 |
Peak memory | 212616 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021561722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.2021561722 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.440912609 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 31158367233 ps |
CPU time | 151.97 seconds |
Started | Feb 08 08:42:34 AM UTC 25 |
Finished | Feb 08 08:45:09 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440912609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.440912609 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2048637662 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 38358619614 ps |
CPU time | 281.29 seconds |
Started | Feb 08 08:42:34 AM UTC 25 |
Finished | Feb 08 08:47:20 AM UTC 25 |
Peak memory | 216072 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048637662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2048637662 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3142188242 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 63477587 ps |
CPU time | 9.06 seconds |
Started | Feb 08 08:42:34 AM UTC 25 |
Finished | Feb 08 08:42:45 AM UTC 25 |
Peak memory | 212484 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142188242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3142188242 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.2831101520 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 43931532 ps |
CPU time | 4.88 seconds |
Started | Feb 08 08:42:35 AM UTC 25 |
Finished | Feb 08 08:42:42 AM UTC 25 |
Peak memory | 212384 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831101520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2831101520 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.261961210 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 120015502 ps |
CPU time | 1.73 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:35 AM UTC 25 |
Peak memory | 211424 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261961210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.261961210 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.2833457854 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 3898072010 ps |
CPU time | 13.91 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:48 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833457854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.2833457854 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2240975460 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1831544161 ps |
CPU time | 8.78 seconds |
Started | Feb 08 08:42:33 AM UTC 25 |
Finished | Feb 08 08:42:44 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240975460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2240975460 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.2450173269 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 8536280 ps |
CPU time | 1.5 seconds |
Started | Feb 08 08:42:31 AM UTC 25 |
Finished | Feb 08 08:42:35 AM UTC 25 |
Peak memory | 211376 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450173269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.2450173269 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.3630338487 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 191939630 ps |
CPU time | 6.24 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:46 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630338487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3630338487 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.2750191136 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 74838989 ps |
CPU time | 13.36 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:54 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750191136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.2750191136 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.2436887292 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 8128733 ps |
CPU time | 1.56 seconds |
Started | Feb 08 08:42:36 AM UTC 25 |
Finished | Feb 08 08:42:39 AM UTC 25 |
Peak memory | 211320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436887292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2436887292 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.4162145627 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 62246802 ps |
CPU time | 8.08 seconds |
Started | Feb 08 08:46:15 AM UTC 25 |
Finished | Feb 08 08:46:24 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162145627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.4162145627 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.666052370 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 11425734899 ps |
CPU time | 40.9 seconds |
Started | Feb 08 08:46:16 AM UTC 25 |
Finished | Feb 08 08:46:59 AM UTC 25 |
Peak memory | 212436 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666052370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.666052370 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.1183810174 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 340143171 ps |
CPU time | 7.79 seconds |
Started | Feb 08 08:46:23 AM UTC 25 |
Finished | Feb 08 08:46:33 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183810174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.1183810174 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.3585558581 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 644144260 ps |
CPU time | 7.79 seconds |
Started | Feb 08 08:46:19 AM UTC 25 |
Finished | Feb 08 08:46:28 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585558581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3585558581 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.3058334450 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 137938480 ps |
CPU time | 9.35 seconds |
Started | Feb 08 08:46:11 AM UTC 25 |
Finished | Feb 08 08:46:22 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058334450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.3058334450 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.3102511657 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 31349290263 ps |
CPU time | 179.06 seconds |
Started | Feb 08 08:46:13 AM UTC 25 |
Finished | Feb 08 08:49:15 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102511657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3102511657 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.2481366056 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 3800647776 ps |
CPU time | 18.64 seconds |
Started | Feb 08 08:46:14 AM UTC 25 |
Finished | Feb 08 08:46:34 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481366056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2481366056 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.49812178 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 36810773 ps |
CPU time | 4.48 seconds |
Started | Feb 08 08:46:13 AM UTC 25 |
Finished | Feb 08 08:46:19 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49812178 -assert nopostproc +UVM_TESTNAME=xbar_base_test + UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.49812178 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.1106425508 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 4487432784 ps |
CPU time | 16.28 seconds |
Started | Feb 08 08:46:18 AM UTC 25 |
Finished | Feb 08 08:46:36 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106425508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1106425508 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.2679836042 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 62254131 ps |
CPU time | 1.87 seconds |
Started | Feb 08 08:46:08 AM UTC 25 |
Finished | Feb 08 08:46:12 AM UTC 25 |
Peak memory | 211292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679836042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2679836042 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.2943747111 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 4855593877 ps |
CPU time | 18.87 seconds |
Started | Feb 08 08:46:10 AM UTC 25 |
Finished | Feb 08 08:46:31 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943747111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2943747111 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2765895196 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 2456290641 ps |
CPU time | 10.19 seconds |
Started | Feb 08 08:46:11 AM UTC 25 |
Finished | Feb 08 08:46:23 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765895196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2765895196 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.780830616 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 8826134 ps |
CPU time | 1.72 seconds |
Started | Feb 08 08:46:09 AM UTC 25 |
Finished | Feb 08 08:46:13 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780830616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.780830616 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.337928370 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 11558715445 ps |
CPU time | 97.29 seconds |
Started | Feb 08 08:46:24 AM UTC 25 |
Finished | Feb 08 08:48:03 AM UTC 25 |
Peak memory | 214612 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337928370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.337928370 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.529015933 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 26153466913 ps |
CPU time | 51.25 seconds |
Started | Feb 08 08:46:25 AM UTC 25 |
Finished | Feb 08 08:47:18 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529015933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.529015933 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.364634812 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 255151971 ps |
CPU time | 59.56 seconds |
Started | Feb 08 08:46:25 AM UTC 25 |
Finished | Feb 08 08:47:27 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364634812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.364634812 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1249858799 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 158859319 ps |
CPU time | 15.64 seconds |
Started | Feb 08 08:46:26 AM UTC 25 |
Finished | Feb 08 08:46:44 AM UTC 25 |
Peak memory | 212456 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249858799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1249858799 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.3462972429 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 866915228 ps |
CPU time | 4.92 seconds |
Started | Feb 08 08:46:23 AM UTC 25 |
Finished | Feb 08 08:46:30 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462972429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3462972429 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.51885691 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 851098796 ps |
CPU time | 23.62 seconds |
Started | Feb 08 08:46:32 AM UTC 25 |
Finished | Feb 08 08:46:57 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51885691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.51885691 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.3103849002 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 55579473050 ps |
CPU time | 257.54 seconds |
Started | Feb 08 08:46:34 AM UTC 25 |
Finished | Feb 08 08:50:55 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103849002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.3103849002 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.3000055676 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 24088387 ps |
CPU time | 1.71 seconds |
Started | Feb 08 08:46:35 AM UTC 25 |
Finished | Feb 08 08:46:38 AM UTC 25 |
Peak memory | 211368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000055676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.3000055676 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.2598805635 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 791806939 ps |
CPU time | 7.56 seconds |
Started | Feb 08 08:46:35 AM UTC 25 |
Finished | Feb 08 08:46:44 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598805635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2598805635 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.2012815122 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 13941984 ps |
CPU time | 2.24 seconds |
Started | Feb 08 08:46:30 AM UTC 25 |
Finished | Feb 08 08:46:34 AM UTC 25 |
Peak memory | 212192 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012815122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.2012815122 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.503435092 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 71328669005 ps |
CPU time | 159.89 seconds |
Started | Feb 08 08:46:30 AM UTC 25 |
Finished | Feb 08 08:49:13 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503435092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.503435092 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.4205400655 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 16013977941 ps |
CPU time | 99.48 seconds |
Started | Feb 08 08:46:32 AM UTC 25 |
Finished | Feb 08 08:48:14 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205400655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.4205400655 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.230950205 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 17018124 ps |
CPU time | 1.88 seconds |
Started | Feb 08 08:46:30 AM UTC 25 |
Finished | Feb 08 08:46:34 AM UTC 25 |
Peak memory | 211208 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230950205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.230950205 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.3460743000 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 77402957 ps |
CPU time | 3.6 seconds |
Started | Feb 08 08:46:34 AM UTC 25 |
Finished | Feb 08 08:46:39 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460743000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3460743000 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.813723633 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 69897782 ps |
CPU time | 1.88 seconds |
Started | Feb 08 08:46:26 AM UTC 25 |
Finished | Feb 08 08:46:30 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813723633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.813723633 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.2001634175 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 2158296828 ps |
CPU time | 12.12 seconds |
Started | Feb 08 08:46:27 AM UTC 25 |
Finished | Feb 08 08:46:41 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001634175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2001634175 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.456960931 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 698625726 ps |
CPU time | 9.17 seconds |
Started | Feb 08 08:46:29 AM UTC 25 |
Finished | Feb 08 08:46:40 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456960931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.456960931 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.2472030610 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 9316594 ps |
CPU time | 1.7 seconds |
Started | Feb 08 08:46:26 AM UTC 25 |
Finished | Feb 08 08:46:29 AM UTC 25 |
Peak memory | 211284 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472030610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.2472030610 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.829572403 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 430942814 ps |
CPU time | 30.55 seconds |
Started | Feb 08 08:46:37 AM UTC 25 |
Finished | Feb 08 08:47:10 AM UTC 25 |
Peak memory | 212252 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829572403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.829572403 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.3159146915 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 13656845863 ps |
CPU time | 68.95 seconds |
Started | Feb 08 08:46:38 AM UTC 25 |
Finished | Feb 08 08:47:49 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159146915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3159146915 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.4084724841 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 3841723367 ps |
CPU time | 94.36 seconds |
Started | Feb 08 08:46:37 AM UTC 25 |
Finished | Feb 08 08:48:14 AM UTC 25 |
Peak memory | 216468 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084724841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.4084724841 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.835265272 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 458609884 ps |
CPU time | 52.61 seconds |
Started | Feb 08 08:46:40 AM UTC 25 |
Finished | Feb 08 08:47:34 AM UTC 25 |
Peak memory | 214548 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835265272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.835265272 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.859103542 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 47434682 ps |
CPU time | 4.41 seconds |
Started | Feb 08 08:46:35 AM UTC 25 |
Finished | Feb 08 08:46:41 AM UTC 25 |
Peak memory | 212416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859103542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.859103542 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.116383692 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 391690188 ps |
CPU time | 8.58 seconds |
Started | Feb 08 08:46:50 AM UTC 25 |
Finished | Feb 08 08:47:00 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116383692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.116383692 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.911282336 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 122045354 ps |
CPU time | 2.88 seconds |
Started | Feb 08 08:46:53 AM UTC 25 |
Finished | Feb 08 08:46:58 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911282336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.911282336 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.3888890488 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 1740163214 ps |
CPU time | 12.95 seconds |
Started | Feb 08 08:46:51 AM UTC 25 |
Finished | Feb 08 08:47:06 AM UTC 25 |
Peak memory | 212568 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888890488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3888890488 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.1628442748 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 28111203 ps |
CPU time | 3.65 seconds |
Started | Feb 08 08:46:44 AM UTC 25 |
Finished | Feb 08 08:46:49 AM UTC 25 |
Peak memory | 212316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628442748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.1628442748 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.2197512462 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 3210390033 ps |
CPU time | 19.31 seconds |
Started | Feb 08 08:46:44 AM UTC 25 |
Finished | Feb 08 08:47:05 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197512462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2197512462 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.192215224 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 22121320386 ps |
CPU time | 81.68 seconds |
Started | Feb 08 08:46:46 AM UTC 25 |
Finished | Feb 08 08:48:09 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192215224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.192215224 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.1092108687 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 169559122 ps |
CPU time | 8.54 seconds |
Started | Feb 08 08:46:44 AM UTC 25 |
Finished | Feb 08 08:46:54 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092108687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.1092108687 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.3086760657 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 274938948 ps |
CPU time | 4.09 seconds |
Started | Feb 08 08:46:50 AM UTC 25 |
Finished | Feb 08 08:46:55 AM UTC 25 |
Peak memory | 212232 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086760657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3086760657 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.1731784534 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 54955910 ps |
CPU time | 2.35 seconds |
Started | Feb 08 08:46:40 AM UTC 25 |
Finished | Feb 08 08:46:43 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731784534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1731784534 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.683795872 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 4994485639 ps |
CPU time | 8.34 seconds |
Started | Feb 08 08:46:42 AM UTC 25 |
Finished | Feb 08 08:46:52 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683795872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.683795872 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.611254565 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 1945354211 ps |
CPU time | 20.24 seconds |
Started | Feb 08 08:46:42 AM UTC 25 |
Finished | Feb 08 08:47:04 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611254565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.611254565 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.742354727 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 10955003 ps |
CPU time | 1.41 seconds |
Started | Feb 08 08:46:41 AM UTC 25 |
Finished | Feb 08 08:46:44 AM UTC 25 |
Peak memory | 211304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742354727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.742354727 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.2680886709 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 9252103949 ps |
CPU time | 19.84 seconds |
Started | Feb 08 08:46:54 AM UTC 25 |
Finished | Feb 08 08:47:16 AM UTC 25 |
Peak memory | 214608 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680886709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2680886709 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.923684411 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 7070458968 ps |
CPU time | 44.99 seconds |
Started | Feb 08 08:46:57 AM UTC 25 |
Finished | Feb 08 08:47:43 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923684411 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.923684411 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.3747093198 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 299982918 ps |
CPU time | 59.52 seconds |
Started | Feb 08 08:46:56 AM UTC 25 |
Finished | Feb 08 08:47:57 AM UTC 25 |
Peak memory | 214356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747093198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.3747093198 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.2869069771 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 1713045509 ps |
CPU time | 103.51 seconds |
Started | Feb 08 08:46:58 AM UTC 25 |
Finished | Feb 08 08:48:44 AM UTC 25 |
Peak memory | 216524 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869069771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.2869069771 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.3962999300 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 2162406169 ps |
CPU time | 12.3 seconds |
Started | Feb 08 08:46:52 AM UTC 25 |
Finished | Feb 08 08:47:06 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962999300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3962999300 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.291315112 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 1169786699 ps |
CPU time | 17.25 seconds |
Started | Feb 08 08:47:04 AM UTC 25 |
Finished | Feb 08 08:47:23 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291315112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.291315112 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.962457702 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 25218425864 ps |
CPU time | 49.02 seconds |
Started | Feb 08 08:47:05 AM UTC 25 |
Finished | Feb 08 08:47:56 AM UTC 25 |
Peak memory | 212132 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962457702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.962457702 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.3569939624 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 1015401347 ps |
CPU time | 12.57 seconds |
Started | Feb 08 08:47:06 AM UTC 25 |
Finished | Feb 08 08:47:20 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569939624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.3569939624 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.3744716914 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 1285625497 ps |
CPU time | 11.91 seconds |
Started | Feb 08 08:47:06 AM UTC 25 |
Finished | Feb 08 08:47:20 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744716914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3744716914 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.4219701495 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 1868704031 ps |
CPU time | 12.82 seconds |
Started | Feb 08 08:47:01 AM UTC 25 |
Finished | Feb 08 08:47:16 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219701495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.4219701495 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.1800169931 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 34936415619 ps |
CPU time | 91.47 seconds |
Started | Feb 08 08:47:03 AM UTC 25 |
Finished | Feb 08 08:48:38 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800169931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1800169931 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.1160004632 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 31547926268 ps |
CPU time | 154.67 seconds |
Started | Feb 08 08:47:03 AM UTC 25 |
Finished | Feb 08 08:49:42 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160004632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1160004632 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.1515735145 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 16552047 ps |
CPU time | 2.79 seconds |
Started | Feb 08 08:47:01 AM UTC 25 |
Finished | Feb 08 08:47:05 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515735145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.1515735145 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.905523854 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 2016896762 ps |
CPU time | 17.35 seconds |
Started | Feb 08 08:47:05 AM UTC 25 |
Finished | Feb 08 08:47:24 AM UTC 25 |
Peak memory | 212100 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905523854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.905523854 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.2834359895 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 120816671 ps |
CPU time | 2.3 seconds |
Started | Feb 08 08:46:59 AM UTC 25 |
Finished | Feb 08 08:47:03 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834359895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2834359895 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.851857302 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 2872125603 ps |
CPU time | 14.07 seconds |
Started | Feb 08 08:47:00 AM UTC 25 |
Finished | Feb 08 08:47:16 AM UTC 25 |
Peak memory | 212276 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851857302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.851857302 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.493462468 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 1006301446 ps |
CPU time | 5.87 seconds |
Started | Feb 08 08:47:00 AM UTC 25 |
Finished | Feb 08 08:47:07 AM UTC 25 |
Peak memory | 212380 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493462468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.493462468 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3157251727 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 14462022 ps |
CPU time | 1.75 seconds |
Started | Feb 08 08:46:59 AM UTC 25 |
Finished | Feb 08 08:47:02 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157251727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3157251727 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.317372487 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 161496619 ps |
CPU time | 8.25 seconds |
Started | Feb 08 08:47:07 AM UTC 25 |
Finished | Feb 08 08:47:17 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317372487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.317372487 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.2851940669 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 3600535108 ps |
CPU time | 30.41 seconds |
Started | Feb 08 08:47:08 AM UTC 25 |
Finished | Feb 08 08:47:40 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851940669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2851940669 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.504004727 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 653417444 ps |
CPU time | 96.25 seconds |
Started | Feb 08 08:47:08 AM UTC 25 |
Finished | Feb 08 08:48:47 AM UTC 25 |
Peak memory | 214552 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504004727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.504004727 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3216227902 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 531488721 ps |
CPU time | 41.87 seconds |
Started | Feb 08 08:47:11 AM UTC 25 |
Finished | Feb 08 08:47:54 AM UTC 25 |
Peak memory | 214348 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216227902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3216227902 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1261018393 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 551657947 ps |
CPU time | 5.61 seconds |
Started | Feb 08 08:47:06 AM UTC 25 |
Finished | Feb 08 08:47:13 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261018393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1261018393 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.912599416 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 312071846 ps |
CPU time | 9.15 seconds |
Started | Feb 08 08:47:16 AM UTC 25 |
Finished | Feb 08 08:47:27 AM UTC 25 |
Peak memory | 212116 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912599416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.912599416 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.3397321098 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 233134102 ps |
CPU time | 3.81 seconds |
Started | Feb 08 08:47:20 AM UTC 25 |
Finished | Feb 08 08:47:25 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397321098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.3397321098 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.4157054463 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 783927034 ps |
CPU time | 15.09 seconds |
Started | Feb 08 08:47:18 AM UTC 25 |
Finished | Feb 08 08:47:34 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157054463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.4157054463 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.2244724018 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 66215747 ps |
CPU time | 9.04 seconds |
Started | Feb 08 08:47:14 AM UTC 25 |
Finished | Feb 08 08:47:25 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244724018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.2244724018 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.284060889 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 23715773110 ps |
CPU time | 95.88 seconds |
Started | Feb 08 08:47:16 AM UTC 25 |
Finished | Feb 08 08:48:55 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284060889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.284060889 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.3180041980 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 51984994774 ps |
CPU time | 149.06 seconds |
Started | Feb 08 08:47:16 AM UTC 25 |
Finished | Feb 08 08:49:48 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180041980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.3180041980 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.121962782 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 56374627 ps |
CPU time | 7.82 seconds |
Started | Feb 08 08:47:14 AM UTC 25 |
Finished | Feb 08 08:47:24 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121962782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.121962782 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.1360612917 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 47187269 ps |
CPU time | 5.62 seconds |
Started | Feb 08 08:47:18 AM UTC 25 |
Finished | Feb 08 08:47:25 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360612917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1360612917 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.1098308421 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 9285127 ps |
CPU time | 1.53 seconds |
Started | Feb 08 08:47:11 AM UTC 25 |
Finished | Feb 08 08:47:13 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098308421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1098308421 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.3442631367 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 6074194791 ps |
CPU time | 6.8 seconds |
Started | Feb 08 08:47:12 AM UTC 25 |
Finished | Feb 08 08:47:20 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442631367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3442631367 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.1909552697 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 873674612 ps |
CPU time | 8.76 seconds |
Started | Feb 08 08:47:14 AM UTC 25 |
Finished | Feb 08 08:47:24 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909552697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.1909552697 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.115609608 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 12148823 ps |
CPU time | 1.43 seconds |
Started | Feb 08 08:47:11 AM UTC 25 |
Finished | Feb 08 08:47:13 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115609608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.115609608 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.2365493021 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 4509521524 ps |
CPU time | 66.45 seconds |
Started | Feb 08 08:47:21 AM UTC 25 |
Finished | Feb 08 08:48:30 AM UTC 25 |
Peak memory | 214396 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365493021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.2365493021 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.4089321028 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 227143967 ps |
CPU time | 17.89 seconds |
Started | Feb 08 08:47:21 AM UTC 25 |
Finished | Feb 08 08:47:41 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089321028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.4089321028 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.1147168953 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 10298405 ps |
CPU time | 6.61 seconds |
Started | Feb 08 08:47:21 AM UTC 25 |
Finished | Feb 08 08:47:30 AM UTC 25 |
Peak memory | 212136 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147168953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.1147168953 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.2944682575 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 2147249073 ps |
CPU time | 74.8 seconds |
Started | Feb 08 08:47:21 AM UTC 25 |
Finished | Feb 08 08:48:39 AM UTC 25 |
Peak memory | 214540 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944682575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.2944682575 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.2480052062 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 77861618 ps |
CPU time | 7.67 seconds |
Started | Feb 08 08:47:19 AM UTC 25 |
Finished | Feb 08 08:47:28 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480052062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2480052062 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.122302820 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 46455183 ps |
CPU time | 8.08 seconds |
Started | Feb 08 08:47:26 AM UTC 25 |
Finished | Feb 08 08:47:36 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122302820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.122302820 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.1073430614 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 46266024679 ps |
CPU time | 108.51 seconds |
Started | Feb 08 08:47:26 AM UTC 25 |
Finished | Feb 08 08:49:17 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073430614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.1073430614 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.3453818720 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 662802660 ps |
CPU time | 9.04 seconds |
Started | Feb 08 08:47:27 AM UTC 25 |
Finished | Feb 08 08:47:38 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453818720 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.3453818720 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.203495303 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 53419122 ps |
CPU time | 5.42 seconds |
Started | Feb 08 08:47:27 AM UTC 25 |
Finished | Feb 08 08:47:34 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203495303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.203495303 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.2972348983 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 92909591 ps |
CPU time | 3.38 seconds |
Started | Feb 08 08:47:25 AM UTC 25 |
Finished | Feb 08 08:47:31 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972348983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.2972348983 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.2335038477 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 50735609568 ps |
CPU time | 125.72 seconds |
Started | Feb 08 08:47:26 AM UTC 25 |
Finished | Feb 08 08:49:34 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335038477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2335038477 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.1131115830 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 134945739429 ps |
CPU time | 149.01 seconds |
Started | Feb 08 08:47:26 AM UTC 25 |
Finished | Feb 08 08:49:58 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131115830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1131115830 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.362670958 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 22356287 ps |
CPU time | 3.02 seconds |
Started | Feb 08 08:47:26 AM UTC 25 |
Finished | Feb 08 08:47:31 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362670958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.362670958 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.511959983 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 166466043 ps |
CPU time | 4.8 seconds |
Started | Feb 08 08:47:27 AM UTC 25 |
Finished | Feb 08 08:47:34 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511959983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.511959983 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.1671649930 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 14993543 ps |
CPU time | 1.28 seconds |
Started | Feb 08 08:47:21 AM UTC 25 |
Finished | Feb 08 08:47:24 AM UTC 25 |
Peak memory | 211356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671649930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1671649930 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2287019891 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 3394697350 ps |
CPU time | 11.61 seconds |
Started | Feb 08 08:47:24 AM UTC 25 |
Finished | Feb 08 08:47:37 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287019891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2287019891 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.3620069309 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 7559550499 ps |
CPU time | 12.59 seconds |
Started | Feb 08 08:47:25 AM UTC 25 |
Finished | Feb 08 08:47:40 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620069309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3620069309 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2857209626 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 9720967 ps |
CPU time | 1.6 seconds |
Started | Feb 08 08:47:23 AM UTC 25 |
Finished | Feb 08 08:47:26 AM UTC 25 |
Peak memory | 211296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857209626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2857209626 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.1899244146 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 991336734 ps |
CPU time | 15.48 seconds |
Started | Feb 08 08:47:28 AM UTC 25 |
Finished | Feb 08 08:47:45 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899244146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1899244146 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1950073583 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 87233976 ps |
CPU time | 6.19 seconds |
Started | Feb 08 08:47:31 AM UTC 25 |
Finished | Feb 08 08:47:38 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950073583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1950073583 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.490250363 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 1695353193 ps |
CPU time | 130.2 seconds |
Started | Feb 08 08:47:29 AM UTC 25 |
Finished | Feb 08 08:49:42 AM UTC 25 |
Peak memory | 218456 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490250363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.490250363 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.4169070757 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 7649557666 ps |
CPU time | 117.31 seconds |
Started | Feb 08 08:47:32 AM UTC 25 |
Finished | Feb 08 08:49:32 AM UTC 25 |
Peak memory | 218504 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169070757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.4169070757 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.157359760 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 57901940 ps |
CPU time | 7.65 seconds |
Started | Feb 08 08:47:27 AM UTC 25 |
Finished | Feb 08 08:47:37 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157359760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.157359760 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.107645994 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 1621891977 ps |
CPU time | 21.64 seconds |
Started | Feb 08 08:47:37 AM UTC 25 |
Finished | Feb 08 08:48:01 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107645994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.107645994 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.3669513279 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 538806446 ps |
CPU time | 7.68 seconds |
Started | Feb 08 08:47:39 AM UTC 25 |
Finished | Feb 08 08:47:48 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669513279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.3669513279 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.687110337 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 10859152 ps |
CPU time | 1.3 seconds |
Started | Feb 08 08:47:39 AM UTC 25 |
Finished | Feb 08 08:47:41 AM UTC 25 |
Peak memory | 211108 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687110337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.687110337 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.368406835 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 1198033900 ps |
CPU time | 15.39 seconds |
Started | Feb 08 08:47:36 AM UTC 25 |
Finished | Feb 08 08:47:53 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368406835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.368406835 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.1713316340 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 44890166910 ps |
CPU time | 79.98 seconds |
Started | Feb 08 08:47:36 AM UTC 25 |
Finished | Feb 08 08:48:58 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713316340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.1713316340 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.1624710665 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 63230682034 ps |
CPU time | 181.91 seconds |
Started | Feb 08 08:47:36 AM UTC 25 |
Finished | Feb 08 08:50:41 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624710665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1624710665 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.2385686284 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 25669678 ps |
CPU time | 3.84 seconds |
Started | Feb 08 08:47:36 AM UTC 25 |
Finished | Feb 08 08:47:41 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385686284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.2385686284 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.2437043748 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 769547567 ps |
CPU time | 8.16 seconds |
Started | Feb 08 08:47:37 AM UTC 25 |
Finished | Feb 08 08:47:47 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437043748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.2437043748 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.3203215665 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 9515884 ps |
CPU time | 1.62 seconds |
Started | Feb 08 08:47:32 AM UTC 25 |
Finished | Feb 08 08:47:35 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203215665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3203215665 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.2591544289 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 2760989779 ps |
CPU time | 18.63 seconds |
Started | Feb 08 08:47:34 AM UTC 25 |
Finished | Feb 08 08:47:54 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591544289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2591544289 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.1559093381 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 1695010848 ps |
CPU time | 13.75 seconds |
Started | Feb 08 08:47:34 AM UTC 25 |
Finished | Feb 08 08:47:50 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559093381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1559093381 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.3816026633 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 9650937 ps |
CPU time | 1.59 seconds |
Started | Feb 08 08:47:33 AM UTC 25 |
Finished | Feb 08 08:47:36 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816026633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.3816026633 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.972507399 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 1070765575 ps |
CPU time | 47.59 seconds |
Started | Feb 08 08:47:39 AM UTC 25 |
Finished | Feb 08 08:48:29 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972507399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.972507399 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.398873643 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 416600961 ps |
CPU time | 24.73 seconds |
Started | Feb 08 08:47:39 AM UTC 25 |
Finished | Feb 08 08:48:06 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398873643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.398873643 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.3296574986 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 700084755 ps |
CPU time | 77.43 seconds |
Started | Feb 08 08:47:39 AM UTC 25 |
Finished | Feb 08 08:48:59 AM UTC 25 |
Peak memory | 216400 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296574986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.3296574986 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.2889634245 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 86177793 ps |
CPU time | 5.94 seconds |
Started | Feb 08 08:47:40 AM UTC 25 |
Finished | Feb 08 08:47:48 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889634245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.2889634245 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.720737746 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 37571182 ps |
CPU time | 3.2 seconds |
Started | Feb 08 08:47:39 AM UTC 25 |
Finished | Feb 08 08:47:44 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720737746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.720737746 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.3950983582 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 1298860836 ps |
CPU time | 19.52 seconds |
Started | Feb 08 08:47:45 AM UTC 25 |
Finished | Feb 08 08:48:07 AM UTC 25 |
Peak memory | 212288 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950983582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.3950983582 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2543860618 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 180242218186 ps |
CPU time | 233.36 seconds |
Started | Feb 08 08:47:45 AM UTC 25 |
Finished | Feb 08 08:51:42 AM UTC 25 |
Peak memory | 214476 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543860618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2543860618 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1039109501 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 445592175 ps |
CPU time | 7.79 seconds |
Started | Feb 08 08:47:49 AM UTC 25 |
Finished | Feb 08 08:47:58 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039109501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1039109501 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.650884937 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 52959628 ps |
CPU time | 7.1 seconds |
Started | Feb 08 08:47:48 AM UTC 25 |
Finished | Feb 08 08:47:56 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650884937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.650884937 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.3143056918 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 381642455 ps |
CPU time | 9.96 seconds |
Started | Feb 08 08:47:43 AM UTC 25 |
Finished | Feb 08 08:47:54 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143056918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.3143056918 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.1335321651 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 115841973303 ps |
CPU time | 149.16 seconds |
Started | Feb 08 08:47:44 AM UTC 25 |
Finished | Feb 08 08:50:16 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335321651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.1335321651 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.1397561851 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 9309870602 ps |
CPU time | 41.15 seconds |
Started | Feb 08 08:47:45 AM UTC 25 |
Finished | Feb 08 08:48:28 AM UTC 25 |
Peak memory | 212628 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397561851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1397561851 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.128073756 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 36716569 ps |
CPU time | 4.47 seconds |
Started | Feb 08 08:47:43 AM UTC 25 |
Finished | Feb 08 08:47:49 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128073756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.128073756 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.701267749 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 796017511 ps |
CPU time | 9.56 seconds |
Started | Feb 08 08:47:46 AM UTC 25 |
Finished | Feb 08 08:47:58 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701267749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.701267749 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.3149544645 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 100705355 ps |
CPU time | 1.95 seconds |
Started | Feb 08 08:47:41 AM UTC 25 |
Finished | Feb 08 08:47:45 AM UTC 25 |
Peak memory | 211412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149544645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3149544645 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2998171376 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 1567494072 ps |
CPU time | 10.19 seconds |
Started | Feb 08 08:47:43 AM UTC 25 |
Finished | Feb 08 08:47:55 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998171376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2998171376 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3221705444 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 827230446 ps |
CPU time | 7.5 seconds |
Started | Feb 08 08:47:43 AM UTC 25 |
Finished | Feb 08 08:47:52 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221705444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3221705444 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.1252264164 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 8667953 ps |
CPU time | 1.44 seconds |
Started | Feb 08 08:47:41 AM UTC 25 |
Finished | Feb 08 08:47:44 AM UTC 25 |
Peak memory | 211320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252264164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.1252264164 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2943561827 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 2590468432 ps |
CPU time | 34.85 seconds |
Started | Feb 08 08:47:50 AM UTC 25 |
Finished | Feb 08 08:48:27 AM UTC 25 |
Peak memory | 214320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943561827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2943561827 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.208683099 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 6343395987 ps |
CPU time | 43.81 seconds |
Started | Feb 08 08:47:51 AM UTC 25 |
Finished | Feb 08 08:48:37 AM UTC 25 |
Peak memory | 214404 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208683099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.208683099 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.1532088650 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 133565672 ps |
CPU time | 15.09 seconds |
Started | Feb 08 08:47:50 AM UTC 25 |
Finished | Feb 08 08:48:07 AM UTC 25 |
Peak memory | 214120 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532088650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.1532088650 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.545160189 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 2284930377 ps |
CPU time | 73.12 seconds |
Started | Feb 08 08:47:52 AM UTC 25 |
Finished | Feb 08 08:49:08 AM UTC 25 |
Peak memory | 214444 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545160189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.545160189 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.1757883518 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 545120574 ps |
CPU time | 8.7 seconds |
Started | Feb 08 08:47:49 AM UTC 25 |
Finished | Feb 08 08:47:59 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757883518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1757883518 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.1194173289 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 119766519 ps |
CPU time | 12.37 seconds |
Started | Feb 08 08:47:57 AM UTC 25 |
Finished | Feb 08 08:48:11 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194173289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.1194173289 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.4036960352 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 222577199334 ps |
CPU time | 312.82 seconds |
Started | Feb 08 08:47:57 AM UTC 25 |
Finished | Feb 08 08:53:14 AM UTC 25 |
Peak memory | 218124 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036960352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.4036960352 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.4032764938 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 487383584 ps |
CPU time | 10.82 seconds |
Started | Feb 08 08:47:59 AM UTC 25 |
Finished | Feb 08 08:48:12 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032764938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.4032764938 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.1915701364 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 825720423 ps |
CPU time | 13.59 seconds |
Started | Feb 08 08:47:58 AM UTC 25 |
Finished | Feb 08 08:48:13 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915701364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.1915701364 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.1195372460 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 114510195 ps |
CPU time | 5.02 seconds |
Started | Feb 08 08:47:55 AM UTC 25 |
Finished | Feb 08 08:48:02 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195372460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1195372460 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.2138428566 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 21687552708 ps |
CPU time | 94.33 seconds |
Started | Feb 08 08:47:57 AM UTC 25 |
Finished | Feb 08 08:49:33 AM UTC 25 |
Peak memory | 212032 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138428566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2138428566 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.585039114 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 1558922260 ps |
CPU time | 16.1 seconds |
Started | Feb 08 08:47:57 AM UTC 25 |
Finished | Feb 08 08:48:14 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585039114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.585039114 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2077489204 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 85745603 ps |
CPU time | 8.44 seconds |
Started | Feb 08 08:47:56 AM UTC 25 |
Finished | Feb 08 08:48:07 AM UTC 25 |
Peak memory | 212052 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077489204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2077489204 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.3899556312 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 47225286 ps |
CPU time | 4.99 seconds |
Started | Feb 08 08:47:57 AM UTC 25 |
Finished | Feb 08 08:48:03 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899556312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3899556312 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.2584888155 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 279993774 ps |
CPU time | 1.94 seconds |
Started | Feb 08 08:47:53 AM UTC 25 |
Finished | Feb 08 08:47:56 AM UTC 25 |
Peak memory | 211360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584888155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2584888155 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.2485133416 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 1760890767 ps |
CPU time | 8.79 seconds |
Started | Feb 08 08:47:54 AM UTC 25 |
Finished | Feb 08 08:48:04 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485133416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2485133416 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.1832357605 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 774485824 ps |
CPU time | 8.26 seconds |
Started | Feb 08 08:47:55 AM UTC 25 |
Finished | Feb 08 08:48:05 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832357605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1832357605 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.4117592490 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 11836191 ps |
CPU time | 1.14 seconds |
Started | Feb 08 08:47:53 AM UTC 25 |
Finished | Feb 08 08:47:55 AM UTC 25 |
Peak memory | 211320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117592490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.4117592490 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.334400237 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 5753590504 ps |
CPU time | 63.36 seconds |
Started | Feb 08 08:47:59 AM UTC 25 |
Finished | Feb 08 08:49:05 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334400237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.334400237 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.637922748 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 6418330669 ps |
CPU time | 39.5 seconds |
Started | Feb 08 08:48:01 AM UTC 25 |
Finished | Feb 08 08:48:43 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637922748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.637922748 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.335707693 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 901226098 ps |
CPU time | 81.74 seconds |
Started | Feb 08 08:48:00 AM UTC 25 |
Finished | Feb 08 08:49:24 AM UTC 25 |
Peak memory | 216532 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335707693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.335707693 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.4007161166 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 1249144320 ps |
CPU time | 27.83 seconds |
Started | Feb 08 08:48:03 AM UTC 25 |
Finished | Feb 08 08:48:32 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007161166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.4007161166 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.2506789356 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 197017570 ps |
CPU time | 5.84 seconds |
Started | Feb 08 08:47:58 AM UTC 25 |
Finished | Feb 08 08:48:05 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506789356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.2506789356 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.2925390474 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 56019569 ps |
CPU time | 10.26 seconds |
Started | Feb 08 08:48:08 AM UTC 25 |
Finished | Feb 08 08:48:20 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925390474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.2925390474 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.4118577402 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 7857479791 ps |
CPU time | 37.83 seconds |
Started | Feb 08 08:48:08 AM UTC 25 |
Finished | Feb 08 08:48:48 AM UTC 25 |
Peak memory | 211716 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118577402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.4118577402 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.2415536837 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 148116003 ps |
CPU time | 3.14 seconds |
Started | Feb 08 08:48:11 AM UTC 25 |
Finished | Feb 08 08:48:17 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415536837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.2415536837 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.3722615808 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 50757718 ps |
CPU time | 4.01 seconds |
Started | Feb 08 08:48:08 AM UTC 25 |
Finished | Feb 08 08:48:14 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722615808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.3722615808 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.3989990602 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 74287593 ps |
CPU time | 5.32 seconds |
Started | Feb 08 08:48:06 AM UTC 25 |
Finished | Feb 08 08:48:13 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989990602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3989990602 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.2923882481 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 9327527478 ps |
CPU time | 56.83 seconds |
Started | Feb 08 08:48:07 AM UTC 25 |
Finished | Feb 08 08:49:05 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923882481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2923882481 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1685836122 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 29420300584 ps |
CPU time | 189.24 seconds |
Started | Feb 08 08:48:08 AM UTC 25 |
Finished | Feb 08 08:51:21 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685836122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1685836122 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.4280535654 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 205392688 ps |
CPU time | 5.69 seconds |
Started | Feb 08 08:48:06 AM UTC 25 |
Finished | Feb 08 08:48:14 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280535654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.4280535654 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.725010861 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 110438215 ps |
CPU time | 3.3 seconds |
Started | Feb 08 08:48:08 AM UTC 25 |
Finished | Feb 08 08:48:13 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725010861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.725010861 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.2960281105 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 10841388 ps |
CPU time | 1.59 seconds |
Started | Feb 08 08:48:04 AM UTC 25 |
Finished | Feb 08 08:48:07 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960281105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2960281105 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.52933506 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 1778698012 ps |
CPU time | 12.31 seconds |
Started | Feb 08 08:48:04 AM UTC 25 |
Finished | Feb 08 08:48:18 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52933506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.52933506 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1093816177 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 1774395740 ps |
CPU time | 15.53 seconds |
Started | Feb 08 08:48:05 AM UTC 25 |
Finished | Feb 08 08:48:23 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093816177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1093816177 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.3570089641 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 9946088 ps |
CPU time | 1.53 seconds |
Started | Feb 08 08:48:04 AM UTC 25 |
Finished | Feb 08 08:48:07 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570089641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.3570089641 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.2699038285 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 340403603 ps |
CPU time | 18.14 seconds |
Started | Feb 08 08:48:13 AM UTC 25 |
Finished | Feb 08 08:48:33 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699038285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2699038285 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.3513648100 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 5632711447 ps |
CPU time | 54.47 seconds |
Started | Feb 08 08:48:16 AM UTC 25 |
Finished | Feb 08 08:49:12 AM UTC 25 |
Peak memory | 212252 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513648100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3513648100 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.3138573757 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 981345764 ps |
CPU time | 19.19 seconds |
Started | Feb 08 08:48:14 AM UTC 25 |
Finished | Feb 08 08:48:35 AM UTC 25 |
Peak memory | 214356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138573757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.3138573757 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2479662589 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 400821939 ps |
CPU time | 78.56 seconds |
Started | Feb 08 08:48:16 AM UTC 25 |
Finished | Feb 08 08:49:37 AM UTC 25 |
Peak memory | 214320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479662589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2479662589 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.2894636342 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 680388520 ps |
CPU time | 16.29 seconds |
Started | Feb 08 08:48:10 AM UTC 25 |
Finished | Feb 08 08:48:28 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894636342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2894636342 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.2108394607 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 12797840 ps |
CPU time | 3.36 seconds |
Started | Feb 08 08:42:41 AM UTC 25 |
Finished | Feb 08 08:42:46 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108394607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2108394607 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.3279791818 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 20173670366 ps |
CPU time | 211.77 seconds |
Started | Feb 08 08:42:41 AM UTC 25 |
Finished | Feb 08 08:46:17 AM UTC 25 |
Peak memory | 212436 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279791818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.3279791818 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.3079888091 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 920200832 ps |
CPU time | 10.79 seconds |
Started | Feb 08 08:42:43 AM UTC 25 |
Finished | Feb 08 08:42:56 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079888091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.3079888091 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.1782760381 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 50161966 ps |
CPU time | 4.78 seconds |
Started | Feb 08 08:42:41 AM UTC 25 |
Finished | Feb 08 08:42:48 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782760381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.1782760381 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.202112101 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 709529220 ps |
CPU time | 7.35 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:48 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202112101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.202112101 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.1241453302 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 68670939982 ps |
CPU time | 246.26 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:46:49 AM UTC 25 |
Peak memory | 214212 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241453302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1241453302 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2235363373 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 28600601158 ps |
CPU time | 82.77 seconds |
Started | Feb 08 08:42:39 AM UTC 25 |
Finished | Feb 08 08:44:04 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235363373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2235363373 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.3846659527 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 11109468 ps |
CPU time | 1.78 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:42 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846659527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.3846659527 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.1325713365 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 1008019553 ps |
CPU time | 13.46 seconds |
Started | Feb 08 08:42:41 AM UTC 25 |
Finished | Feb 08 08:42:57 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325713365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1325713365 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.2639819222 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 9341807 ps |
CPU time | 1.46 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:42 AM UTC 25 |
Peak memory | 211324 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639819222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2639819222 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.263995593 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 3543399232 ps |
CPU time | 10.41 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:51 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263995593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.263995593 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.2227940622 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 2038960832 ps |
CPU time | 12.7 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:53 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227940622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2227940622 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.1086369584 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 40426429 ps |
CPU time | 1.67 seconds |
Started | Feb 08 08:42:38 AM UTC 25 |
Finished | Feb 08 08:42:42 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086369584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.1086369584 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.2753069561 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 8219056409 ps |
CPU time | 118.93 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:44:46 AM UTC 25 |
Peak memory | 216660 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753069561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2753069561 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2842829737 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 61344115 ps |
CPU time | 5.9 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:42:51 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842829737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2842829737 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.3019750908 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 4561484415 ps |
CPU time | 167.17 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:45:35 AM UTC 25 |
Peak memory | 218508 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019750908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.3019750908 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.2950963102 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 368764845 ps |
CPU time | 67.78 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:43:54 AM UTC 25 |
Peak memory | 216600 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950963102 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.2950963102 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.1170285110 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 59282958 ps |
CPU time | 6.42 seconds |
Started | Feb 08 08:42:43 AM UTC 25 |
Finished | Feb 08 08:42:52 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170285110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.1170285110 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.3315955160 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 1001756886 ps |
CPU time | 15.16 seconds |
Started | Feb 08 08:48:20 AM UTC 25 |
Finished | Feb 08 08:48:37 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315955160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.3315955160 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.3617492274 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 59841472819 ps |
CPU time | 384.7 seconds |
Started | Feb 08 08:48:20 AM UTC 25 |
Finished | Feb 08 08:54:50 AM UTC 25 |
Peak memory | 218380 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617492274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.3617492274 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.3355921795 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 17596463 ps |
CPU time | 2.14 seconds |
Started | Feb 08 08:48:22 AM UTC 25 |
Finished | Feb 08 08:48:26 AM UTC 25 |
Peak memory | 212552 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355921795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.3355921795 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.3176661035 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 511052128 ps |
CPU time | 10.53 seconds |
Started | Feb 08 08:48:21 AM UTC 25 |
Finished | Feb 08 08:48:34 AM UTC 25 |
Peak memory | 212436 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176661035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3176661035 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.4068059639 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 53489589 ps |
CPU time | 3.26 seconds |
Started | Feb 08 08:48:16 AM UTC 25 |
Finished | Feb 08 08:48:21 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068059639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.4068059639 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.3163025143 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 46791131684 ps |
CPU time | 102.9 seconds |
Started | Feb 08 08:48:17 AM UTC 25 |
Finished | Feb 08 08:50:03 AM UTC 25 |
Peak memory | 212284 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163025143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.3163025143 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.3986993069 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 12807408731 ps |
CPU time | 67.45 seconds |
Started | Feb 08 08:48:17 AM UTC 25 |
Finished | Feb 08 08:49:27 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986993069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3986993069 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.4026727773 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 32945500 ps |
CPU time | 6.46 seconds |
Started | Feb 08 08:48:17 AM UTC 25 |
Finished | Feb 08 08:48:26 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026727773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.4026727773 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.3222756790 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 81564165 ps |
CPU time | 5.79 seconds |
Started | Feb 08 08:48:20 AM UTC 25 |
Finished | Feb 08 08:48:27 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222756790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3222756790 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.1642137826 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 50830326 ps |
CPU time | 1.71 seconds |
Started | Feb 08 08:48:16 AM UTC 25 |
Finished | Feb 08 08:48:19 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642137826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1642137826 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.941067698 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 2055197800 ps |
CPU time | 10.23 seconds |
Started | Feb 08 08:48:16 AM UTC 25 |
Finished | Feb 08 08:48:28 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941067698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.941067698 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2914998924 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 929142932 ps |
CPU time | 9.1 seconds |
Started | Feb 08 08:48:16 AM UTC 25 |
Finished | Feb 08 08:48:27 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914998924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2914998924 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.2080318794 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 24409021 ps |
CPU time | 1.4 seconds |
Started | Feb 08 08:48:16 AM UTC 25 |
Finished | Feb 08 08:48:19 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080318794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.2080318794 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.2028256093 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 1001037230 ps |
CPU time | 24.76 seconds |
Started | Feb 08 08:48:23 AM UTC 25 |
Finished | Feb 08 08:48:51 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028256093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2028256093 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.3673277004 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 5445328439 ps |
CPU time | 69.85 seconds |
Started | Feb 08 08:48:28 AM UTC 25 |
Finished | Feb 08 08:49:41 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673277004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3673277004 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4276698591 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 327392654 ps |
CPU time | 48.28 seconds |
Started | Feb 08 08:48:27 AM UTC 25 |
Finished | Feb 08 08:49:18 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276698591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.4276698591 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.4209580068 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 46692840 ps |
CPU time | 8.08 seconds |
Started | Feb 08 08:48:28 AM UTC 25 |
Finished | Feb 08 08:48:38 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209580068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.4209580068 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.2950472583 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 509056346 ps |
CPU time | 11.88 seconds |
Started | Feb 08 08:48:21 AM UTC 25 |
Finished | Feb 08 08:48:35 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950472583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2950472583 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.3819066094 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 88614042 ps |
CPU time | 6 seconds |
Started | Feb 08 08:48:33 AM UTC 25 |
Finished | Feb 08 08:48:41 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819066094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.3819066094 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.3074832375 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 88489401557 ps |
CPU time | 399.35 seconds |
Started | Feb 08 08:48:34 AM UTC 25 |
Finished | Feb 08 08:55:19 AM UTC 25 |
Peak memory | 217996 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074832375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.3074832375 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1303786573 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 762363211 ps |
CPU time | 10.55 seconds |
Started | Feb 08 08:48:36 AM UTC 25 |
Finished | Feb 08 08:48:48 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303786573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1303786573 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.131841768 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 56189286 ps |
CPU time | 6.18 seconds |
Started | Feb 08 08:48:34 AM UTC 25 |
Finished | Feb 08 08:48:42 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131841768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.131841768 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.3861956758 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 2574626223 ps |
CPU time | 17.95 seconds |
Started | Feb 08 08:48:29 AM UTC 25 |
Finished | Feb 08 08:48:49 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861956758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.3861956758 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.243738512 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 20181593256 ps |
CPU time | 87.88 seconds |
Started | Feb 08 08:48:31 AM UTC 25 |
Finished | Feb 08 08:50:01 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243738512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.243738512 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.78924532 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 12351883423 ps |
CPU time | 54.86 seconds |
Started | Feb 08 08:48:33 AM UTC 25 |
Finished | Feb 08 08:49:30 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78924532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_ SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.78924532 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.6224503 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 54771776 ps |
CPU time | 6.55 seconds |
Started | Feb 08 08:48:29 AM UTC 25 |
Finished | Feb 08 08:48:38 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6224503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.6224503 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.1232507177 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 2316807344 ps |
CPU time | 13.91 seconds |
Started | Feb 08 08:48:34 AM UTC 25 |
Finished | Feb 08 08:48:50 AM UTC 25 |
Peak memory | 212460 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232507177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1232507177 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.758579063 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 254438847 ps |
CPU time | 2.43 seconds |
Started | Feb 08 08:48:28 AM UTC 25 |
Finished | Feb 08 08:48:33 AM UTC 25 |
Peak memory | 212292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758579063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.758579063 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.70062782 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 7088571247 ps |
CPU time | 12.29 seconds |
Started | Feb 08 08:48:29 AM UTC 25 |
Finished | Feb 08 08:48:44 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70062782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.70062782 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.4241982555 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1536280568 ps |
CPU time | 12.86 seconds |
Started | Feb 08 08:48:29 AM UTC 25 |
Finished | Feb 08 08:48:44 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241982555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.4241982555 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3005088565 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 38149497 ps |
CPU time | 1.66 seconds |
Started | Feb 08 08:48:28 AM UTC 25 |
Finished | Feb 08 08:48:32 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005088565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3005088565 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3596437087 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 2135925430 ps |
CPU time | 29.06 seconds |
Started | Feb 08 08:48:38 AM UTC 25 |
Finished | Feb 08 08:49:09 AM UTC 25 |
Peak memory | 211960 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596437087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3596437087 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.491015749 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 5093923581 ps |
CPU time | 51.67 seconds |
Started | Feb 08 08:48:39 AM UTC 25 |
Finished | Feb 08 08:49:33 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491015749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.491015749 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.270478640 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 156899604 ps |
CPU time | 28.05 seconds |
Started | Feb 08 08:48:38 AM UTC 25 |
Finished | Feb 08 08:49:08 AM UTC 25 |
Peak memory | 214068 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270478640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.270478640 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.531558143 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 319079995 ps |
CPU time | 31.96 seconds |
Started | Feb 08 08:48:39 AM UTC 25 |
Finished | Feb 08 08:49:13 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531558143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.531558143 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.3844267337 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 456353601 ps |
CPU time | 3.24 seconds |
Started | Feb 08 08:48:35 AM UTC 25 |
Finished | Feb 08 08:48:40 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844267337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3844267337 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.2015458856 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 49224979 ps |
CPU time | 3.82 seconds |
Started | Feb 08 08:48:45 AM UTC 25 |
Finished | Feb 08 08:48:51 AM UTC 25 |
Peak memory | 211160 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015458856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.2015458856 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1652006509 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 19564849703 ps |
CPU time | 173.55 seconds |
Started | Feb 08 08:48:45 AM UTC 25 |
Finished | Feb 08 08:51:43 AM UTC 25 |
Peak memory | 214544 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652006509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1652006509 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.2449275280 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 454290211 ps |
CPU time | 7.39 seconds |
Started | Feb 08 08:48:49 AM UTC 25 |
Finished | Feb 08 08:48:58 AM UTC 25 |
Peak memory | 212288 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449275280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.2449275280 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.2583843407 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 1454782036 ps |
CPU time | 13.65 seconds |
Started | Feb 08 08:48:48 AM UTC 25 |
Finished | Feb 08 08:49:03 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583843407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2583843407 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.3735739504 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 75287856 ps |
CPU time | 2.87 seconds |
Started | Feb 08 08:48:44 AM UTC 25 |
Finished | Feb 08 08:48:48 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735739504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3735739504 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.712167308 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 44290656138 ps |
CPU time | 163.52 seconds |
Started | Feb 08 08:48:44 AM UTC 25 |
Finished | Feb 08 08:51:31 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712167308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.712167308 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.3736092749 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 42264681562 ps |
CPU time | 95.36 seconds |
Started | Feb 08 08:48:44 AM UTC 25 |
Finished | Feb 08 08:50:22 AM UTC 25 |
Peak memory | 212328 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736092749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3736092749 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.884311166 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 104710231 ps |
CPU time | 7.17 seconds |
Started | Feb 08 08:48:44 AM UTC 25 |
Finished | Feb 08 08:48:53 AM UTC 25 |
Peak memory | 212244 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884311166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.884311166 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.1389427565 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 163020367 ps |
CPU time | 5.93 seconds |
Started | Feb 08 08:48:46 AM UTC 25 |
Finished | Feb 08 08:48:53 AM UTC 25 |
Peak memory | 211372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389427565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1389427565 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3236670479 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 161124473 ps |
CPU time | 1.99 seconds |
Started | Feb 08 08:48:39 AM UTC 25 |
Finished | Feb 08 08:48:43 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236670479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3236670479 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.1117701849 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 7442547248 ps |
CPU time | 18.32 seconds |
Started | Feb 08 08:48:42 AM UTC 25 |
Finished | Feb 08 08:49:02 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117701849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1117701849 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.3026089017 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 1170638801 ps |
CPU time | 10.33 seconds |
Started | Feb 08 08:48:42 AM UTC 25 |
Finished | Feb 08 08:48:54 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026089017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3026089017 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.4280217081 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 8883272 ps |
CPU time | 1.66 seconds |
Started | Feb 08 08:48:39 AM UTC 25 |
Finished | Feb 08 08:48:43 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280217081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.4280217081 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.3616654425 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 194676832 ps |
CPU time | 22.9 seconds |
Started | Feb 08 08:48:49 AM UTC 25 |
Finished | Feb 08 08:49:14 AM UTC 25 |
Peak memory | 214348 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616654425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3616654425 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.4106395690 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 12732827897 ps |
CPU time | 38.57 seconds |
Started | Feb 08 08:48:51 AM UTC 25 |
Finished | Feb 08 08:49:32 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106395690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.4106395690 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.3535079706 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 7784161445 ps |
CPU time | 98.65 seconds |
Started | Feb 08 08:48:50 AM UTC 25 |
Finished | Feb 08 08:50:32 AM UTC 25 |
Peak memory | 216464 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535079706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.3535079706 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4068653639 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 3224558092 ps |
CPU time | 90.43 seconds |
Started | Feb 08 08:48:53 AM UTC 25 |
Finished | Feb 08 08:50:26 AM UTC 25 |
Peak memory | 216456 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068653639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.4068653639 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.448133310 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 245954519 ps |
CPU time | 7.15 seconds |
Started | Feb 08 08:48:49 AM UTC 25 |
Finished | Feb 08 08:48:58 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448133310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.448133310 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.1588782273 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 2633144838 ps |
CPU time | 20.77 seconds |
Started | Feb 08 08:49:00 AM UTC 25 |
Finished | Feb 08 08:49:23 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588782273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.1588782273 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.1243814011 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 48034443859 ps |
CPU time | 406.46 seconds |
Started | Feb 08 08:49:00 AM UTC 25 |
Finished | Feb 08 08:55:52 AM UTC 25 |
Peak memory | 216000 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243814011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.1243814011 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.1471331687 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 450505371 ps |
CPU time | 5.16 seconds |
Started | Feb 08 08:49:04 AM UTC 25 |
Finished | Feb 08 08:49:12 AM UTC 25 |
Peak memory | 212356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471331687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.1471331687 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3191846879 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 2000007611 ps |
CPU time | 12.16 seconds |
Started | Feb 08 08:49:02 AM UTC 25 |
Finished | Feb 08 08:49:16 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191846879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3191846879 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.4202125905 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 552212169 ps |
CPU time | 6.99 seconds |
Started | Feb 08 08:48:55 AM UTC 25 |
Finished | Feb 08 08:49:04 AM UTC 25 |
Peak memory | 212016 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202125905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.4202125905 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.1922191555 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 135424849892 ps |
CPU time | 114.52 seconds |
Started | Feb 08 08:48:58 AM UTC 25 |
Finished | Feb 08 08:50:56 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922191555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1922191555 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.1827190531 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 67071363561 ps |
CPU time | 95.83 seconds |
Started | Feb 08 08:49:00 AM UTC 25 |
Finished | Feb 08 08:50:39 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827190531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1827190531 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.3206102398 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 28790936 ps |
CPU time | 5.14 seconds |
Started | Feb 08 08:48:57 AM UTC 25 |
Finished | Feb 08 08:49:04 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206102398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.3206102398 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.2213235228 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 26794166 ps |
CPU time | 2.24 seconds |
Started | Feb 08 08:49:00 AM UTC 25 |
Finished | Feb 08 08:49:04 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213235228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2213235228 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.2420166287 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 9633649 ps |
CPU time | 1.64 seconds |
Started | Feb 08 08:48:53 AM UTC 25 |
Finished | Feb 08 08:48:56 AM UTC 25 |
Peak memory | 211416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420166287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2420166287 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4003659828 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 5948675790 ps |
CPU time | 9.57 seconds |
Started | Feb 08 08:48:54 AM UTC 25 |
Finished | Feb 08 08:49:05 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003659828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4003659828 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.1914003956 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 1657766353 ps |
CPU time | 10.46 seconds |
Started | Feb 08 08:48:55 AM UTC 25 |
Finished | Feb 08 08:49:07 AM UTC 25 |
Peak memory | 212220 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914003956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1914003956 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.1239310317 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 16496815 ps |
CPU time | 1.72 seconds |
Started | Feb 08 08:48:54 AM UTC 25 |
Finished | Feb 08 08:48:57 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239310317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.1239310317 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.1096271462 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 3733074286 ps |
CPU time | 58.68 seconds |
Started | Feb 08 08:49:06 AM UTC 25 |
Finished | Feb 08 08:50:07 AM UTC 25 |
Peak memory | 216384 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096271462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1096271462 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.220638425 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 1499695422 ps |
CPU time | 26.49 seconds |
Started | Feb 08 08:49:06 AM UTC 25 |
Finished | Feb 08 08:49:35 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220638425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.220638425 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2467197382 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 262950221 ps |
CPU time | 18.99 seconds |
Started | Feb 08 08:49:06 AM UTC 25 |
Finished | Feb 08 08:49:27 AM UTC 25 |
Peak memory | 214612 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467197382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.2467197382 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.4261449497 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 382338918 ps |
CPU time | 7.43 seconds |
Started | Feb 08 08:49:04 AM UTC 25 |
Finished | Feb 08 08:49:14 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261449497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.4261449497 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.1742838358 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 152100316 ps |
CPU time | 3.26 seconds |
Started | Feb 08 08:49:13 AM UTC 25 |
Finished | Feb 08 08:49:18 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742838358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.1742838358 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.290990370 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 25535791453 ps |
CPU time | 186.3 seconds |
Started | Feb 08 08:49:13 AM UTC 25 |
Finished | Feb 08 08:52:23 AM UTC 25 |
Peak memory | 214612 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290990370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.290990370 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.2740699875 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 493991620 ps |
CPU time | 10.79 seconds |
Started | Feb 08 08:49:16 AM UTC 25 |
Finished | Feb 08 08:49:28 AM UTC 25 |
Peak memory | 212268 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740699875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.2740699875 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.296429546 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 365858361 ps |
CPU time | 6.03 seconds |
Started | Feb 08 08:49:14 AM UTC 25 |
Finished | Feb 08 08:49:22 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296429546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.296429546 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3764097018 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 842511649 ps |
CPU time | 10.47 seconds |
Started | Feb 08 08:49:10 AM UTC 25 |
Finished | Feb 08 08:49:21 AM UTC 25 |
Peak memory | 212116 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764097018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3764097018 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.2292055988 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 4357399881 ps |
CPU time | 22.87 seconds |
Started | Feb 08 08:49:11 AM UTC 25 |
Finished | Feb 08 08:49:35 AM UTC 25 |
Peak memory | 212356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292055988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2292055988 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.331254788 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 50416696090 ps |
CPU time | 121.83 seconds |
Started | Feb 08 08:49:12 AM UTC 25 |
Finished | Feb 08 08:51:17 AM UTC 25 |
Peak memory | 212632 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331254788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.331254788 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.3360880285 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 57590064 ps |
CPU time | 8.11 seconds |
Started | Feb 08 08:49:10 AM UTC 25 |
Finished | Feb 08 08:49:19 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360880285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.3360880285 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.4058886221 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 221675053 ps |
CPU time | 5.43 seconds |
Started | Feb 08 08:49:14 AM UTC 25 |
Finished | Feb 08 08:49:22 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058886221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.4058886221 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.133487180 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 9631738 ps |
CPU time | 1.54 seconds |
Started | Feb 08 08:49:07 AM UTC 25 |
Finished | Feb 08 08:49:10 AM UTC 25 |
Peak memory | 211364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133487180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.133487180 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.1405099282 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 1542984758 ps |
CPU time | 11.48 seconds |
Started | Feb 08 08:49:08 AM UTC 25 |
Finished | Feb 08 08:49:21 AM UTC 25 |
Peak memory | 212108 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405099282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.1405099282 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.1056350724 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 2116137946 ps |
CPU time | 22.63 seconds |
Started | Feb 08 08:49:10 AM UTC 25 |
Finished | Feb 08 08:49:34 AM UTC 25 |
Peak memory | 212356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056350724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1056350724 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.3744793952 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 9241711 ps |
CPU time | 1.52 seconds |
Started | Feb 08 08:49:08 AM UTC 25 |
Finished | Feb 08 08:49:11 AM UTC 25 |
Peak memory | 211216 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744793952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.3744793952 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.1329606143 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 6276391 ps |
CPU time | 1.14 seconds |
Started | Feb 08 08:49:16 AM UTC 25 |
Finished | Feb 08 08:49:18 AM UTC 25 |
Peak memory | 202568 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329606143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1329606143 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.2528535882 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 210439562 ps |
CPU time | 16.24 seconds |
Started | Feb 08 08:49:18 AM UTC 25 |
Finished | Feb 08 08:49:36 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528535882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2528535882 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.414541715 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 489381815 ps |
CPU time | 89.98 seconds |
Started | Feb 08 08:49:18 AM UTC 25 |
Finished | Feb 08 08:50:50 AM UTC 25 |
Peak memory | 216400 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414541715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.414541715 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.3035759308 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 2630277191 ps |
CPU time | 87.78 seconds |
Started | Feb 08 08:49:19 AM UTC 25 |
Finished | Feb 08 08:50:50 AM UTC 25 |
Peak memory | 216456 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035759308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.3035759308 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.3050084573 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 381757184 ps |
CPU time | 6.15 seconds |
Started | Feb 08 08:49:16 AM UTC 25 |
Finished | Feb 08 08:49:24 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050084573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3050084573 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.2360687012 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 51094016 ps |
CPU time | 10.37 seconds |
Started | Feb 08 08:49:23 AM UTC 25 |
Finished | Feb 08 08:49:35 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360687012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.2360687012 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1308091532 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 65799191453 ps |
CPU time | 121.98 seconds |
Started | Feb 08 08:49:25 AM UTC 25 |
Finished | Feb 08 08:51:29 AM UTC 25 |
Peak memory | 212472 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308091532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.1308091532 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.1584381772 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 248360990 ps |
CPU time | 6.85 seconds |
Started | Feb 08 08:49:25 AM UTC 25 |
Finished | Feb 08 08:49:33 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584381772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.1584381772 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.953025206 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 638305403 ps |
CPU time | 4.53 seconds |
Started | Feb 08 08:49:25 AM UTC 25 |
Finished | Feb 08 08:49:31 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953025206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.953025206 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.385216786 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 744224608 ps |
CPU time | 15.13 seconds |
Started | Feb 08 08:49:22 AM UTC 25 |
Finished | Feb 08 08:49:39 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385216786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.385216786 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.3617632402 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 39298999515 ps |
CPU time | 99.6 seconds |
Started | Feb 08 08:49:23 AM UTC 25 |
Finished | Feb 08 08:51:05 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617632402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3617632402 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.1822428441 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 85159750963 ps |
CPU time | 107.47 seconds |
Started | Feb 08 08:49:23 AM UTC 25 |
Finished | Feb 08 08:51:13 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822428441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.1822428441 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.3258468108 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 42277720 ps |
CPU time | 5.27 seconds |
Started | Feb 08 08:49:23 AM UTC 25 |
Finished | Feb 08 08:49:30 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258468108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.3258468108 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.544042084 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 549358331 ps |
CPU time | 6.01 seconds |
Started | Feb 08 08:49:25 AM UTC 25 |
Finished | Feb 08 08:49:32 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544042084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.544042084 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.3809530322 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 10948937 ps |
CPU time | 1.76 seconds |
Started | Feb 08 08:49:19 AM UTC 25 |
Finished | Feb 08 08:49:23 AM UTC 25 |
Peak memory | 211416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809530322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3809530322 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.1442085859 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 3697091783 ps |
CPU time | 9.84 seconds |
Started | Feb 08 08:49:21 AM UTC 25 |
Finished | Feb 08 08:49:32 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442085859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1442085859 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.3890066563 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 977787579 ps |
CPU time | 9.43 seconds |
Started | Feb 08 08:49:21 AM UTC 25 |
Finished | Feb 08 08:49:32 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890066563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.3890066563 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.49665519 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 8993922 ps |
CPU time | 1.7 seconds |
Started | Feb 08 08:49:19 AM UTC 25 |
Finished | Feb 08 08:49:23 AM UTC 25 |
Peak memory | 211288 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49665519 -assert nopostproc +UVM_TESTNAME=xbar_base_test + UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.49665519 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.2845578735 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 239487418 ps |
CPU time | 22.35 seconds |
Started | Feb 08 08:49:26 AM UTC 25 |
Finished | Feb 08 08:49:50 AM UTC 25 |
Peak memory | 214348 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845578735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2845578735 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.3422209383 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 25613124396 ps |
CPU time | 56.6 seconds |
Started | Feb 08 08:49:28 AM UTC 25 |
Finished | Feb 08 08:50:27 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422209383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3422209383 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1576817939 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1388887043 ps |
CPU time | 89.73 seconds |
Started | Feb 08 08:49:28 AM UTC 25 |
Finished | Feb 08 08:51:00 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576817939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1576817939 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.3777871473 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 232733615 ps |
CPU time | 35.41 seconds |
Started | Feb 08 08:49:29 AM UTC 25 |
Finished | Feb 08 08:50:07 AM UTC 25 |
Peak memory | 214348 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777871473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.3777871473 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.831939696 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 14005458 ps |
CPU time | 2.21 seconds |
Started | Feb 08 08:49:25 AM UTC 25 |
Finished | Feb 08 08:49:29 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831939696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.831939696 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.2999621712 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 63636432 ps |
CPU time | 10.62 seconds |
Started | Feb 08 08:49:33 AM UTC 25 |
Finished | Feb 08 08:49:46 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999621712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.2999621712 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.3501689263 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 38035203063 ps |
CPU time | 245.1 seconds |
Started | Feb 08 08:49:35 AM UTC 25 |
Finished | Feb 08 08:53:44 AM UTC 25 |
Peak memory | 214608 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501689263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.3501689263 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.1512703826 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 1256248653 ps |
CPU time | 10.25 seconds |
Started | Feb 08 08:49:35 AM UTC 25 |
Finished | Feb 08 08:49:47 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512703826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.1512703826 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.3357511557 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 1305913668 ps |
CPU time | 15.66 seconds |
Started | Feb 08 08:49:35 AM UTC 25 |
Finished | Feb 08 08:49:53 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357511557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.3357511557 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.2166043492 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 36998265 ps |
CPU time | 2.12 seconds |
Started | Feb 08 08:49:33 AM UTC 25 |
Finished | Feb 08 08:49:37 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166043492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.2166043492 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.392515359 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 16224061243 ps |
CPU time | 59.88 seconds |
Started | Feb 08 08:49:33 AM UTC 25 |
Finished | Feb 08 08:50:35 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392515359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.392515359 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.341795756 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 47893806960 ps |
CPU time | 153.7 seconds |
Started | Feb 08 08:49:33 AM UTC 25 |
Finished | Feb 08 08:52:10 AM UTC 25 |
Peak memory | 212376 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341795756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.341795756 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.3008952267 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 130491113 ps |
CPU time | 6.61 seconds |
Started | Feb 08 08:49:33 AM UTC 25 |
Finished | Feb 08 08:49:41 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008952267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.3008952267 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.2681158003 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 20820494 ps |
CPU time | 2.5 seconds |
Started | Feb 08 08:49:35 AM UTC 25 |
Finished | Feb 08 08:49:39 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681158003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2681158003 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.27488399 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 275978822 ps |
CPU time | 2.38 seconds |
Started | Feb 08 08:49:29 AM UTC 25 |
Finished | Feb 08 08:49:33 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27488399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_m ode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.27488399 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.1363087749 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 10329775102 ps |
CPU time | 12.31 seconds |
Started | Feb 08 08:49:31 AM UTC 25 |
Finished | Feb 08 08:49:45 AM UTC 25 |
Peak memory | 212404 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363087749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1363087749 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.4130160924 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 4294085430 ps |
CPU time | 7.72 seconds |
Started | Feb 08 08:49:32 AM UTC 25 |
Finished | Feb 08 08:49:41 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130160924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.4130160924 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.3212415394 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 10306848 ps |
CPU time | 1.31 seconds |
Started | Feb 08 08:49:31 AM UTC 25 |
Finished | Feb 08 08:49:33 AM UTC 25 |
Peak memory | 211080 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212415394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.3212415394 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.2194260910 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 719045585 ps |
CPU time | 47.52 seconds |
Started | Feb 08 08:49:35 AM UTC 25 |
Finished | Feb 08 08:50:25 AM UTC 25 |
Peak memory | 214348 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194260910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2194260910 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.2755918243 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 4077898454 ps |
CPU time | 62.42 seconds |
Started | Feb 08 08:49:37 AM UTC 25 |
Finished | Feb 08 08:50:42 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755918243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.2755918243 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.3670608786 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 738806818 ps |
CPU time | 105.14 seconds |
Started | Feb 08 08:49:37 AM UTC 25 |
Finished | Feb 08 08:51:25 AM UTC 25 |
Peak memory | 218320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670608786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.3670608786 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.2466376609 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 68371868 ps |
CPU time | 7.6 seconds |
Started | Feb 08 08:49:35 AM UTC 25 |
Finished | Feb 08 08:49:44 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466376609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2466376609 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.3246628452 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 165432099 ps |
CPU time | 11.61 seconds |
Started | Feb 08 08:49:43 AM UTC 25 |
Finished | Feb 08 08:49:56 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246628452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.3246628452 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.819344140 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 34666612872 ps |
CPU time | 115.3 seconds |
Started | Feb 08 08:49:43 AM UTC 25 |
Finished | Feb 08 08:51:40 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819344140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.819344140 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.1942114421 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 42331432 ps |
CPU time | 5.58 seconds |
Started | Feb 08 08:49:44 AM UTC 25 |
Finished | Feb 08 08:49:51 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942114421 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.1942114421 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.832098782 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 587680205 ps |
CPU time | 7.74 seconds |
Started | Feb 08 08:49:43 AM UTC 25 |
Finished | Feb 08 08:49:52 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832098782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.832098782 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.3812739441 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 135712615 ps |
CPU time | 8.3 seconds |
Started | Feb 08 08:49:39 AM UTC 25 |
Finished | Feb 08 08:49:49 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812739441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.3812739441 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.2951871205 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 19987970910 ps |
CPU time | 13.5 seconds |
Started | Feb 08 08:49:40 AM UTC 25 |
Finished | Feb 08 08:49:56 AM UTC 25 |
Peak memory | 212380 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951871205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2951871205 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3115672388 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 9939494541 ps |
CPU time | 69.82 seconds |
Started | Feb 08 08:49:42 AM UTC 25 |
Finished | Feb 08 08:50:55 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115672388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3115672388 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.3511933021 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 15809799 ps |
CPU time | 2.28 seconds |
Started | Feb 08 08:49:40 AM UTC 25 |
Finished | Feb 08 08:49:44 AM UTC 25 |
Peak memory | 212216 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511933021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.3511933021 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.973966787 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 210706802 ps |
CPU time | 4.71 seconds |
Started | Feb 08 08:49:43 AM UTC 25 |
Finished | Feb 08 08:49:49 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973966787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.973966787 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.3492485091 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 155092087 ps |
CPU time | 1.79 seconds |
Started | Feb 08 08:49:37 AM UTC 25 |
Finished | Feb 08 08:49:41 AM UTC 25 |
Peak memory | 211296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492485091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3492485091 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.3531711391 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 3345765457 ps |
CPU time | 13.46 seconds |
Started | Feb 08 08:49:37 AM UTC 25 |
Finished | Feb 08 08:49:53 AM UTC 25 |
Peak memory | 212332 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531711391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3531711391 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.1238650102 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 3602178451 ps |
CPU time | 14.14 seconds |
Started | Feb 08 08:49:39 AM UTC 25 |
Finished | Feb 08 08:49:55 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238650102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1238650102 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.551993531 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 9968435 ps |
CPU time | 1.86 seconds |
Started | Feb 08 08:49:37 AM UTC 25 |
Finished | Feb 08 08:49:41 AM UTC 25 |
Peak memory | 211304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551993531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.551993531 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.520927130 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 10426564493 ps |
CPU time | 94.81 seconds |
Started | Feb 08 08:49:46 AM UTC 25 |
Finished | Feb 08 08:51:23 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520927130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.520927130 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.2098692348 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 4645501167 ps |
CPU time | 39.72 seconds |
Started | Feb 08 08:49:46 AM UTC 25 |
Finished | Feb 08 08:50:28 AM UTC 25 |
Peak memory | 212260 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098692348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2098692348 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.398776515 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 5735669952 ps |
CPU time | 139.92 seconds |
Started | Feb 08 08:49:46 AM UTC 25 |
Finished | Feb 08 08:52:09 AM UTC 25 |
Peak memory | 218516 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398776515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.398776515 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.623102903 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 192918598 ps |
CPU time | 41.02 seconds |
Started | Feb 08 08:49:46 AM UTC 25 |
Finished | Feb 08 08:50:29 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623102903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.623102903 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.3585029049 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 58987830 ps |
CPU time | 1.3 seconds |
Started | Feb 08 08:49:43 AM UTC 25 |
Finished | Feb 08 08:49:45 AM UTC 25 |
Peak memory | 211424 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585029049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3585029049 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.832705859 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 124872704 ps |
CPU time | 12.04 seconds |
Started | Feb 08 08:49:52 AM UTC 25 |
Finished | Feb 08 08:50:06 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832705859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.832705859 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.4069976296 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 72785308436 ps |
CPU time | 380.54 seconds |
Started | Feb 08 08:49:54 AM UTC 25 |
Finished | Feb 08 08:56:20 AM UTC 25 |
Peak memory | 217720 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069976296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.4069976296 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.1579671998 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 47556342 ps |
CPU time | 5.18 seconds |
Started | Feb 08 08:49:56 AM UTC 25 |
Finished | Feb 08 08:50:03 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579671998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.1579671998 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.2953353367 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 36216863 ps |
CPU time | 3.14 seconds |
Started | Feb 08 08:49:54 AM UTC 25 |
Finished | Feb 08 08:49:59 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953353367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2953353367 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.3833428777 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 29425955 ps |
CPU time | 4.15 seconds |
Started | Feb 08 08:49:50 AM UTC 25 |
Finished | Feb 08 08:49:56 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833428777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.3833428777 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.3454432341 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 11334866574 ps |
CPU time | 22.67 seconds |
Started | Feb 08 08:49:52 AM UTC 25 |
Finished | Feb 08 08:50:16 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454432341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3454432341 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.999759134 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 11372497963 ps |
CPU time | 83.06 seconds |
Started | Feb 08 08:49:52 AM UTC 25 |
Finished | Feb 08 08:51:18 AM UTC 25 |
Peak memory | 212376 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999759134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.999759134 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.1305826673 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 37983354 ps |
CPU time | 5.02 seconds |
Started | Feb 08 08:49:50 AM UTC 25 |
Finished | Feb 08 08:49:57 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305826673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.1305826673 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.1462076503 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 27715239 ps |
CPU time | 4.23 seconds |
Started | Feb 08 08:49:54 AM UTC 25 |
Finished | Feb 08 08:50:00 AM UTC 25 |
Peak memory | 211936 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462076503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1462076503 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.4246148392 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 59139394 ps |
CPU time | 2.3 seconds |
Started | Feb 08 08:49:48 AM UTC 25 |
Finished | Feb 08 08:49:51 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246148392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.4246148392 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3756394547 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 8148805211 ps |
CPU time | 12.3 seconds |
Started | Feb 08 08:49:49 AM UTC 25 |
Finished | Feb 08 08:50:03 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756394547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3756394547 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.863942189 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 9638825740 ps |
CPU time | 18.42 seconds |
Started | Feb 08 08:49:49 AM UTC 25 |
Finished | Feb 08 08:50:09 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863942189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.863942189 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.1210845885 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 9138291 ps |
CPU time | 1.76 seconds |
Started | Feb 08 08:49:48 AM UTC 25 |
Finished | Feb 08 08:49:51 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210845885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.1210845885 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.2849549933 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 2703943170 ps |
CPU time | 23.07 seconds |
Started | Feb 08 08:49:56 AM UTC 25 |
Finished | Feb 08 08:50:21 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849549933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2849549933 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.785316138 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 177971480 ps |
CPU time | 14.69 seconds |
Started | Feb 08 08:49:58 AM UTC 25 |
Finished | Feb 08 08:50:14 AM UTC 25 |
Peak memory | 212624 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785316138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.785316138 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.2543983970 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 412665106 ps |
CPU time | 62.19 seconds |
Started | Feb 08 08:49:57 AM UTC 25 |
Finished | Feb 08 08:51:01 AM UTC 25 |
Peak memory | 216596 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543983970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.2543983970 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.2229556007 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 137675339 ps |
CPU time | 10.37 seconds |
Started | Feb 08 08:49:58 AM UTC 25 |
Finished | Feb 08 08:50:10 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229556007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.2229556007 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.3918301714 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 49533293 ps |
CPU time | 5.03 seconds |
Started | Feb 08 08:49:54 AM UTC 25 |
Finished | Feb 08 08:50:01 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918301714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3918301714 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2052744416 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 626217159 ps |
CPU time | 14.17 seconds |
Started | Feb 08 08:50:05 AM UTC 25 |
Finished | Feb 08 08:50:21 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052744416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2052744416 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.3792727644 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 41803704099 ps |
CPU time | 352.36 seconds |
Started | Feb 08 08:50:05 AM UTC 25 |
Finished | Feb 08 08:56:02 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792727644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.3792727644 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.2781171552 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 479503060 ps |
CPU time | 12.81 seconds |
Started | Feb 08 08:50:10 AM UTC 25 |
Finished | Feb 08 08:50:25 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781171552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.2781171552 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.1572679636 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 472221522 ps |
CPU time | 12.07 seconds |
Started | Feb 08 08:50:08 AM UTC 25 |
Finished | Feb 08 08:50:22 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572679636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1572679636 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.39431431 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 497460927 ps |
CPU time | 5.59 seconds |
Started | Feb 08 08:50:02 AM UTC 25 |
Finished | Feb 08 08:50:09 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39431431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.39431431 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.2371970278 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 6624524730 ps |
CPU time | 43.06 seconds |
Started | Feb 08 08:50:04 AM UTC 25 |
Finished | Feb 08 08:50:49 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371970278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2371970278 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1443964524 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 4831689382 ps |
CPU time | 28.71 seconds |
Started | Feb 08 08:50:05 AM UTC 25 |
Finished | Feb 08 08:50:36 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443964524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1443964524 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.1481918758 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 165941756 ps |
CPU time | 9.85 seconds |
Started | Feb 08 08:50:04 AM UTC 25 |
Finished | Feb 08 08:50:15 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481918758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.1481918758 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3973513779 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 51326405 ps |
CPU time | 4.5 seconds |
Started | Feb 08 08:50:06 AM UTC 25 |
Finished | Feb 08 08:50:12 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973513779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3973513779 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.87658757 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 28992179 ps |
CPU time | 1.86 seconds |
Started | Feb 08 08:49:59 AM UTC 25 |
Finished | Feb 08 08:50:03 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87658757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_m ode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.87658757 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.451365518 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 11484567344 ps |
CPU time | 12.83 seconds |
Started | Feb 08 08:50:01 AM UTC 25 |
Finished | Feb 08 08:50:15 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451365518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.451365518 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.1530502560 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 1790814209 ps |
CPU time | 16.48 seconds |
Started | Feb 08 08:50:02 AM UTC 25 |
Finished | Feb 08 08:50:20 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530502560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1530502560 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1289987385 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 11722271 ps |
CPU time | 1.75 seconds |
Started | Feb 08 08:49:59 AM UTC 25 |
Finished | Feb 08 08:50:03 AM UTC 25 |
Peak memory | 211300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289987385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1289987385 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.1175423185 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 3652533922 ps |
CPU time | 45.15 seconds |
Started | Feb 08 08:50:10 AM UTC 25 |
Finished | Feb 08 08:50:58 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175423185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1175423185 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.956821812 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 2221644685 ps |
CPU time | 32.07 seconds |
Started | Feb 08 08:50:13 AM UTC 25 |
Finished | Feb 08 08:50:47 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956821812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.956821812 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.231224341 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 632642490 ps |
CPU time | 60.76 seconds |
Started | Feb 08 08:50:12 AM UTC 25 |
Finished | Feb 08 08:51:15 AM UTC 25 |
Peak memory | 216404 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231224341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.231224341 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.1292742607 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 14437369841 ps |
CPU time | 111.04 seconds |
Started | Feb 08 08:50:14 AM UTC 25 |
Finished | Feb 08 08:52:08 AM UTC 25 |
Peak memory | 218700 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292742607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.1292742607 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.3005898292 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 1737248332 ps |
CPU time | 11.78 seconds |
Started | Feb 08 08:50:08 AM UTC 25 |
Finished | Feb 08 08:50:21 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005898292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3005898292 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.1306034143 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1132634919 ps |
CPU time | 16.78 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:43:05 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306034143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1306034143 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.830299879 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 82278353538 ps |
CPU time | 401.13 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:49:33 AM UTC 25 |
Peak memory | 218120 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830299879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.830299879 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3891583501 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 360925884 ps |
CPU time | 8.59 seconds |
Started | Feb 08 08:42:48 AM UTC 25 |
Finished | Feb 08 08:42:59 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891583501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3891583501 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1193286508 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 694237331 ps |
CPU time | 12.5 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:43:01 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193286508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1193286508 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.3729115607 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 82482893 ps |
CPU time | 6.89 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:42:55 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3729115607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.3729115607 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.908945020 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 29266806772 ps |
CPU time | 212.47 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:46:23 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908945020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.908945020 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.2866440297 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 17885850511 ps |
CPU time | 151.02 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:45:21 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866440297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2866440297 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.1361199436 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 66779481 ps |
CPU time | 4.8 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:42:53 AM UTC 25 |
Peak memory | 212552 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361199436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.1361199436 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1145120683 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 1184742683 ps |
CPU time | 16.83 seconds |
Started | Feb 08 08:42:46 AM UTC 25 |
Finished | Feb 08 08:43:05 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145120683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1145120683 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.1380695399 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 17373685 ps |
CPU time | 1.61 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:42:47 AM UTC 25 |
Peak memory | 211324 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380695399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1380695399 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.1746199097 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 2327892132 ps |
CPU time | 14.49 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:43:00 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746199097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1746199097 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.4177973651 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 3179421502 ps |
CPU time | 9.59 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:42:55 AM UTC 25 |
Peak memory | 212552 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177973651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.4177973651 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.3843107113 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 20128416 ps |
CPU time | 1.36 seconds |
Started | Feb 08 08:42:44 AM UTC 25 |
Finished | Feb 08 08:42:47 AM UTC 25 |
Peak memory | 211292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843107113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.3843107113 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.1955536155 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 4282730227 ps |
CPU time | 84.67 seconds |
Started | Feb 08 08:42:48 AM UTC 25 |
Finished | Feb 08 08:44:16 AM UTC 25 |
Peak memory | 214372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955536155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1955536155 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.1974084566 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 6428573998 ps |
CPU time | 135.21 seconds |
Started | Feb 08 08:42:49 AM UTC 25 |
Finished | Feb 08 08:45:07 AM UTC 25 |
Peak memory | 216468 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974084566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.1974084566 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.3937337338 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 9170645173 ps |
CPU time | 55.8 seconds |
Started | Feb 08 08:42:48 AM UTC 25 |
Finished | Feb 08 08:43:47 AM UTC 25 |
Peak memory | 214372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937337338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.3937337338 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.3883989924 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 1299165430 ps |
CPU time | 127.79 seconds |
Started | Feb 08 08:42:49 AM UTC 25 |
Finished | Feb 08 08:45:00 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883989924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.3883989924 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.1167816773 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 16703029 ps |
CPU time | 1.88 seconds |
Started | Feb 08 08:42:48 AM UTC 25 |
Finished | Feb 08 08:42:52 AM UTC 25 |
Peak memory | 211320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167816773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1167816773 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3563723447 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 700010897 ps |
CPU time | 15.26 seconds |
Started | Feb 08 08:50:21 AM UTC 25 |
Finished | Feb 08 08:50:38 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563723447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3563723447 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.192019905 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 12080995731 ps |
CPU time | 79.68 seconds |
Started | Feb 08 08:50:23 AM UTC 25 |
Finished | Feb 08 08:51:45 AM UTC 25 |
Peak memory | 214392 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192019905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.192019905 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.4004701847 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 786242226 ps |
CPU time | 10.44 seconds |
Started | Feb 08 08:50:24 AM UTC 25 |
Finished | Feb 08 08:50:36 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004701847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.4004701847 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.112833728 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 722657495 ps |
CPU time | 7.03 seconds |
Started | Feb 08 08:50:23 AM UTC 25 |
Finished | Feb 08 08:50:32 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112833728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.112833728 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.1659376397 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 30445510 ps |
CPU time | 5.36 seconds |
Started | Feb 08 08:50:17 AM UTC 25 |
Finished | Feb 08 08:50:24 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659376397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.1659376397 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.4245057672 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 30951807590 ps |
CPU time | 156.65 seconds |
Started | Feb 08 08:50:20 AM UTC 25 |
Finished | Feb 08 08:53:00 AM UTC 25 |
Peak memory | 212356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245057672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.4245057672 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.2841432548 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 3063802130 ps |
CPU time | 7.73 seconds |
Started | Feb 08 08:50:20 AM UTC 25 |
Finished | Feb 08 08:50:29 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841432548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2841432548 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.2669533179 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 65853221 ps |
CPU time | 4.05 seconds |
Started | Feb 08 08:50:17 AM UTC 25 |
Finished | Feb 08 08:50:23 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669533179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.2669533179 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.3802460331 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 6260180001 ps |
CPU time | 10.69 seconds |
Started | Feb 08 08:50:23 AM UTC 25 |
Finished | Feb 08 08:50:35 AM UTC 25 |
Peak memory | 212312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802460331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3802460331 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.86292497 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 10595416 ps |
CPU time | 1.63 seconds |
Started | Feb 08 08:50:15 AM UTC 25 |
Finished | Feb 08 08:50:19 AM UTC 25 |
Peak memory | 211352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86292497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_m ode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.86292497 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.1942143222 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 2514855403 ps |
CPU time | 15.75 seconds |
Started | Feb 08 08:50:17 AM UTC 25 |
Finished | Feb 08 08:50:35 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942143222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1942143222 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.3766892105 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 2441517938 ps |
CPU time | 8.16 seconds |
Started | Feb 08 08:50:17 AM UTC 25 |
Finished | Feb 08 08:50:27 AM UTC 25 |
Peak memory | 212428 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766892105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3766892105 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.3886859832 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 12290025 ps |
CPU time | 1.55 seconds |
Started | Feb 08 08:50:16 AM UTC 25 |
Finished | Feb 08 08:50:19 AM UTC 25 |
Peak memory | 211416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886859832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.3886859832 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.231261375 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 14317240420 ps |
CPU time | 44.24 seconds |
Started | Feb 08 08:50:24 AM UTC 25 |
Finished | Feb 08 08:51:11 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231261375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.231261375 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3094614002 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 3791533934 ps |
CPU time | 45.94 seconds |
Started | Feb 08 08:50:27 AM UTC 25 |
Finished | Feb 08 08:51:15 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094614002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3094614002 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.1329995813 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 1932659729 ps |
CPU time | 176.2 seconds |
Started | Feb 08 08:50:26 AM UTC 25 |
Finished | Feb 08 08:53:25 AM UTC 25 |
Peak memory | 216400 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329995813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.1329995813 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.422296762 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 712202988 ps |
CPU time | 83.84 seconds |
Started | Feb 08 08:50:27 AM UTC 25 |
Finished | Feb 08 08:51:54 AM UTC 25 |
Peak memory | 218448 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422296762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.422296762 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.1600330024 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 345623669 ps |
CPU time | 7.67 seconds |
Started | Feb 08 08:50:23 AM UTC 25 |
Finished | Feb 08 08:50:33 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600330024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.1600330024 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.2316066444 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 208390681 ps |
CPU time | 3.63 seconds |
Started | Feb 08 08:50:34 AM UTC 25 |
Finished | Feb 08 08:50:39 AM UTC 25 |
Peak memory | 211700 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316066444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.2316066444 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.2430008703 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 168425835324 ps |
CPU time | 320.74 seconds |
Started | Feb 08 08:50:34 AM UTC 25 |
Finished | Feb 08 08:55:59 AM UTC 25 |
Peak memory | 214592 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430008703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.2430008703 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.3164973667 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 1318106225 ps |
CPU time | 12.53 seconds |
Started | Feb 08 08:50:36 AM UTC 25 |
Finished | Feb 08 08:50:51 AM UTC 25 |
Peak memory | 212484 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164973667 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.3164973667 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.3823921958 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 661563227 ps |
CPU time | 8.7 seconds |
Started | Feb 08 08:50:36 AM UTC 25 |
Finished | Feb 08 08:50:47 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823921958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3823921958 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.1146666589 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 74611910 ps |
CPU time | 9.01 seconds |
Started | Feb 08 08:50:30 AM UTC 25 |
Finished | Feb 08 08:50:41 AM UTC 25 |
Peak memory | 212028 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146666589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.1146666589 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.16713253 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 31664531186 ps |
CPU time | 131.29 seconds |
Started | Feb 08 08:50:32 AM UTC 25 |
Finished | Feb 08 08:52:46 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16713253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.16713253 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.3744379567 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 13967118089 ps |
CPU time | 81.48 seconds |
Started | Feb 08 08:50:34 AM UTC 25 |
Finished | Feb 08 08:51:58 AM UTC 25 |
Peak memory | 211780 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744379567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3744379567 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.2128350242 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 71654103 ps |
CPU time | 7.05 seconds |
Started | Feb 08 08:50:30 AM UTC 25 |
Finished | Feb 08 08:50:40 AM UTC 25 |
Peak memory | 212276 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128350242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.2128350242 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.2432996335 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 232088079 ps |
CPU time | 2.93 seconds |
Started | Feb 08 08:50:34 AM UTC 25 |
Finished | Feb 08 08:50:38 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432996335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2432996335 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.3321363923 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 37016415 ps |
CPU time | 1.91 seconds |
Started | Feb 08 08:50:27 AM UTC 25 |
Finished | Feb 08 08:50:31 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321363923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3321363923 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.3911327196 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 6860340387 ps |
CPU time | 19.3 seconds |
Started | Feb 08 08:50:29 AM UTC 25 |
Finished | Feb 08 08:50:50 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911327196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3911327196 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.1377925143 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 875034737 ps |
CPU time | 5.38 seconds |
Started | Feb 08 08:50:29 AM UTC 25 |
Finished | Feb 08 08:50:36 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377925143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1377925143 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.2260888986 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 14099905 ps |
CPU time | 1.71 seconds |
Started | Feb 08 08:50:29 AM UTC 25 |
Finished | Feb 08 08:50:32 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260888986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.2260888986 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.2471625830 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 283172124 ps |
CPU time | 30.78 seconds |
Started | Feb 08 08:50:36 AM UTC 25 |
Finished | Feb 08 08:51:09 AM UTC 25 |
Peak memory | 214544 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471625830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2471625830 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.1324294342 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 5850525432 ps |
CPU time | 37.37 seconds |
Started | Feb 08 08:50:38 AM UTC 25 |
Finished | Feb 08 08:51:17 AM UTC 25 |
Peak memory | 212620 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324294342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1324294342 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.3310626799 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 760739026 ps |
CPU time | 98.95 seconds |
Started | Feb 08 08:50:38 AM UTC 25 |
Finished | Feb 08 08:52:20 AM UTC 25 |
Peak memory | 216596 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310626799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.3310626799 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.1877567003 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 4674771886 ps |
CPU time | 128.68 seconds |
Started | Feb 08 08:50:38 AM UTC 25 |
Finished | Feb 08 08:52:50 AM UTC 25 |
Peak memory | 218504 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877567003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.1877567003 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.1816535073 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 2094709090 ps |
CPU time | 15.62 seconds |
Started | Feb 08 08:50:36 AM UTC 25 |
Finished | Feb 08 08:50:54 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816535073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.1816535073 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.2497490912 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 934632856 ps |
CPU time | 7.7 seconds |
Started | Feb 08 08:50:44 AM UTC 25 |
Finished | Feb 08 08:50:54 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497490912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.2497490912 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.2867986735 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 263152598 ps |
CPU time | 4.64 seconds |
Started | Feb 08 08:50:52 AM UTC 25 |
Finished | Feb 08 08:50:58 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867986735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.2867986735 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.2974342724 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 595320912 ps |
CPU time | 10.36 seconds |
Started | Feb 08 08:50:48 AM UTC 25 |
Finished | Feb 08 08:51:00 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974342724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2974342724 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.645692930 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 69889815 ps |
CPU time | 9.14 seconds |
Started | Feb 08 08:50:41 AM UTC 25 |
Finished | Feb 08 08:50:52 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645692930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.645692930 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.1253744554 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 130496173528 ps |
CPU time | 76.65 seconds |
Started | Feb 08 08:50:43 AM UTC 25 |
Finished | Feb 08 08:52:01 AM UTC 25 |
Peak memory | 212284 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253744554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1253744554 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1422739915 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 20906651228 ps |
CPU time | 184.98 seconds |
Started | Feb 08 08:50:44 AM UTC 25 |
Finished | Feb 08 08:53:53 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422739915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1422739915 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.1260820555 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 76366745 ps |
CPU time | 6.36 seconds |
Started | Feb 08 08:50:43 AM UTC 25 |
Finished | Feb 08 08:50:51 AM UTC 25 |
Peak memory | 212216 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260820555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.1260820555 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.4091219310 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 57973274 ps |
CPU time | 5.39 seconds |
Started | Feb 08 08:50:48 AM UTC 25 |
Finished | Feb 08 08:50:55 AM UTC 25 |
Peak memory | 212584 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091219310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4091219310 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.1289174351 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 186792326 ps |
CPU time | 2 seconds |
Started | Feb 08 08:50:40 AM UTC 25 |
Finished | Feb 08 08:50:44 AM UTC 25 |
Peak memory | 211424 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289174351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1289174351 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.2016956027 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 4033304507 ps |
CPU time | 13.71 seconds |
Started | Feb 08 08:50:40 AM UTC 25 |
Finished | Feb 08 08:50:55 AM UTC 25 |
Peak memory | 212624 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016956027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2016956027 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.4066067442 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 1214084113 ps |
CPU time | 14.32 seconds |
Started | Feb 08 08:50:40 AM UTC 25 |
Finished | Feb 08 08:50:56 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066067442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.4066067442 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.4278263019 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 8382054 ps |
CPU time | 1.21 seconds |
Started | Feb 08 08:50:40 AM UTC 25 |
Finished | Feb 08 08:50:43 AM UTC 25 |
Peak memory | 211300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278263019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.4278263019 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.2007908029 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 443315488 ps |
CPU time | 27.65 seconds |
Started | Feb 08 08:50:52 AM UTC 25 |
Finished | Feb 08 08:51:21 AM UTC 25 |
Peak memory | 214356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007908029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2007908029 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.490450352 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 2851843648 ps |
CPU time | 37.57 seconds |
Started | Feb 08 08:50:52 AM UTC 25 |
Finished | Feb 08 08:51:31 AM UTC 25 |
Peak memory | 212552 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490450352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.490450352 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.530894284 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 624692310 ps |
CPU time | 62.49 seconds |
Started | Feb 08 08:50:52 AM UTC 25 |
Finished | Feb 08 08:51:56 AM UTC 25 |
Peak memory | 214484 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530894284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.530894284 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.2393814739 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 59707397 ps |
CPU time | 19.46 seconds |
Started | Feb 08 08:50:52 AM UTC 25 |
Finished | Feb 08 08:51:13 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393814739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.2393814739 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.1202104958 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 1788399222 ps |
CPU time | 16.37 seconds |
Started | Feb 08 08:50:50 AM UTC 25 |
Finished | Feb 08 08:51:08 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202104958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.1202104958 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.3346442285 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 1115807096 ps |
CPU time | 25.12 seconds |
Started | Feb 08 08:50:58 AM UTC 25 |
Finished | Feb 08 08:51:25 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346442285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.3346442285 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.2043092815 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 40284928644 ps |
CPU time | 259.5 seconds |
Started | Feb 08 08:50:58 AM UTC 25 |
Finished | Feb 08 08:55:21 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043092815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.2043092815 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.4178223067 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 320289244 ps |
CPU time | 4.24 seconds |
Started | Feb 08 08:51:01 AM UTC 25 |
Finished | Feb 08 08:51:07 AM UTC 25 |
Peak memory | 212240 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178223067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.4178223067 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.201096920 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 544455107 ps |
CPU time | 9.97 seconds |
Started | Feb 08 08:51:00 AM UTC 25 |
Finished | Feb 08 08:51:11 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201096920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.201096920 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.1287913369 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 48635123 ps |
CPU time | 7.95 seconds |
Started | Feb 08 08:50:56 AM UTC 25 |
Finished | Feb 08 08:51:06 AM UTC 25 |
Peak memory | 212452 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287913369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.1287913369 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.2255497205 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 19221630238 ps |
CPU time | 62.96 seconds |
Started | Feb 08 08:50:58 AM UTC 25 |
Finished | Feb 08 08:52:03 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255497205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2255497205 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.3362634852 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 38626849861 ps |
CPU time | 87.29 seconds |
Started | Feb 08 08:50:58 AM UTC 25 |
Finished | Feb 08 08:52:27 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362634852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.3362634852 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.2520994281 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 207014501 ps |
CPU time | 11.23 seconds |
Started | Feb 08 08:50:56 AM UTC 25 |
Finished | Feb 08 08:51:09 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520994281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.2520994281 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.2224876209 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 3175641419 ps |
CPU time | 18.17 seconds |
Started | Feb 08 08:51:00 AM UTC 25 |
Finished | Feb 08 08:51:19 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224876209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2224876209 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.2481018074 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 19404655 ps |
CPU time | 1.7 seconds |
Started | Feb 08 08:50:53 AM UTC 25 |
Finished | Feb 08 08:50:56 AM UTC 25 |
Peak memory | 211308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481018074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2481018074 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.569662849 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 13881111221 ps |
CPU time | 9.53 seconds |
Started | Feb 08 08:50:56 AM UTC 25 |
Finished | Feb 08 08:51:07 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569662849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.569662849 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.2752292757 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 783884888 ps |
CPU time | 8.67 seconds |
Started | Feb 08 08:50:56 AM UTC 25 |
Finished | Feb 08 08:51:06 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752292757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2752292757 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.1383206136 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 32551333 ps |
CPU time | 1.29 seconds |
Started | Feb 08 08:50:56 AM UTC 25 |
Finished | Feb 08 08:50:59 AM UTC 25 |
Peak memory | 211304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383206136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.1383206136 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.56043150 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 1983321349 ps |
CPU time | 22.21 seconds |
Started | Feb 08 08:51:01 AM UTC 25 |
Finished | Feb 08 08:51:25 AM UTC 25 |
Peak memory | 212232 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56043150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bu ild_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.56043150 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.2597467829 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 287060976 ps |
CPU time | 36.33 seconds |
Started | Feb 08 08:51:06 AM UTC 25 |
Finished | Feb 08 08:51:44 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597467829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2597467829 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.3480139526 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 4462284121 ps |
CPU time | 111.32 seconds |
Started | Feb 08 08:51:02 AM UTC 25 |
Finished | Feb 08 08:52:57 AM UTC 25 |
Peak memory | 216464 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480139526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.3480139526 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.3437195388 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 16285601905 ps |
CPU time | 206.37 seconds |
Started | Feb 08 08:51:07 AM UTC 25 |
Finished | Feb 08 08:54:37 AM UTC 25 |
Peak memory | 218508 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437195388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.3437195388 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.3213628192 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 661405782 ps |
CPU time | 13.88 seconds |
Started | Feb 08 08:51:00 AM UTC 25 |
Finished | Feb 08 08:51:15 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213628192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3213628192 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.3424575177 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 8903813 ps |
CPU time | 2.05 seconds |
Started | Feb 08 08:51:13 AM UTC 25 |
Finished | Feb 08 08:51:17 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424575177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.3424575177 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1903665134 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 153305730060 ps |
CPU time | 213.03 seconds |
Started | Feb 08 08:51:15 AM UTC 25 |
Finished | Feb 08 08:54:52 AM UTC 25 |
Peak memory | 214420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903665134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1903665134 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.4193476921 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 87198426 ps |
CPU time | 7.52 seconds |
Started | Feb 08 08:51:17 AM UTC 25 |
Finished | Feb 08 08:51:26 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193476921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.4193476921 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.85592239 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 133069311 ps |
CPU time | 4.13 seconds |
Started | Feb 08 08:51:15 AM UTC 25 |
Finished | Feb 08 08:51:21 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85592239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.85592239 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.629109046 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 511976170 ps |
CPU time | 7.81 seconds |
Started | Feb 08 08:51:10 AM UTC 25 |
Finished | Feb 08 08:51:20 AM UTC 25 |
Peak memory | 212440 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629109046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.629109046 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.592859059 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 21038273584 ps |
CPU time | 133.3 seconds |
Started | Feb 08 08:51:12 AM UTC 25 |
Finished | Feb 08 08:53:28 AM UTC 25 |
Peak memory | 212444 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592859059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.592859059 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.1383334098 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 37299579763 ps |
CPU time | 114.25 seconds |
Started | Feb 08 08:51:12 AM UTC 25 |
Finished | Feb 08 08:53:09 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383334098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1383334098 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.3165177175 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 477434929 ps |
CPU time | 7.15 seconds |
Started | Feb 08 08:51:10 AM UTC 25 |
Finished | Feb 08 08:51:19 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165177175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.3165177175 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.3187624653 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 11407126 ps |
CPU time | 1.76 seconds |
Started | Feb 08 08:51:15 AM UTC 25 |
Finished | Feb 08 08:51:18 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187624653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3187624653 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.312706929 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 109167141 ps |
CPU time | 2.46 seconds |
Started | Feb 08 08:51:09 AM UTC 25 |
Finished | Feb 08 08:51:13 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312706929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.312706929 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3528461306 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 2735015210 ps |
CPU time | 10.5 seconds |
Started | Feb 08 08:51:09 AM UTC 25 |
Finished | Feb 08 08:51:21 AM UTC 25 |
Peak memory | 212624 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528461306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3528461306 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.2437707742 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 1328220869 ps |
CPU time | 14.05 seconds |
Started | Feb 08 08:51:10 AM UTC 25 |
Finished | Feb 08 08:51:26 AM UTC 25 |
Peak memory | 212252 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437707742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2437707742 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.1155777123 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 8875437 ps |
CPU time | 1.65 seconds |
Started | Feb 08 08:51:09 AM UTC 25 |
Finished | Feb 08 08:51:12 AM UTC 25 |
Peak memory | 211296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155777123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.1155777123 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.464348339 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 4058571849 ps |
CPU time | 49.06 seconds |
Started | Feb 08 08:51:17 AM UTC 25 |
Finished | Feb 08 08:52:08 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464348339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.464348339 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2674965251 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 316027382 ps |
CPU time | 19.16 seconds |
Started | Feb 08 08:51:18 AM UTC 25 |
Finished | Feb 08 08:51:40 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674965251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2674965251 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.3029284283 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 6356819068 ps |
CPU time | 133.45 seconds |
Started | Feb 08 08:51:18 AM UTC 25 |
Finished | Feb 08 08:53:35 AM UTC 25 |
Peak memory | 216660 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029284283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.3029284283 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.2200785447 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 2184106905 ps |
CPU time | 9.74 seconds |
Started | Feb 08 08:51:17 AM UTC 25 |
Finished | Feb 08 08:51:29 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200785447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2200785447 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.491512412 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 973245748 ps |
CPU time | 10.33 seconds |
Started | Feb 08 08:51:23 AM UTC 25 |
Finished | Feb 08 08:51:36 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491512412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.491512412 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.3447938586 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 96810347271 ps |
CPU time | 277.35 seconds |
Started | Feb 08 08:51:25 AM UTC 25 |
Finished | Feb 08 08:56:07 AM UTC 25 |
Peak memory | 214420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447938586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.3447938586 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.2855263030 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 60004502 ps |
CPU time | 1.87 seconds |
Started | Feb 08 08:51:27 AM UTC 25 |
Finished | Feb 08 08:51:32 AM UTC 25 |
Peak memory | 211296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855263030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.2855263030 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.3536654318 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 119007515 ps |
CPU time | 3.61 seconds |
Started | Feb 08 08:51:25 AM UTC 25 |
Finished | Feb 08 08:51:30 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536654318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3536654318 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.1065048212 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 437453821 ps |
CPU time | 3.47 seconds |
Started | Feb 08 08:51:22 AM UTC 25 |
Finished | Feb 08 08:51:27 AM UTC 25 |
Peak memory | 211956 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065048212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.1065048212 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.3204684865 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 24917096407 ps |
CPU time | 110.35 seconds |
Started | Feb 08 08:51:22 AM UTC 25 |
Finished | Feb 08 08:53:15 AM UTC 25 |
Peak memory | 211852 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204684865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.3204684865 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.2417274280 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 27642895936 ps |
CPU time | 60.44 seconds |
Started | Feb 08 08:51:22 AM UTC 25 |
Finished | Feb 08 08:52:25 AM UTC 25 |
Peak memory | 211968 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417274280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2417274280 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.2093692314 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 28818187 ps |
CPU time | 3.75 seconds |
Started | Feb 08 08:51:22 AM UTC 25 |
Finished | Feb 08 08:51:28 AM UTC 25 |
Peak memory | 211828 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093692314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.2093692314 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.2427704136 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 55262219 ps |
CPU time | 5.16 seconds |
Started | Feb 08 08:51:25 AM UTC 25 |
Finished | Feb 08 08:51:32 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427704136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.2427704136 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.2892653604 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 184047917 ps |
CPU time | 1.43 seconds |
Started | Feb 08 08:51:20 AM UTC 25 |
Finished | Feb 08 08:51:23 AM UTC 25 |
Peak memory | 211412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892653604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2892653604 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.331097081 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 1428651851 ps |
CPU time | 10.47 seconds |
Started | Feb 08 08:51:20 AM UTC 25 |
Finished | Feb 08 08:51:33 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331097081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.331097081 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.1952773822 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 727694605 ps |
CPU time | 6.42 seconds |
Started | Feb 08 08:51:22 AM UTC 25 |
Finished | Feb 08 08:51:30 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952773822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1952773822 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.3542487383 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 10262074 ps |
CPU time | 1.58 seconds |
Started | Feb 08 08:51:20 AM UTC 25 |
Finished | Feb 08 08:51:23 AM UTC 25 |
Peak memory | 211312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542487383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.3542487383 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.1371868708 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 7795110060 ps |
CPU time | 28.32 seconds |
Started | Feb 08 08:51:27 AM UTC 25 |
Finished | Feb 08 08:51:59 AM UTC 25 |
Peak memory | 212344 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371868708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1371868708 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.3985087283 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 15023346240 ps |
CPU time | 44.62 seconds |
Started | Feb 08 08:51:27 AM UTC 25 |
Finished | Feb 08 08:52:15 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985087283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3985087283 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.3914650077 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 5693687554 ps |
CPU time | 87.68 seconds |
Started | Feb 08 08:51:27 AM UTC 25 |
Finished | Feb 08 08:52:59 AM UTC 25 |
Peak memory | 216524 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914650077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.3914650077 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1300275359 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 1369500362 ps |
CPU time | 254.07 seconds |
Started | Feb 08 08:51:29 AM UTC 25 |
Finished | Feb 08 08:55:48 AM UTC 25 |
Peak memory | 216392 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300275359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1300275359 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.4161410989 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 479776020 ps |
CPU time | 8.31 seconds |
Started | Feb 08 08:51:27 AM UTC 25 |
Finished | Feb 08 08:51:38 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161410989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4161410989 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.510879132 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 485613947 ps |
CPU time | 5.1 seconds |
Started | Feb 08 08:51:34 AM UTC 25 |
Finished | Feb 08 08:51:41 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510879132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.510879132 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.4248642899 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 17655847199 ps |
CPU time | 166.4 seconds |
Started | Feb 08 08:51:34 AM UTC 25 |
Finished | Feb 08 08:54:23 AM UTC 25 |
Peak memory | 214420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248642899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.4248642899 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.2169928848 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 18422805 ps |
CPU time | 2.67 seconds |
Started | Feb 08 08:51:40 AM UTC 25 |
Finished | Feb 08 08:51:44 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169928848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.2169928848 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.1184741986 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 1176477364 ps |
CPU time | 9.43 seconds |
Started | Feb 08 08:51:35 AM UTC 25 |
Finished | Feb 08 08:51:46 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184741986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1184741986 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.1086955331 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 198935898 ps |
CPU time | 6.24 seconds |
Started | Feb 08 08:51:32 AM UTC 25 |
Finished | Feb 08 08:51:40 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086955331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.1086955331 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.2675349428 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 41607601245 ps |
CPU time | 70.32 seconds |
Started | Feb 08 08:51:33 AM UTC 25 |
Finished | Feb 08 08:52:47 AM UTC 25 |
Peak memory | 212356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675349428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2675349428 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.1831790606 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 24391428080 ps |
CPU time | 84.83 seconds |
Started | Feb 08 08:51:34 AM UTC 25 |
Finished | Feb 08 08:53:01 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831790606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1831790606 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2098624876 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 24368026 ps |
CPU time | 3.2 seconds |
Started | Feb 08 08:51:33 AM UTC 25 |
Finished | Feb 08 08:51:39 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098624876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2098624876 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.3227620102 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 25085998 ps |
CPU time | 2.75 seconds |
Started | Feb 08 08:51:35 AM UTC 25 |
Finished | Feb 08 08:51:39 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227620102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.3227620102 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.3928273893 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 103577058 ps |
CPU time | 2.03 seconds |
Started | Feb 08 08:51:29 AM UTC 25 |
Finished | Feb 08 08:51:33 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928273893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3928273893 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.760401938 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 3607502634 ps |
CPU time | 17.75 seconds |
Started | Feb 08 08:51:31 AM UTC 25 |
Finished | Feb 08 08:51:52 AM UTC 25 |
Peak memory | 212052 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760401938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.760401938 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.2435526313 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 6228042799 ps |
CPU time | 11.81 seconds |
Started | Feb 08 08:51:31 AM UTC 25 |
Finished | Feb 08 08:51:46 AM UTC 25 |
Peak memory | 212276 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435526313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2435526313 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.1668267057 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 11071760 ps |
CPU time | 1.81 seconds |
Started | Feb 08 08:51:30 AM UTC 25 |
Finished | Feb 08 08:51:34 AM UTC 25 |
Peak memory | 211316 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668267057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.1668267057 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.2388803541 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 2797802191 ps |
CPU time | 41.29 seconds |
Started | Feb 08 08:51:40 AM UTC 25 |
Finished | Feb 08 08:52:23 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388803541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2388803541 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.1180730061 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 272563110 ps |
CPU time | 19.59 seconds |
Started | Feb 08 08:51:41 AM UTC 25 |
Finished | Feb 08 08:52:03 AM UTC 25 |
Peak memory | 212488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180730061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1180730061 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1003293765 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 656321050 ps |
CPU time | 113.47 seconds |
Started | Feb 08 08:51:41 AM UTC 25 |
Finished | Feb 08 08:53:37 AM UTC 25 |
Peak memory | 216400 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003293765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1003293765 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.2891312589 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 321340240 ps |
CPU time | 5.48 seconds |
Started | Feb 08 08:51:36 AM UTC 25 |
Finished | Feb 08 08:51:43 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891312589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2891312589 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2260641196 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 704451667 ps |
CPU time | 13.63 seconds |
Started | Feb 08 08:51:48 AM UTC 25 |
Finished | Feb 08 08:52:03 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260641196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2260641196 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.3372302198 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 50442768504 ps |
CPU time | 110.01 seconds |
Started | Feb 08 08:51:48 AM UTC 25 |
Finished | Feb 08 08:53:41 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372302198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.3372302198 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.795177831 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 369230918 ps |
CPU time | 6.04 seconds |
Started | Feb 08 08:51:52 AM UTC 25 |
Finished | Feb 08 08:52:01 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795177831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.795177831 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.1573353587 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 260497142 ps |
CPU time | 7.77 seconds |
Started | Feb 08 08:51:48 AM UTC 25 |
Finished | Feb 08 08:51:57 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573353587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1573353587 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.3469637710 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 190290652 ps |
CPU time | 3.64 seconds |
Started | Feb 08 08:51:45 AM UTC 25 |
Finished | Feb 08 08:51:51 AM UTC 25 |
Peak memory | 211988 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469637710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.3469637710 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1752849060 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 78931764252 ps |
CPU time | 189.61 seconds |
Started | Feb 08 08:51:45 AM UTC 25 |
Finished | Feb 08 08:54:59 AM UTC 25 |
Peak memory | 212340 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752849060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1752849060 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1659548446 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 2757497392 ps |
CPU time | 24.71 seconds |
Started | Feb 08 08:51:45 AM UTC 25 |
Finished | Feb 08 08:52:13 AM UTC 25 |
Peak memory | 212128 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659548446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1659548446 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.114372270 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 181594225 ps |
CPU time | 6.3 seconds |
Started | Feb 08 08:51:45 AM UTC 25 |
Finished | Feb 08 08:51:54 AM UTC 25 |
Peak memory | 211720 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114372270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.114372270 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.643148616 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 3744501321 ps |
CPU time | 16.81 seconds |
Started | Feb 08 08:51:48 AM UTC 25 |
Finished | Feb 08 08:52:06 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643148616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.643148616 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.387587857 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 128851821 ps |
CPU time | 1.47 seconds |
Started | Feb 08 08:51:43 AM UTC 25 |
Finished | Feb 08 08:51:46 AM UTC 25 |
Peak memory | 211272 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387587857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.387587857 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.1266860352 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 3258229652 ps |
CPU time | 17.32 seconds |
Started | Feb 08 08:51:43 AM UTC 25 |
Finished | Feb 08 08:52:02 AM UTC 25 |
Peak memory | 212336 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266860352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1266860352 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3067119160 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 2768018108 ps |
CPU time | 17.71 seconds |
Started | Feb 08 08:51:45 AM UTC 25 |
Finished | Feb 08 08:52:06 AM UTC 25 |
Peak memory | 212332 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067119160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3067119160 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.882714405 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 10353211 ps |
CPU time | 1.55 seconds |
Started | Feb 08 08:51:43 AM UTC 25 |
Finished | Feb 08 08:51:46 AM UTC 25 |
Peak memory | 211304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882714405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.882714405 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.2903737202 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 247441177 ps |
CPU time | 23.71 seconds |
Started | Feb 08 08:51:53 AM UTC 25 |
Finished | Feb 08 08:52:20 AM UTC 25 |
Peak memory | 214356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903737202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.2903737202 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.2502326929 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 146807860 ps |
CPU time | 12.67 seconds |
Started | Feb 08 08:51:55 AM UTC 25 |
Finished | Feb 08 08:52:09 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502326929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2502326929 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.820429525 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 19921680 ps |
CPU time | 8.58 seconds |
Started | Feb 08 08:51:55 AM UTC 25 |
Finished | Feb 08 08:52:06 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820429525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.820429525 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.557228505 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 2664654468 ps |
CPU time | 83.01 seconds |
Started | Feb 08 08:51:58 AM UTC 25 |
Finished | Feb 08 08:53:24 AM UTC 25 |
Peak memory | 216208 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557228505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.557228505 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.1432392491 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 329306492 ps |
CPU time | 6.92 seconds |
Started | Feb 08 08:51:48 AM UTC 25 |
Finished | Feb 08 08:51:57 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432392491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.1432392491 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.3309921712 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 881164808 ps |
CPU time | 22.06 seconds |
Started | Feb 08 08:52:05 AM UTC 25 |
Finished | Feb 08 08:52:29 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309921712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.3309921712 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.3397271519 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 14253194374 ps |
CPU time | 118.04 seconds |
Started | Feb 08 08:52:05 AM UTC 25 |
Finished | Feb 08 08:54:06 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397271519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.3397271519 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.4245887473 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 480070459 ps |
CPU time | 6.83 seconds |
Started | Feb 08 08:52:07 AM UTC 25 |
Finished | Feb 08 08:52:16 AM UTC 25 |
Peak memory | 212028 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245887473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.4245887473 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.2706195800 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 41034421 ps |
CPU time | 5.74 seconds |
Started | Feb 08 08:52:06 AM UTC 25 |
Finished | Feb 08 08:52:13 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706195800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2706195800 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.665968569 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 34251405 ps |
CPU time | 4.16 seconds |
Started | Feb 08 08:52:02 AM UTC 25 |
Finished | Feb 08 08:52:08 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665968569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.665968569 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.1539092083 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 53909528225 ps |
CPU time | 241.98 seconds |
Started | Feb 08 08:52:03 AM UTC 25 |
Finished | Feb 08 08:56:10 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539092083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1539092083 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.4006487376 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 75971030680 ps |
CPU time | 242.96 seconds |
Started | Feb 08 08:52:03 AM UTC 25 |
Finished | Feb 08 08:56:10 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006487376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.4006487376 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.1893838112 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 144798431 ps |
CPU time | 7.23 seconds |
Started | Feb 08 08:52:03 AM UTC 25 |
Finished | Feb 08 08:52:12 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893838112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.1893838112 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.546802501 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 48467767 ps |
CPU time | 4.65 seconds |
Started | Feb 08 08:52:05 AM UTC 25 |
Finished | Feb 08 08:52:12 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546802501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.546802501 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.24906034 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 56744202 ps |
CPU time | 1.68 seconds |
Started | Feb 08 08:51:58 AM UTC 25 |
Finished | Feb 08 08:52:02 AM UTC 25 |
Peak memory | 211176 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24906034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xb ar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_m ode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.24906034 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.4225565916 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 5075799358 ps |
CPU time | 16.14 seconds |
Started | Feb 08 08:51:59 AM UTC 25 |
Finished | Feb 08 08:52:18 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225565916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.4225565916 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.885310039 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 3875342912 ps |
CPU time | 13.49 seconds |
Started | Feb 08 08:52:00 AM UTC 25 |
Finished | Feb 08 08:52:16 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885310039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.885310039 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.960489946 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 10109861 ps |
CPU time | 1.75 seconds |
Started | Feb 08 08:51:59 AM UTC 25 |
Finished | Feb 08 08:52:03 AM UTC 25 |
Peak memory | 211292 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960489946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.960489946 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.4098749218 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 12308341326 ps |
CPU time | 64.26 seconds |
Started | Feb 08 08:52:07 AM UTC 25 |
Finished | Feb 08 08:53:14 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098749218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.4098749218 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.784549886 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 3064813820 ps |
CPU time | 46.68 seconds |
Started | Feb 08 08:52:09 AM UTC 25 |
Finished | Feb 08 08:52:58 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784549886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.784549886 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.3050486216 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 193801123 ps |
CPU time | 23.93 seconds |
Started | Feb 08 08:52:09 AM UTC 25 |
Finished | Feb 08 08:52:36 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050486216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.3050486216 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.2928076213 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 548885414 ps |
CPU time | 55.08 seconds |
Started | Feb 08 08:52:09 AM UTC 25 |
Finished | Feb 08 08:53:07 AM UTC 25 |
Peak memory | 214540 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928076213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.2928076213 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.3168589442 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 362104044 ps |
CPU time | 5.45 seconds |
Started | Feb 08 08:52:07 AM UTC 25 |
Finished | Feb 08 08:52:15 AM UTC 25 |
Peak memory | 212164 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168589442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3168589442 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.1883969293 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 401533638 ps |
CPU time | 5.43 seconds |
Started | Feb 08 08:52:17 AM UTC 25 |
Finished | Feb 08 08:52:25 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883969293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.1883969293 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.594426496 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 12691569636 ps |
CPU time | 80.86 seconds |
Started | Feb 08 08:52:17 AM UTC 25 |
Finished | Feb 08 08:53:42 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594426496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.594426496 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.4092554039 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 379666785 ps |
CPU time | 5.5 seconds |
Started | Feb 08 08:52:19 AM UTC 25 |
Finished | Feb 08 08:52:27 AM UTC 25 |
Peak memory | 211412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092554039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.4092554039 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1703675207 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 81919359 ps |
CPU time | 4.28 seconds |
Started | Feb 08 08:52:18 AM UTC 25 |
Finished | Feb 08 08:52:24 AM UTC 25 |
Peak memory | 212020 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703675207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1703675207 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.1580422132 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 66855579 ps |
CPU time | 7.58 seconds |
Started | Feb 08 08:52:13 AM UTC 25 |
Finished | Feb 08 08:52:24 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580422132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.1580422132 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.3293878519 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 36676956904 ps |
CPU time | 125.23 seconds |
Started | Feb 08 08:52:15 AM UTC 25 |
Finished | Feb 08 08:54:24 AM UTC 25 |
Peak memory | 212360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293878519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3293878519 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.1314334649 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 1747297901 ps |
CPU time | 13.74 seconds |
Started | Feb 08 08:52:15 AM UTC 25 |
Finished | Feb 08 08:52:31 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314334649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1314334649 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3271145322 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 328305775 ps |
CPU time | 9.97 seconds |
Started | Feb 08 08:52:13 AM UTC 25 |
Finished | Feb 08 08:52:25 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271145322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3271145322 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1406004206 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 202523215 ps |
CPU time | 4.75 seconds |
Started | Feb 08 08:52:18 AM UTC 25 |
Finished | Feb 08 08:52:25 AM UTC 25 |
Peak memory | 212016 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406004206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1406004206 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.3880170468 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 9232481 ps |
CPU time | 1.55 seconds |
Started | Feb 08 08:52:12 AM UTC 25 |
Finished | Feb 08 08:52:16 AM UTC 25 |
Peak memory | 211352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880170468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3880170468 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.2059392483 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 4156698544 ps |
CPU time | 12.84 seconds |
Started | Feb 08 08:52:12 AM UTC 25 |
Finished | Feb 08 08:52:27 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059392483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.2059392483 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.3019520565 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 1737128731 ps |
CPU time | 9.89 seconds |
Started | Feb 08 08:52:13 AM UTC 25 |
Finished | Feb 08 08:52:26 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019520565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3019520565 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.3933543616 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 9606885 ps |
CPU time | 1.7 seconds |
Started | Feb 08 08:52:12 AM UTC 25 |
Finished | Feb 08 08:52:16 AM UTC 25 |
Peak memory | 211320 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933543616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.3933543616 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.1620145974 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 672630089 ps |
CPU time | 46.48 seconds |
Started | Feb 08 08:52:19 AM UTC 25 |
Finished | Feb 08 08:53:08 AM UTC 25 |
Peak memory | 213476 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620145974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1620145974 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.909873314 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 315615675 ps |
CPU time | 12.05 seconds |
Started | Feb 08 08:52:21 AM UTC 25 |
Finished | Feb 08 08:52:35 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909873314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.909873314 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.755119942 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 574584652 ps |
CPU time | 136.64 seconds |
Started | Feb 08 08:52:21 AM UTC 25 |
Finished | Feb 08 08:54:41 AM UTC 25 |
Peak memory | 216404 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755119942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.755119942 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.459856499 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 752586134 ps |
CPU time | 97.34 seconds |
Started | Feb 08 08:52:25 AM UTC 25 |
Finished | Feb 08 08:54:05 AM UTC 25 |
Peak memory | 214548 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459856499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.459856499 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.4037111909 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 402917371 ps |
CPU time | 9.82 seconds |
Started | Feb 08 08:52:18 AM UTC 25 |
Finished | Feb 08 08:52:30 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037111909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.4037111909 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.3122453949 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 16401484 ps |
CPU time | 1.53 seconds |
Started | Feb 08 08:42:53 AM UTC 25 |
Finished | Feb 08 08:42:57 AM UTC 25 |
Peak memory | 211420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122453949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3122453949 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.735239363 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 170172967870 ps |
CPU time | 248.71 seconds |
Started | Feb 08 08:42:53 AM UTC 25 |
Finished | Feb 08 08:47:07 AM UTC 25 |
Peak memory | 214608 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735239363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.735239363 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.1356043484 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 125300108 ps |
CPU time | 7.07 seconds |
Started | Feb 08 08:42:56 AM UTC 25 |
Finished | Feb 08 08:43:05 AM UTC 25 |
Peak memory | 212236 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356043484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.1356043484 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.2271468065 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 1004045012 ps |
CPU time | 12.78 seconds |
Started | Feb 08 08:42:54 AM UTC 25 |
Finished | Feb 08 08:43:09 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271468065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2271468065 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2574828041 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 131340516 ps |
CPU time | 4.4 seconds |
Started | Feb 08 08:42:53 AM UTC 25 |
Finished | Feb 08 08:43:00 AM UTC 25 |
Peak memory | 212148 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574828041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2574828041 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.271073904 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 35637427247 ps |
CPU time | 156.45 seconds |
Started | Feb 08 08:42:53 AM UTC 25 |
Finished | Feb 08 08:45:34 AM UTC 25 |
Peak memory | 212352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271073904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.271073904 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.987881925 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 44444374206 ps |
CPU time | 267.12 seconds |
Started | Feb 08 08:42:53 AM UTC 25 |
Finished | Feb 08 08:47:26 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987881925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.987881925 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.2112502021 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 181242217 ps |
CPU time | 8.49 seconds |
Started | Feb 08 08:42:53 AM UTC 25 |
Finished | Feb 08 08:43:05 AM UTC 25 |
Peak memory | 212164 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112502021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2112502021 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.3900450973 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 8271216 ps |
CPU time | 1.45 seconds |
Started | Feb 08 08:42:49 AM UTC 25 |
Finished | Feb 08 08:42:52 AM UTC 25 |
Peak memory | 211164 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900450973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3900450973 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.1302383556 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 7755385144 ps |
CPU time | 14.7 seconds |
Started | Feb 08 08:42:51 AM UTC 25 |
Finished | Feb 08 08:43:08 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302383556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.1302383556 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.2276548253 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 829283531 ps |
CPU time | 9.62 seconds |
Started | Feb 08 08:42:51 AM UTC 25 |
Finished | Feb 08 08:43:03 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276548253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2276548253 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.672595641 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 9556740 ps |
CPU time | 1.51 seconds |
Started | Feb 08 08:42:49 AM UTC 25 |
Finished | Feb 08 08:42:52 AM UTC 25 |
Peak memory | 211300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672595641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.672595641 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.2869109620 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 4249782945 ps |
CPU time | 20.83 seconds |
Started | Feb 08 08:42:56 AM UTC 25 |
Finished | Feb 08 08:43:19 AM UTC 25 |
Peak memory | 212060 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869109620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.2869109620 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.1424770957 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 8470747050 ps |
CPU time | 71.99 seconds |
Started | Feb 08 08:42:56 AM UTC 25 |
Finished | Feb 08 08:44:11 AM UTC 25 |
Peak memory | 214372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424770957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1424770957 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.2300546268 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 522246777 ps |
CPU time | 7.94 seconds |
Started | Feb 08 08:42:56 AM UTC 25 |
Finished | Feb 08 08:43:06 AM UTC 25 |
Peak memory | 212256 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300546268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2300546268 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.679004282 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 499850129 ps |
CPU time | 9.03 seconds |
Started | Feb 08 08:43:03 AM UTC 25 |
Finished | Feb 08 08:43:14 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679004282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.679004282 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.1877597500 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 3497401102 ps |
CPU time | 40.98 seconds |
Started | Feb 08 08:43:03 AM UTC 25 |
Finished | Feb 08 08:43:46 AM UTC 25 |
Peak memory | 212376 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877597500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.1877597500 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.1495427222 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 296606861 ps |
CPU time | 5.3 seconds |
Started | Feb 08 08:43:05 AM UTC 25 |
Finished | Feb 08 08:43:12 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495427222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.1495427222 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.1730810276 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 22983847 ps |
CPU time | 2.77 seconds |
Started | Feb 08 08:43:03 AM UTC 25 |
Finished | Feb 08 08:43:08 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730810276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1730810276 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.557334925 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 76526875 ps |
CPU time | 9.37 seconds |
Started | Feb 08 08:42:59 AM UTC 25 |
Finished | Feb 08 08:43:10 AM UTC 25 |
Peak memory | 212312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557334925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.557334925 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.1769984719 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 54774124240 ps |
CPU time | 181.56 seconds |
Started | Feb 08 08:43:01 AM UTC 25 |
Finished | Feb 08 08:46:06 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769984719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1769984719 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.2960126072 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 3392980287 ps |
CPU time | 41.73 seconds |
Started | Feb 08 08:43:01 AM UTC 25 |
Finished | Feb 08 08:43:45 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960126072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2960126072 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.971110876 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 33883752 ps |
CPU time | 2.17 seconds |
Started | Feb 08 08:43:01 AM UTC 25 |
Finished | Feb 08 08:43:05 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971110876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.971110876 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.1819055015 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 491393321 ps |
CPU time | 10.02 seconds |
Started | Feb 08 08:43:03 AM UTC 25 |
Finished | Feb 08 08:43:15 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819055015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1819055015 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2500432404 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 17146454 ps |
CPU time | 1.73 seconds |
Started | Feb 08 08:42:58 AM UTC 25 |
Finished | Feb 08 08:43:02 AM UTC 25 |
Peak memory | 211424 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500432404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2500432404 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3066138970 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 3020306330 ps |
CPU time | 17.19 seconds |
Started | Feb 08 08:42:59 AM UTC 25 |
Finished | Feb 08 08:43:18 AM UTC 25 |
Peak memory | 212564 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066138970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3066138970 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.2691428586 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 749702848 ps |
CPU time | 10.67 seconds |
Started | Feb 08 08:42:59 AM UTC 25 |
Finished | Feb 08 08:43:11 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691428586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2691428586 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.869999592 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 11229126 ps |
CPU time | 1.34 seconds |
Started | Feb 08 08:42:59 AM UTC 25 |
Finished | Feb 08 08:43:02 AM UTC 25 |
Peak memory | 211300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869999592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.869999592 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.505088517 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 3935751569 ps |
CPU time | 94.31 seconds |
Started | Feb 08 08:43:05 AM UTC 25 |
Finished | Feb 08 08:44:42 AM UTC 25 |
Peak memory | 214412 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505088517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_b uild_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.505088517 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.1306905719 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 6009008127 ps |
CPU time | 106.93 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:44:57 AM UTC 25 |
Peak memory | 214420 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306905719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.1306905719 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.474311213 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 5632799329 ps |
CPU time | 216.83 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:46:48 AM UTC 25 |
Peak memory | 216508 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474311213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.474311213 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.3933616252 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 390787479 ps |
CPU time | 73.14 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:44:23 AM UTC 25 |
Peak memory | 214512 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933616252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.3933616252 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.1232942719 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 132644679 ps |
CPU time | 5.41 seconds |
Started | Feb 08 08:43:05 AM UTC 25 |
Finished | Feb 08 08:43:12 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232942719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1232942719 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1864668923 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 130095054 ps |
CPU time | 11.77 seconds |
Started | Feb 08 08:43:12 AM UTC 25 |
Finished | Feb 08 08:43:25 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864668923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1864668923 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.2257110354 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 15429925907 ps |
CPU time | 180.34 seconds |
Started | Feb 08 08:43:12 AM UTC 25 |
Finished | Feb 08 08:46:16 AM UTC 25 |
Peak memory | 214180 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257110354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.2257110354 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.207108147 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 93134007 ps |
CPU time | 5.53 seconds |
Started | Feb 08 08:43:14 AM UTC 25 |
Finished | Feb 08 08:43:21 AM UTC 25 |
Peak memory | 212284 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207108147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.207108147 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.3038572949 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 1038663988 ps |
CPU time | 12.82 seconds |
Started | Feb 08 08:43:12 AM UTC 25 |
Finished | Feb 08 08:43:26 AM UTC 25 |
Peak memory | 212032 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038572949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_bui ld_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.3038572949 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.1072056960 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 431316884 ps |
CPU time | 9.34 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:43:19 AM UTC 25 |
Peak memory | 212144 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072056960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.1072056960 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.52828079 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 30718550610 ps |
CPU time | 220.34 seconds |
Started | Feb 08 08:43:09 AM UTC 25 |
Finished | Feb 08 08:46:54 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52828079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_T EST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.52828079 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2185683392 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 165771869784 ps |
CPU time | 225.37 seconds |
Started | Feb 08 08:43:09 AM UTC 25 |
Finished | Feb 08 08:46:59 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185683392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2185683392 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.3778561707 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 45850926 ps |
CPU time | 4.41 seconds |
Started | Feb 08 08:43:09 AM UTC 25 |
Finished | Feb 08 08:43:15 AM UTC 25 |
Peak memory | 212296 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778561707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.3778561707 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.2477458846 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 524926352 ps |
CPU time | 10.04 seconds |
Started | Feb 08 08:43:12 AM UTC 25 |
Finished | Feb 08 08:43:23 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477458846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2477458846 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.135100215 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 42217176 ps |
CPU time | 2.08 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:43:11 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135100215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_ mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.135100215 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2172052629 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 2736760618 ps |
CPU time | 13.07 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:43:22 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172052629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2172052629 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.353597113 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 2100290584 ps |
CPU time | 12.62 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:43:22 AM UTC 25 |
Peak memory | 212504 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353597113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.353597113 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.2857519301 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 8962753 ps |
CPU time | 1.44 seconds |
Started | Feb 08 08:43:07 AM UTC 25 |
Finished | Feb 08 08:43:11 AM UTC 25 |
Peak memory | 211076 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857519301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.2857519301 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.3281477494 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 6557119100 ps |
CPU time | 26.3 seconds |
Started | Feb 08 08:43:14 AM UTC 25 |
Finished | Feb 08 08:43:42 AM UTC 25 |
Peak memory | 211848 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281477494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3281477494 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3062239664 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1327917188 ps |
CPU time | 21.27 seconds |
Started | Feb 08 08:43:18 AM UTC 25 |
Finished | Feb 08 08:43:41 AM UTC 25 |
Peak memory | 212372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062239664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3062239664 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.1566758683 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 564042149 ps |
CPU time | 103.1 seconds |
Started | Feb 08 08:43:14 AM UTC 25 |
Finished | Feb 08 08:45:00 AM UTC 25 |
Peak memory | 215768 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566758683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.1566758683 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.3106205990 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 7215898162 ps |
CPU time | 99.69 seconds |
Started | Feb 08 08:43:18 AM UTC 25 |
Finished | Feb 08 08:45:00 AM UTC 25 |
Peak memory | 214416 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106205990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.3106205990 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.1529203423 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 789308123 ps |
CPU time | 9.66 seconds |
Started | Feb 08 08:43:14 AM UTC 25 |
Finished | Feb 08 08:43:26 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529203423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1529203423 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.1380477368 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 1654071871 ps |
CPU time | 24.5 seconds |
Started | Feb 08 08:43:22 AM UTC 25 |
Finished | Feb 08 08:43:49 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380477368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/covera ge/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.1380477368 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.2692599896 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 45391790783 ps |
CPU time | 355.33 seconds |
Started | Feb 08 08:43:23 AM UTC 25 |
Finished | Feb 08 08:49:24 AM UTC 25 |
Peak memory | 218132 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692599896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/ coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.2692599896 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3988732822 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 847595702 ps |
CPU time | 8.95 seconds |
Started | Feb 08 08:43:25 AM UTC 25 |
Finished | Feb 08 08:43:35 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988732822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3988732822 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.882304602 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 8755180 ps |
CPU time | 1.5 seconds |
Started | Feb 08 08:43:24 AM UTC 25 |
Finished | Feb 08 08:43:27 AM UTC 25 |
Peak memory | 211360 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882304602 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.882304602 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.1574017246 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 49414408 ps |
CPU time | 4.75 seconds |
Started | Feb 08 08:43:20 AM UTC 25 |
Finished | Feb 08 08:43:26 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574017246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.1574017246 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.655713416 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 15442114599 ps |
CPU time | 120.85 seconds |
Started | Feb 08 08:43:22 AM UTC 25 |
Finished | Feb 08 08:45:26 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655713416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.655713416 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3193513862 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 7658886598 ps |
CPU time | 67.65 seconds |
Started | Feb 08 08:43:22 AM UTC 25 |
Finished | Feb 08 08:44:32 AM UTC 25 |
Peak memory | 212556 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193513862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3193513862 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.905836632 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 56162277 ps |
CPU time | 6.48 seconds |
Started | Feb 08 08:43:20 AM UTC 25 |
Finished | Feb 08 08:43:28 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905836632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.905836632 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.811999071 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 1125737866 ps |
CPU time | 10.02 seconds |
Started | Feb 08 08:43:24 AM UTC 25 |
Finished | Feb 08 08:43:36 AM UTC 25 |
Peak memory | 212500 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811999071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.811999071 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.1289309410 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 18294247 ps |
CPU time | 1.41 seconds |
Started | Feb 08 08:43:18 AM UTC 25 |
Finished | Feb 08 08:43:20 AM UTC 25 |
Peak memory | 211324 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289309410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1289309410 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.1618267175 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1928678365 ps |
CPU time | 12.43 seconds |
Started | Feb 08 08:43:20 AM UTC 25 |
Finished | Feb 08 08:43:34 AM UTC 25 |
Peak memory | 212308 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618267175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.1618267175 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2517553803 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 14760421605 ps |
CPU time | 21.14 seconds |
Started | Feb 08 08:43:20 AM UTC 25 |
Finished | Feb 08 08:43:43 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517553803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2517553803 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.854256364 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 17707910 ps |
CPU time | 1.73 seconds |
Started | Feb 08 08:43:18 AM UTC 25 |
Finished | Feb 08 08:43:21 AM UTC 25 |
Peak memory | 211300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854256364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cover age/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.854256364 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.2561857674 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 16184285377 ps |
CPU time | 57.3 seconds |
Started | Feb 08 08:43:26 AM UTC 25 |
Finished | Feb 08 08:44:25 AM UTC 25 |
Peak memory | 214488 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561857674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.2561857674 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.3111045399 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 578897367 ps |
CPU time | 40.5 seconds |
Started | Feb 08 08:43:27 AM UTC 25 |
Finished | Feb 08 08:44:10 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111045399 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3111045399 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.400156161 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 603450126 ps |
CPU time | 86.6 seconds |
Started | Feb 08 08:43:26 AM UTC 25 |
Finished | Feb 08 08:44:55 AM UTC 25 |
Peak memory | 216372 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400156161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.400156161 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.4213540977 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 460781278 ps |
CPU time | 50.73 seconds |
Started | Feb 08 08:43:27 AM UTC 25 |
Finished | Feb 08 08:44:20 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213540977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.4213540977 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.2868359563 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 616970144 ps |
CPU time | 4.22 seconds |
Started | Feb 08 08:43:24 AM UTC 25 |
Finished | Feb 08 08:43:30 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868359563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.2868359563 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.455156024 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 3151897035 ps |
CPU time | 18.32 seconds |
Started | Feb 08 08:43:34 AM UTC 25 |
Finished | Feb 08 08:43:54 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455156024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverag e/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.455156024 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_access_same_device/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.832211536 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 6841298180 ps |
CPU time | 62.89 seconds |
Started | Feb 08 08:43:36 AM UTC 25 |
Finished | Feb 08 08:44:41 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832211536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST _SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/c overage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.832211536 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.4054334829 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 489854937 ps |
CPU time | 9.88 seconds |
Started | Feb 08 08:43:42 AM UTC 25 |
Finished | Feb 08 08:43:54 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054334829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/x bar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.4054334829 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.874737558 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 2354461228 ps |
CPU time | 16.6 seconds |
Started | Feb 08 08:43:40 AM UTC 25 |
Finished | Feb 08 08:43:58 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874737558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.874737558 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_error_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.4002388614 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 2302242548 ps |
CPU time | 16.96 seconds |
Started | Feb 08 08:43:32 AM UTC 25 |
Finished | Feb 08 08:43:51 AM UTC 25 |
Peak memory | 212496 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002388614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_buil d_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.4002388614 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_random/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.1434106436 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 43876939118 ps |
CPU time | 212.93 seconds |
Started | Feb 08 08:43:34 AM UTC 25 |
Finished | Feb 08 08:47:11 AM UTC 25 |
Peak memory | 212364 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434106436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage /xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1434106436 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.3432618338 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 59510879054 ps |
CPU time | 127.1 seconds |
Started | Feb 08 08:43:34 AM UTC 25 |
Finished | Feb 08 08:45:44 AM UTC 25 |
Peak memory | 212560 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432618338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xba r_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3432618338 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.3482101599 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 23708405 ps |
CPU time | 4.24 seconds |
Started | Feb 08 08:43:33 AM UTC 25 |
Finished | Feb 08 08:43:39 AM UTC 25 |
Peak memory | 212300 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482101599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cov erage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.3482101599 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.1057010884 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 3419568268 ps |
CPU time | 9.43 seconds |
Started | Feb 08 08:43:37 AM UTC 25 |
Finished | Feb 08 08:43:48 AM UTC 25 |
Peak memory | 212368 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057010884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1057010884 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_same_source/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.4211396034 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 273053045 ps |
CPU time | 2.31 seconds |
Started | Feb 08 08:43:27 AM UTC 25 |
Finished | Feb 08 08:43:31 AM UTC 25 |
Peak memory | 212312 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211396034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build _mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.4211396034 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_smoke/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1762323499 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 4005511828 ps |
CPU time | 22.44 seconds |
Started | Feb 08 08:43:29 AM UTC 25 |
Finished | Feb 08 08:43:53 AM UTC 25 |
Peak memory | 212344 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay= 1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762323499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/ xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1762323499 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.3676571038 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 1535306674 ps |
CPU time | 13.07 seconds |
Started | Feb 08 08:43:31 AM UTC 25 |
Finished | Feb 08 08:43:46 AM UTC 25 |
Peak memory | 212492 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=10 00 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676571038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TES T_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3676571038 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.2304973722 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 9035864 ps |
CPU time | 1.76 seconds |
Started | Feb 08 08:43:29 AM UTC 25 |
Finished | Feb 08 08:43:32 AM UTC 25 |
Peak memory | 211280 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304973722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/cove rage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.2304973722 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.4011874227 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 238695897 ps |
CPU time | 32.69 seconds |
Started | Feb 08 08:43:43 AM UTC 25 |
Finished | Feb 08 08:44:18 AM UTC 25 |
Peak memory | 214356 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011874227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_ build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4011874227 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_stress_all/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1225579662 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 1436883772 ps |
CPU time | 68.49 seconds |
Started | Feb 08 08:43:45 AM UTC 25 |
Finished | Feb 08 08:44:56 AM UTC 25 |
Peak memory | 214352 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225579662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar _build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1225579662 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.115705259 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 717030808 ps |
CPU time | 112.23 seconds |
Started | Feb 08 08:43:44 AM UTC 25 |
Finished | Feb 08 08:45:39 AM UTC 25 |
Peak memory | 216588 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115705259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=x bar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.115705259 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.3770275146 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 461661464 ps |
CPU time | 79.95 seconds |
Started | Feb 08 08:43:46 AM UTC 25 |
Finished | Feb 08 08:45:09 AM UTC 25 |
Peak memory | 216404 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770275146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ =xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.3770275146 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
Test location | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.2435643288 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 150103750 ps |
CPU time | 3.18 seconds |
Started | Feb 08 08:43:41 AM UTC 25 |
Finished | Feb 08 08:43:46 AM UTC 25 |
Peak memory | 212304 kb |
Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
User | miguelosorio |
Command | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435643288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ= xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/coverage/xb ar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2435643288 |
Directory | /workspaces/repo/scratch/os_regression/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest |
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