| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.24 | 100.00 | 95.42 | 100.00 | 100.00 | 100.00 | 100.00 |
| T775 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.317100414 | Oct 14 09:19:36 PM UTC 24 | Oct 14 09:19:40 PM UTC 24 | 45188951 ps | ||
| T776 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1219908423 | Oct 14 09:18:50 PM UTC 24 | Oct 14 09:19:40 PM UTC 24 | 15234553873 ps | ||
| T777 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.2617699231 | Oct 14 09:18:40 PM UTC 24 | Oct 14 09:19:42 PM UTC 24 | 11298496274 ps | ||
| T778 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.108459502 | Oct 14 09:19:39 PM UTC 24 | Oct 14 09:19:42 PM UTC 24 | 38444585 ps | ||
| T779 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1521566620 | Oct 14 09:18:55 PM UTC 24 | Oct 14 09:19:43 PM UTC 24 | 8998414133 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.524751852 | Oct 14 09:19:36 PM UTC 24 | Oct 14 09:19:44 PM UTC 24 | 236552182 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.1664054280 | Oct 14 09:19:36 PM UTC 24 | Oct 14 09:19:44 PM UTC 24 | 109486524 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.196364318 | Oct 14 09:19:18 PM UTC 24 | Oct 14 09:19:45 PM UTC 24 | 521829633 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2326961294 | Oct 14 09:19:40 PM UTC 24 | Oct 14 09:19:45 PM UTC 24 | 46341143 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3936566559 | Oct 14 09:19:35 PM UTC 24 | Oct 14 09:19:45 PM UTC 24 | 2269718194 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2533061114 | Oct 14 09:18:33 PM UTC 24 | Oct 14 09:19:45 PM UTC 24 | 3153590728 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.331069627 | Oct 14 09:19:43 PM UTC 24 | Oct 14 09:19:46 PM UTC 24 | 15353452 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.1052291332 | Oct 14 09:19:43 PM UTC 24 | Oct 14 09:19:46 PM UTC 24 | 451661744 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3044360693 | Oct 14 09:19:11 PM UTC 24 | Oct 14 09:19:46 PM UTC 24 | 712870166 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2842075203 | Oct 14 09:19:40 PM UTC 24 | Oct 14 09:19:47 PM UTC 24 | 668713414 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.3146943009 | Oct 14 09:19:36 PM UTC 24 | Oct 14 09:19:47 PM UTC 24 | 170738568 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2923131977 | Oct 14 09:18:59 PM UTC 24 | Oct 14 09:19:47 PM UTC 24 | 2290221948 ps | ||
| T237 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.491548370 | Oct 14 09:17:08 PM UTC 24 | Oct 14 09:19:50 PM UTC 24 | 20596129070 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4233876483 | Oct 14 09:19:35 PM UTC 24 | Oct 14 09:19:50 PM UTC 24 | 4509348731 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.190684094 | Oct 14 09:18:29 PM UTC 24 | Oct 14 09:19:50 PM UTC 24 | 16068095019 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1331982294 | Oct 14 09:19:40 PM UTC 24 | Oct 14 09:19:51 PM UTC 24 | 573916021 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3844308956 | Oct 14 09:19:43 PM UTC 24 | Oct 14 09:19:52 PM UTC 24 | 1479872022 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.312702638 | Oct 14 09:19:47 PM UTC 24 | Oct 14 09:19:52 PM UTC 24 | 160282429 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1929182391 | Oct 14 09:19:15 PM UTC 24 | Oct 14 09:19:53 PM UTC 24 | 7067456837 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.118498088 | Oct 14 09:19:47 PM UTC 24 | Oct 14 09:19:54 PM UTC 24 | 78844430 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.60484383 | Oct 14 09:19:47 PM UTC 24 | Oct 14 09:19:54 PM UTC 24 | 3550884337 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.1147624588 | Oct 14 09:19:47 PM UTC 24 | Oct 14 09:19:54 PM UTC 24 | 287616797 ps | ||
| T34 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.878913310 | Oct 14 09:18:50 PM UTC 24 | Oct 14 09:19:54 PM UTC 24 | 41518855845 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3104488746 | Oct 14 09:19:51 PM UTC 24 | Oct 14 09:19:54 PM UTC 24 | 156338306 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.259186116 | Oct 14 09:19:06 PM UTC 24 | Oct 14 09:19:54 PM UTC 24 | 6190289934 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3996600869 | Oct 14 09:18:46 PM UTC 24 | Oct 14 09:19:54 PM UTC 24 | 16355383852 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.4026777949 | Oct 14 09:19:51 PM UTC 24 | Oct 14 09:19:55 PM UTC 24 | 286521482 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.384959223 | Oct 14 09:19:40 PM UTC 24 | Oct 14 09:19:55 PM UTC 24 | 669971671 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.686881499 | Oct 14 09:19:36 PM UTC 24 | Oct 14 09:19:55 PM UTC 24 | 4316353905 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.373482644 | Oct 14 09:18:46 PM UTC 24 | Oct 14 09:19:56 PM UTC 24 | 1462158252 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.914565457 | Oct 14 09:19:51 PM UTC 24 | Oct 14 09:19:56 PM UTC 24 | 983973243 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3788654322 | Oct 14 09:19:43 PM UTC 24 | Oct 14 09:19:58 PM UTC 24 | 17371100703 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3961993951 | Oct 14 09:19:55 PM UTC 24 | Oct 14 09:19:58 PM UTC 24 | 8748665 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.972987935 | Oct 14 09:18:50 PM UTC 24 | Oct 14 09:19:58 PM UTC 24 | 3231966792 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3718867887 | Oct 14 09:19:11 PM UTC 24 | Oct 14 09:19:58 PM UTC 24 | 4886434658 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.1302409109 | Oct 14 09:19:06 PM UTC 24 | Oct 14 09:19:59 PM UTC 24 | 14572399690 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2833028133 | Oct 14 09:19:56 PM UTC 24 | Oct 14 09:19:59 PM UTC 24 | 43103771 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3294394722 | Oct 14 09:19:43 PM UTC 24 | Oct 14 09:20:01 PM UTC 24 | 144909314 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2113301924 | Oct 14 09:19:55 PM UTC 24 | Oct 14 09:20:02 PM UTC 24 | 138779673 ps | ||
| T128 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.3962631419 | Oct 14 09:18:55 PM UTC 24 | Oct 14 09:20:02 PM UTC 24 | 24586038089 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2301394284 | Oct 14 09:19:15 PM UTC 24 | Oct 14 09:20:02 PM UTC 24 | 7320089957 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.3820982288 | Oct 14 09:20:06 PM UTC 24 | Oct 14 09:20:33 PM UTC 24 | 2735224559 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2685555219 | Oct 14 09:19:55 PM UTC 24 | Oct 14 09:20:03 PM UTC 24 | 39444743 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.259911430 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:20:03 PM UTC 24 | 18571237 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.4113226249 | Oct 14 09:20:00 PM UTC 24 | Oct 14 09:20:03 PM UTC 24 | 18514164 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.38210310 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:20:03 PM UTC 24 | 22542565 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3116584259 | Oct 14 09:19:56 PM UTC 24 | Oct 14 09:20:04 PM UTC 24 | 1202413626 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3945315423 | Oct 14 09:19:31 PM UTC 24 | Oct 14 09:20:05 PM UTC 24 | 3386471984 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.114638516 | Oct 14 09:20:00 PM UTC 24 | Oct 14 09:20:05 PM UTC 24 | 209749009 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2622278340 | Oct 14 09:19:55 PM UTC 24 | Oct 14 09:20:05 PM UTC 24 | 3025772365 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.3619633284 | Oct 14 09:19:56 PM UTC 24 | Oct 14 09:20:05 PM UTC 24 | 796200044 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3407212838 | Oct 14 09:19:55 PM UTC 24 | Oct 14 09:20:05 PM UTC 24 | 993864150 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2249274090 | Oct 14 09:18:22 PM UTC 24 | Oct 14 09:20:06 PM UTC 24 | 22198957589 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4115333848 | Oct 14 09:17:41 PM UTC 24 | Oct 14 09:20:06 PM UTC 24 | 1254191411 ps | ||
| T828 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2299933740 | Oct 14 09:20:03 PM UTC 24 | Oct 14 09:20:06 PM UTC 24 | 18515200 ps | ||
| T829 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.255501272 | Oct 14 09:18:24 PM UTC 24 | Oct 14 09:20:06 PM UTC 24 | 1428240640 ps | ||
| T830 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2066498830 | Oct 14 09:20:03 PM UTC 24 | Oct 14 09:20:07 PM UTC 24 | 242987954 ps | ||
| T831 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.220896520 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:20:08 PM UTC 24 | 410423428 ps | ||
| T832 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.352151241 | Oct 14 09:19:31 PM UTC 24 | Oct 14 09:20:09 PM UTC 24 | 226449692 ps | ||
| T833 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2707112181 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:20:09 PM UTC 24 | 58726786 ps | ||
| T834 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3650980567 | Oct 14 09:20:06 PM UTC 24 | Oct 14 09:20:10 PM UTC 24 | 67987611 ps | ||
| T835 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.112580025 | Oct 14 09:19:56 PM UTC 24 | Oct 14 09:20:10 PM UTC 24 | 4925717125 ps | ||
| T836 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2018487474 | Oct 14 09:15:20 PM UTC 24 | Oct 14 09:20:10 PM UTC 24 | 20650883402 ps | ||
| T837 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3727749690 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:20:10 PM UTC 24 | 1789312903 ps | ||
| T838 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2576400825 | Oct 14 09:20:03 PM UTC 24 | Oct 14 09:20:10 PM UTC 24 | 362336496 ps | ||
| T129 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2284000066 | Oct 14 09:16:54 PM UTC 24 | Oct 14 09:20:10 PM UTC 24 | 39093932258 ps | ||
| T130 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.3640479628 | Oct 14 09:19:47 PM UTC 24 | Oct 14 09:20:10 PM UTC 24 | 3876676699 ps | ||
| T839 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1821302047 | Oct 14 09:20:06 PM UTC 24 | Oct 14 09:20:11 PM UTC 24 | 782689873 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1542023322 | Oct 14 09:19:36 PM UTC 24 | Oct 14 09:20:11 PM UTC 24 | 4602360979 ps | ||
| T840 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1218646908 | Oct 14 09:19:36 PM UTC 24 | Oct 14 09:20:12 PM UTC 24 | 14557860528 ps | ||
| T841 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1351438664 | Oct 14 09:19:11 PM UTC 24 | Oct 14 09:20:13 PM UTC 24 | 394365825 ps | ||
| T842 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3609497800 | Oct 14 09:20:10 PM UTC 24 | Oct 14 09:20:13 PM UTC 24 | 8479932 ps | ||
| T131 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3953947925 | Oct 14 09:18:50 PM UTC 24 | Oct 14 09:20:14 PM UTC 24 | 25468236812 ps | ||
| T843 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.570911957 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:20:14 PM UTC 24 | 2160270828 ps | ||
| T844 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3144073777 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:20:14 PM UTC 24 | 109741926 ps | ||
| T845 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1958406808 | Oct 14 09:17:29 PM UTC 24 | Oct 14 09:20:15 PM UTC 24 | 6341981765 ps | ||
| T846 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.240570270 | Oct 14 09:19:56 PM UTC 24 | Oct 14 09:20:15 PM UTC 24 | 1716300687 ps | ||
| T847 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.591393738 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:20:15 PM UTC 24 | 29258792 ps | ||
| T848 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.3011079867 | Oct 14 09:20:03 PM UTC 24 | Oct 14 09:20:16 PM UTC 24 | 1559451843 ps | ||
| T849 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2821729242 | Oct 14 09:20:00 PM UTC 24 | Oct 14 09:20:16 PM UTC 24 | 2317169096 ps | ||
| T850 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1297401455 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:17 PM UTC 24 | 10568883 ps | ||
| T851 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1000438197 | Oct 14 09:20:06 PM UTC 24 | Oct 14 09:20:17 PM UTC 24 | 1209513036 ps | ||
| T852 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.446510103 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:17 PM UTC 24 | 12478920 ps | ||
| T157 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2823875385 | Oct 14 09:16:38 PM UTC 24 | Oct 14 09:20:17 PM UTC 24 | 26592395215 ps | ||
| T853 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1399026509 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:20:17 PM UTC 24 | 57298583 ps | ||
| T854 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2568256887 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:20:18 PM UTC 24 | 65829008 ps | ||
| T855 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3320413640 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:18 PM UTC 24 | 186868026 ps | ||
| T856 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.593225418 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:19 PM UTC 24 | 40939667 ps | ||
| T857 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2288437125 | Oct 14 09:19:47 PM UTC 24 | Oct 14 09:20:20 PM UTC 24 | 8792511283 ps | ||
| T858 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2415314789 | Oct 14 09:20:10 PM UTC 24 | Oct 14 09:20:21 PM UTC 24 | 4245532291 ps | ||
| T859 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1156573130 | Oct 14 09:20:10 PM UTC 24 | Oct 14 09:20:21 PM UTC 24 | 1263272044 ps | ||
| T860 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2122531595 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:20:22 PM UTC 24 | 70160255 ps | ||
| T861 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1664924358 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:20:23 PM UTC 24 | 7569870 ps | ||
| T862 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4173085515 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:25 PM UTC 24 | 4984085746 ps | ||
| T863 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.3793077842 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:20:25 PM UTC 24 | 1301280626 ps | ||
| T864 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1356411906 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:26 PM UTC 24 | 2412444280 ps | ||
| T865 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1191113031 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:27 PM UTC 24 | 321798892 ps | ||
| T866 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2909337022 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:20:27 PM UTC 24 | 845726727 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1920219687 | Oct 14 09:18:13 PM UTC 24 | Oct 14 09:20:28 PM UTC 24 | 1038851691 ps | ||
| T35 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3139634950 | Oct 14 09:20:18 PM UTC 24 | Oct 14 09:20:29 PM UTC 24 | 61292420 ps | ||
| T867 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2216779401 | Oct 14 09:19:26 PM UTC 24 | Oct 14 09:20:29 PM UTC 24 | 13615130792 ps | ||
| T868 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1666008330 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:20:29 PM UTC 24 | 1491410162 ps | ||
| T869 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2564212537 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:30 PM UTC 24 | 1100737524 ps | ||
| T870 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2486305568 | Oct 14 09:19:15 PM UTC 24 | Oct 14 09:20:30 PM UTC 24 | 20241035896 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1521929430 | Oct 14 09:18:07 PM UTC 24 | Oct 14 09:20:30 PM UTC 24 | 16534357078 ps | ||
| T871 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1074279893 | Oct 14 09:19:18 PM UTC 24 | Oct 14 09:20:31 PM UTC 24 | 532595772 ps | ||
| T872 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2548321137 | Oct 14 09:20:18 PM UTC 24 | Oct 14 09:20:33 PM UTC 24 | 694347540 ps | ||
| T873 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1200892114 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:20:33 PM UTC 24 | 1086507446 ps | ||
| T874 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.4228225846 | Oct 14 09:19:26 PM UTC 24 | Oct 14 09:20:33 PM UTC 24 | 15570008674 ps | ||
| T132 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3763183628 | Oct 14 09:18:29 PM UTC 24 | Oct 14 09:20:34 PM UTC 24 | 18434941294 ps | ||
| T875 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.991672032 | Oct 14 09:19:22 PM UTC 24 | Oct 14 09:20:36 PM UTC 24 | 10005048010 ps | ||
| T876 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1727522775 | Oct 14 09:20:18 PM UTC 24 | Oct 14 09:20:36 PM UTC 24 | 8334929533 ps | ||
| T238 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.574608881 | Oct 14 09:18:41 PM UTC 24 | Oct 14 09:20:38 PM UTC 24 | 23114498151 ps | ||
| T877 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3970160540 | Oct 14 09:20:18 PM UTC 24 | Oct 14 09:20:39 PM UTC 24 | 3130994958 ps | ||
| T142 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1005355372 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:20:47 PM UTC 24 | 53003979698 ps | ||
| T878 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3917714923 | Oct 14 09:20:00 PM UTC 24 | Oct 14 09:20:48 PM UTC 24 | 718544117 ps | ||
| T879 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.157478086 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:20:51 PM UTC 24 | 1442950454 ps | ||
| T880 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2163518911 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:20:52 PM UTC 24 | 544078705 ps | ||
| T881 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1461738859 | Oct 14 09:19:26 PM UTC 24 | Oct 14 09:20:52 PM UTC 24 | 60554733622 ps | ||
| T882 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3248945847 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:20:53 PM UTC 24 | 9326715819 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.371463008 | Oct 14 09:19:06 PM UTC 24 | Oct 14 09:20:55 PM UTC 24 | 27567954420 ps | ||
| T883 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3792066538 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:20:56 PM UTC 24 | 18861350738 ps | ||
| T884 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.49561453 | Oct 14 09:19:31 PM UTC 24 | Oct 14 09:20:57 PM UTC 24 | 3693197462 ps | ||
| T885 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2880860521 | Oct 14 09:19:31 PM UTC 24 | Oct 14 09:20:57 PM UTC 24 | 13943664945 ps | ||
| T158 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1691793336 | Oct 14 09:20:18 PM UTC 24 | Oct 14 09:20:59 PM UTC 24 | 9033419884 ps | ||
| T886 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2099318796 | Oct 14 09:19:56 PM UTC 24 | Oct 14 09:20:59 PM UTC 24 | 47800512270 ps | ||
| T133 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.614746270 | Oct 14 09:19:47 PM UTC 24 | Oct 14 09:21:01 PM UTC 24 | 9011888678 ps | ||
| T887 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.4095643400 | Oct 14 09:19:51 PM UTC 24 | Oct 14 09:21:03 PM UTC 24 | 10567539550 ps | ||
| T888 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3028203041 | Oct 14 09:20:00 PM UTC 24 | Oct 14 09:21:04 PM UTC 24 | 955953432 ps | ||
| T889 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1099522681 | Oct 14 09:19:51 PM UTC 24 | Oct 14 09:21:05 PM UTC 24 | 9348366931 ps | ||
| T890 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2836222968 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:21:07 PM UTC 24 | 9462738321 ps | ||
| T891 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.559369774 | Oct 14 09:19:51 PM UTC 24 | Oct 14 09:21:07 PM UTC 24 | 15655860457 ps | ||
| T892 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2385861678 | Oct 14 09:20:19 PM UTC 24 | Oct 14 09:21:08 PM UTC 24 | 221096903 ps | ||
| T893 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.439238768 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:21:12 PM UTC 24 | 2293546586 ps | ||
| T894 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4183288073 | Oct 14 09:18:50 PM UTC 24 | Oct 14 09:21:13 PM UTC 24 | 18817515790 ps | ||
| T895 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1874529795 | Oct 14 09:19:40 PM UTC 24 | Oct 14 09:21:16 PM UTC 24 | 5926114264 ps | ||
| T896 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1965001140 | Oct 14 09:20:00 PM UTC 24 | Oct 14 09:21:17 PM UTC 24 | 1540739423 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.317936535 | Oct 14 09:20:03 PM UTC 24 | Oct 14 09:21:19 PM UTC 24 | 28341144098 ps | ||
| T897 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2793969297 | Oct 14 09:20:14 PM UTC 24 | Oct 14 09:21:24 PM UTC 24 | 22601629305 ps | ||
| T898 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1199652269 | Oct 14 09:20:06 PM UTC 24 | Oct 14 09:21:34 PM UTC 24 | 4214617777 ps | ||
| T899 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1035302594 | Oct 14 09:20:01 PM UTC 24 | Oct 14 09:21:35 PM UTC 24 | 16679969195 ps | ||
| T900 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.341872350 | Oct 14 09:20:11 PM UTC 24 | Oct 14 09:22:01 PM UTC 24 | 24903879834 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4045482991 | Oct 14 09:17:58 PM UTC 24 | Oct 14 09:22:12 PM UTC 24 | 59159897645 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1643409267 | Oct 14 09:19:51 PM UTC 24 | Oct 14 09:23:09 PM UTC 24 | 952152399 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3575824766 | Oct 14 09:20:06 PM UTC 24 | Oct 14 09:23:43 PM UTC 24 | 6650975881 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_unmapped_addr.978583631 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 330349292 ps |
| CPU time | 3.69 seconds |
| Started | Oct 14 09:12:07 PM UTC 24 |
| Finished | Oct 14 09:12:12 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978583631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.978583631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device_slow_rsp.1198745699 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 64091908003 ps |
| CPU time | 148.67 seconds |
| Started | Oct 14 09:13:32 PM UTC 24 |
| Finished | Oct 14 09:16:03 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198745699 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device_slow_rsp.1198745699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device_slow_rsp.321408112 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 27349515605 ps |
| CPU time | 178.6 seconds |
| Started | Oct 14 09:14:51 PM UTC 24 |
| Finished | Oct 14 09:17:53 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321408112 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device_slow_rsp.321408112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device_slow_rsp.2972929545 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 127931723183 ps |
| CPU time | 180.92 seconds |
| Started | Oct 14 09:13:18 PM UTC 24 |
| Finished | Oct 14 09:16:22 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972929545 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device_slow_rsp.2972929545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device_slow_rsp.4045482991 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 59159897645 ps |
| CPU time | 250.63 seconds |
| Started | Oct 14 09:17:58 PM UTC 24 |
| Finished | Oct 14 09:22:12 PM UTC 24 |
| Peak memory | 216720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045482991 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device_slow_rsp.4045482991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random.735922066 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 33277790 ps |
| CPU time | 1.46 seconds |
| Started | Oct 14 09:12:03 PM UTC 24 |
| Finished | Oct 14 09:12:06 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735922066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random.735922066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device_slow_rsp.2914061178 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 17830710279 ps |
| CPU time | 158.81 seconds |
| Started | Oct 14 09:12:55 PM UTC 24 |
| Finished | Oct 14 09:15:37 PM UTC 24 |
| Peak memory | 213152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914061178 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device_slow_rsp.2914061178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_reset_error.3442297958 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 217815166 ps |
| CPU time | 26.1 seconds |
| Started | Oct 14 09:12:24 PM UTC 24 |
| Finished | Oct 14 09:12:51 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442297958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_reset_error.3442297958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device_slow_rsp.1792678025 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 41202158559 ps |
| CPU time | 85.48 seconds |
| Started | Oct 14 09:12:05 PM UTC 24 |
| Finished | Oct 14 09:13:32 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792678025 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device_slow_rsp.1792678025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_random.4189834856 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 972515898 ps |
| CPU time | 14.56 seconds |
| Started | Oct 14 09:12:07 PM UTC 24 |
| Finished | Oct 14 09:12:23 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189834856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.4189834856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device_slow_rsp.2335036897 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 29428476068 ps |
| CPU time | 129.41 seconds |
| Started | Oct 14 09:15:41 PM UTC 24 |
| Finished | Oct 14 09:17:53 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335036897 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device_slow_rsp.2335036897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_large_delays.3180745531 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2168048205 ps |
| CPU time | 9.64 seconds |
| Started | Oct 14 09:12:03 PM UTC 24 |
| Finished | Oct 14 09:12:14 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180745531 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3180745531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_error.2697381673 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2855259165 ps |
| CPU time | 49.98 seconds |
| Started | Oct 14 09:12:48 PM UTC 24 |
| Finished | Oct 14 09:13:39 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697381673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2697381673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device_slow_rsp.337335605 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 93089325792 ps |
| CPU time | 197.01 seconds |
| Started | Oct 14 09:15:32 PM UTC 24 |
| Finished | Oct 14 09:18:52 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337335605 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device_slow_rsp.337335605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_same_source.1685002827 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4805780644 ps |
| CPU time | 16.89 seconds |
| Started | Oct 14 09:13:06 PM UTC 24 |
| Finished | Oct 14 09:13:24 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685002827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.1685002827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device_slow_rsp.2627779186 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 14263874350 ps |
| CPU time | 82.1 seconds |
| Started | Oct 14 09:15:25 PM UTC 24 |
| Finished | Oct 14 09:16:49 PM UTC 24 |
| Peak memory | 210780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627779186 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device_slow_rsp.2627779186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device_slow_rsp.4183288073 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 18817515790 ps |
| CPU time | 140.47 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:21:13 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183288073 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device_slow_rsp.4183288073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all.3444072468 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6004346549 ps |
| CPU time | 70.18 seconds |
| Started | Oct 14 09:14:01 PM UTC 24 |
| Finished | Oct 14 09:15:13 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444072468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3444072468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_zero_delays.1838642798 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 28877423 ps |
| CPU time | 3.97 seconds |
| Started | Oct 14 09:12:15 PM UTC 24 |
| Finished | Oct 14 09:12:20 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838642798 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_delays.1838642798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device_slow_rsp.1459066699 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 77183086877 ps |
| CPU time | 79.46 seconds |
| Started | Oct 14 09:12:17 PM UTC 24 |
| Finished | Oct 14 09:13:39 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459066699 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device_slow_rsp.1459066699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_reset_error.884300193 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 897982030 ps |
| CPU time | 53.05 seconds |
| Started | Oct 14 09:12:48 PM UTC 24 |
| Finished | Oct 14 09:13:42 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884300193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_reset_error.884300193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_reset_error.705392157 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3549466296 ps |
| CPU time | 90.44 seconds |
| Started | Oct 14 09:13:53 PM UTC 24 |
| Finished | Oct 14 09:15:25 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705392157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_reset_error.705392157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_rand_reset.659600323 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 645649972 ps |
| CPU time | 69.18 seconds |
| Started | Oct 14 09:12:23 PM UTC 24 |
| Finished | Oct 14 09:13:34 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659600323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_rand_reset.659600323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_rand_reset.1643409267 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 952152399 ps |
| CPU time | 194.44 seconds |
| Started | Oct 14 09:19:51 PM UTC 24 |
| Finished | Oct 14 09:23:09 PM UTC 24 |
| Peak memory | 220896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643409267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_rand_reset.1643409267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_rand_reset.3575824766 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 6650975881 ps |
| CPU time | 214.12 seconds |
| Started | Oct 14 09:20:06 PM UTC 24 |
| Finished | Oct 14 09:23:43 PM UTC 24 |
| Peak memory | 220748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575824766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_rand_reset.3575824766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device.4283628182 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4974567142 ps |
| CPU time | 13.46 seconds |
| Started | Oct 14 09:17:46 PM UTC 24 |
| Finished | Oct 14 09:18:01 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283628182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device.4283628182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device.608400958 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 3118896484 ps |
| CPU time | 20.02 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:15 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608400958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device.608400958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device_slow_rsp.3624211127 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 82090121186 ps |
| CPU time | 222.12 seconds |
| Started | Oct 14 09:12:30 PM UTC 24 |
| Finished | Oct 14 09:16:15 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624211127 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device_slow_rsp.3624211127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random.3257800067 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 269442225 ps |
| CPU time | 5.98 seconds |
| Started | Oct 14 09:12:38 PM UTC 24 |
| Finished | Oct 14 09:12:45 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257800067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random.3257800067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device_slow_rsp.1634410116 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 80344470435 ps |
| CPU time | 119.01 seconds |
| Started | Oct 14 09:13:06 PM UTC 24 |
| Finished | Oct 14 09:15:07 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634410116 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device_slow_rsp.1634410116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_rand_reset.471587417 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 133163400 ps |
| CPU time | 35.52 seconds |
| Started | Oct 14 09:12:33 PM UTC 24 |
| Finished | Oct 14 09:13:10 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471587417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_rand_reset.471587417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_rand_reset.2381700265 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3584910226 ps |
| CPU time | 171.5 seconds |
| Started | Oct 14 09:13:51 PM UTC 24 |
| Finished | Oct 14 09:16:46 PM UTC 24 |
| Peak memory | 217252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381700265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_rand_reset.2381700265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_slow_rsp.3045908730 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 20185277519 ps |
| CPU time | 92.09 seconds |
| Started | Oct 14 09:12:04 PM UTC 24 |
| Finished | Oct 14 09:13:38 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045908730 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3045908730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_rand_reset.3571499767 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 11126712703 ps |
| CPU time | 95.25 seconds |
| Started | Oct 14 09:15:02 PM UTC 24 |
| Finished | Oct 14 09:16:39 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571499767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_rand_reset.3571499767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_random_zero_delays.2505559883 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 560406908 ps |
| CPU time | 8.89 seconds |
| Started | Oct 14 09:12:03 PM UTC 24 |
| Finished | Oct 14 09:12:13 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505559883 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_delays.2505559883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_rand_reset.2243027841 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 7328191724 ps |
| CPU time | 145.4 seconds |
| Started | Oct 14 09:14:46 PM UTC 24 |
| Finished | Oct 14 09:17:14 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243027841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_rand_reset.2243027841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_rand_reset.1575230879 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 542846117 ps |
| CPU time | 52.79 seconds |
| Started | Oct 14 09:18:24 PM UTC 24 |
| Finished | Oct 14 09:19:18 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575230879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_rand_reset.1575230879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_slow_rsp.4059463608 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 14611059588 ps |
| CPU time | 87.94 seconds |
| Started | Oct 14 09:12:16 PM UTC 24 |
| Finished | Oct 14 09:13:46 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059463608 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.4059463608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_large_delays.2886875194 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 11158545120 ps |
| CPU time | 8.93 seconds |
| Started | Oct 14 09:12:13 PM UTC 24 |
| Finished | Oct 14 09:12:23 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886875194 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2886875194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device.1292257971 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2196968314 ps |
| CPU time | 11.53 seconds |
| Started | Oct 14 09:16:38 PM UTC 24 |
| Finished | Oct 14 09:16:50 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292257971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device.1292257971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_access_same_device.4177036414 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 83389836 ps |
| CPU time | 2.7 seconds |
| Started | Oct 14 09:12:04 PM UTC 24 |
| Finished | Oct 14 09:12:07 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177036414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.4177036414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_error_and_unmapped_addr.1731437330 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2017323846 ps |
| CPU time | 11.48 seconds |
| Started | Oct 14 09:12:09 PM UTC 24 |
| Finished | Oct 14 09:12:22 PM UTC 24 |
| Peak memory | 210600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731437330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr.1731437330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_same_source.3355519927 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 552376379 ps |
| CPU time | 8.89 seconds |
| Started | Oct 14 09:12:05 PM UTC 24 |
| Finished | Oct 14 09:12:15 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355519927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.3355519927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke.17770595 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8431838 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 09:12:01 PM UTC 24 |
| Finished | Oct 14 09:12:03 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17770595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.17770595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_large_delays.570848369 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4112280073 ps |
| CPU time | 12.37 seconds |
| Started | Oct 14 09:12:01 PM UTC 24 |
| Finished | Oct 14 09:12:14 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570848369 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.570848369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_slow_rsp.3615338483 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 5562714937 ps |
| CPU time | 14.61 seconds |
| Started | Oct 14 09:12:03 PM UTC 24 |
| Finished | Oct 14 09:12:19 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615338483 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3615338483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_smoke_zero_delays.667167072 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 15461769 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 09:12:01 PM UTC 24 |
| Finished | Oct 14 09:12:03 PM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667167072 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays.667167072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all.3496205947 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2121643990 ps |
| CPU time | 35.94 seconds |
| Started | Oct 14 09:12:09 PM UTC 24 |
| Finished | Oct 14 09:12:47 PM UTC 24 |
| Peak memory | 210696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496205947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.3496205947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_error.2209647436 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 430005791 ps |
| CPU time | 22.5 seconds |
| Started | Oct 14 09:12:13 PM UTC 24 |
| Finished | Oct 14 09:12:37 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209647436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2209647436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_rand_reset.4230792360 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 121420019 ps |
| CPU time | 13.4 seconds |
| Started | Oct 14 09:12:09 PM UTC 24 |
| Finished | Oct 14 09:12:24 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230792360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_rand_reset.4230792360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/0.xbar_stress_all_with_reset_error.3924133429 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1199994685 ps |
| CPU time | 86.34 seconds |
| Started | Oct 14 09:12:13 PM UTC 24 |
| Finished | Oct 14 09:13:41 PM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924133429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_reset_error.3924133429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_access_same_device.2236356015 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 63730872 ps |
| CPU time | 14.45 seconds |
| Started | Oct 14 09:12:16 PM UTC 24 |
| Finished | Oct 14 09:12:32 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236356015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.2236356015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_and_unmapped_addr.1994529283 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 689282757 ps |
| CPU time | 12.68 seconds |
| Started | Oct 14 09:12:22 PM UTC 24 |
| Finished | Oct 14 09:12:36 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994529283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr.1994529283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_error_random.205717774 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 35184608 ps |
| CPU time | 3.2 seconds |
| Started | Oct 14 09:12:20 PM UTC 24 |
| Finished | Oct 14 09:12:24 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205717774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.205717774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random.3099121722 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 31431542 ps |
| CPU time | 5.09 seconds |
| Started | Oct 14 09:12:15 PM UTC 24 |
| Finished | Oct 14 09:12:21 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099121722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random.3099121722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_random_large_delays.3575842220 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 30392140988 ps |
| CPU time | 113.07 seconds |
| Started | Oct 14 09:12:15 PM UTC 24 |
| Finished | Oct 14 09:14:10 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575842220 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3575842220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_same_source.318912047 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 166725485 ps |
| CPU time | 6.69 seconds |
| Started | Oct 14 09:12:17 PM UTC 24 |
| Finished | Oct 14 09:12:25 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318912047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.318912047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke.1247430021 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 38823873 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 09:12:13 PM UTC 24 |
| Finished | Oct 14 09:12:16 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247430021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1247430021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_slow_rsp.3129716643 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 777159362 ps |
| CPU time | 6.69 seconds |
| Started | Oct 14 09:12:15 PM UTC 24 |
| Finished | Oct 14 09:12:23 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129716643 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3129716643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_smoke_zero_delays.3230093872 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 11836455 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 09:12:13 PM UTC 24 |
| Finished | Oct 14 09:12:16 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230093872 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays.3230093872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all.483149987 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 308702383 ps |
| CPU time | 39.88 seconds |
| Started | Oct 14 09:12:23 PM UTC 24 |
| Finished | Oct 14 09:13:05 PM UTC 24 |
| Peak memory | 213096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483149987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.483149987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_stress_all_with_error.353031136 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1786128185 ps |
| CPU time | 30.01 seconds |
| Started | Oct 14 09:12:23 PM UTC 24 |
| Finished | Oct 14 09:12:55 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353031136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.353031136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/1.xbar_unmapped_addr.1128131427 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 76309913 ps |
| CPU time | 7.55 seconds |
| Started | Oct 14 09:12:21 PM UTC 24 |
| Finished | Oct 14 09:12:29 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128131427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1128131427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/1.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device.3553146242 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 31345419 ps |
| CPU time | 6.09 seconds |
| Started | Oct 14 09:13:58 PM UTC 24 |
| Finished | Oct 14 09:14:05 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553146242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device.3553146242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_access_same_device_slow_rsp.1207202568 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 16269132213 ps |
| CPU time | 59.26 seconds |
| Started | Oct 14 09:13:58 PM UTC 24 |
| Finished | Oct 14 09:14:59 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207202568 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device_slow_rsp.1207202568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_and_unmapped_addr.1494185172 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 357781218 ps |
| CPU time | 8.89 seconds |
| Started | Oct 14 09:14:00 PM UTC 24 |
| Finished | Oct 14 09:14:10 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494185172 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr.1494185172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_error_random.1662773905 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2379948700 ps |
| CPU time | 9.86 seconds |
| Started | Oct 14 09:14:00 PM UTC 24 |
| Finished | Oct 14 09:14:11 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662773905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1662773905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random.3669181919 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 68813915 ps |
| CPU time | 5.05 seconds |
| Started | Oct 14 09:13:54 PM UTC 24 |
| Finished | Oct 14 09:14:00 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669181919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random.3669181919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_large_delays.1787129898 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 16417232504 ps |
| CPU time | 74.27 seconds |
| Started | Oct 14 09:13:57 PM UTC 24 |
| Finished | Oct 14 09:15:13 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787129898 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1787129898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_slow_rsp.3639353332 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 14630783210 ps |
| CPU time | 30.22 seconds |
| Started | Oct 14 09:13:57 PM UTC 24 |
| Finished | Oct 14 09:14:28 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639353332 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.3639353332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_random_zero_delays.3936074074 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 59275457 ps |
| CPU time | 4.13 seconds |
| Started | Oct 14 09:13:55 PM UTC 24 |
| Finished | Oct 14 09:14:01 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936074074 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_delays.3936074074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_same_source.1723265939 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 944447376 ps |
| CPU time | 8.64 seconds |
| Started | Oct 14 09:13:58 PM UTC 24 |
| Finished | Oct 14 09:14:08 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723265939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1723265939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke.844207479 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 20606300 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 09:13:53 PM UTC 24 |
| Finished | Oct 14 09:13:56 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844207479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.844207479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_large_delays.1293193294 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2421160466 ps |
| CPU time | 19.63 seconds |
| Started | Oct 14 09:13:54 PM UTC 24 |
| Finished | Oct 14 09:14:15 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293193294 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.1293193294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_slow_rsp.3879402143 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1181496553 ps |
| CPU time | 7.28 seconds |
| Started | Oct 14 09:13:54 PM UTC 24 |
| Finished | Oct 14 09:14:03 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879402143 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3879402143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_smoke_zero_delays.3815349525 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 12931631 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 09:13:54 PM UTC 24 |
| Finished | Oct 14 09:13:57 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815349525 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays.3815349525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_error.4105681945 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5297884719 ps |
| CPU time | 32.33 seconds |
| Started | Oct 14 09:14:02 PM UTC 24 |
| Finished | Oct 14 09:14:35 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105681945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4105681945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_rand_reset.1656156002 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2835349517 ps |
| CPU time | 117.41 seconds |
| Started | Oct 14 09:14:01 PM UTC 24 |
| Finished | Oct 14 09:16:01 PM UTC 24 |
| Peak memory | 217184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656156002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_rand_reset.1656156002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_stress_all_with_reset_error.666465861 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 383647360 ps |
| CPU time | 36.42 seconds |
| Started | Oct 14 09:14:03 PM UTC 24 |
| Finished | Oct 14 09:14:41 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666465861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_reset_error.666465861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/10.xbar_unmapped_addr.2531652196 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 29842247 ps |
| CPU time | 4.09 seconds |
| Started | Oct 14 09:14:00 PM UTC 24 |
| Finished | Oct 14 09:14:05 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531652196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2531652196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/10.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device.2591321968 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 261729498 ps |
| CPU time | 6.69 seconds |
| Started | Oct 14 09:14:09 PM UTC 24 |
| Finished | Oct 14 09:14:16 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591321968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device.2591321968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_access_same_device_slow_rsp.4021715916 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 20347461348 ps |
| CPU time | 149.1 seconds |
| Started | Oct 14 09:14:09 PM UTC 24 |
| Finished | Oct 14 09:16:40 PM UTC 24 |
| Peak memory | 213088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021715916 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device_slow_rsp.4021715916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_and_unmapped_addr.3050383425 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1369800538 ps |
| CPU time | 9.36 seconds |
| Started | Oct 14 09:14:11 PM UTC 24 |
| Finished | Oct 14 09:14:21 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050383425 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr.3050383425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_error_random.2165284361 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 231221559 ps |
| CPU time | 7.8 seconds |
| Started | Oct 14 09:14:11 PM UTC 24 |
| Finished | Oct 14 09:14:20 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165284361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2165284361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random.3719257334 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 154286334 ps |
| CPU time | 3.44 seconds |
| Started | Oct 14 09:14:06 PM UTC 24 |
| Finished | Oct 14 09:14:11 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719257334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random.3719257334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_large_delays.1824180689 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 27751624891 ps |
| CPU time | 72.1 seconds |
| Started | Oct 14 09:14:07 PM UTC 24 |
| Finished | Oct 14 09:15:21 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824180689 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1824180689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_slow_rsp.3395101516 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 10010697438 ps |
| CPU time | 28.23 seconds |
| Started | Oct 14 09:14:07 PM UTC 24 |
| Finished | Oct 14 09:14:37 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395101516 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3395101516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_random_zero_delays.3951943111 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 58040086 ps |
| CPU time | 4.02 seconds |
| Started | Oct 14 09:14:06 PM UTC 24 |
| Finished | Oct 14 09:14:11 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951943111 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_delays.3951943111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_same_source.2849708708 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 732813816 ps |
| CPU time | 13.3 seconds |
| Started | Oct 14 09:14:09 PM UTC 24 |
| Finished | Oct 14 09:14:23 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849708708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2849708708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke.796622136 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 58192467 ps |
| CPU time | 2.25 seconds |
| Started | Oct 14 09:14:03 PM UTC 24 |
| Finished | Oct 14 09:14:06 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796622136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.796622136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_large_delays.2293904951 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 9295691544 ps |
| CPU time | 7.49 seconds |
| Started | Oct 14 09:14:04 PM UTC 24 |
| Finished | Oct 14 09:14:13 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293904951 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2293904951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_slow_rsp.3622795781 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 968274700 ps |
| CPU time | 8.2 seconds |
| Started | Oct 14 09:14:06 PM UTC 24 |
| Finished | Oct 14 09:14:15 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622795781 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3622795781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_smoke_zero_delays.2817932671 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 12676710 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 09:14:04 PM UTC 24 |
| Finished | Oct 14 09:14:07 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817932671 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays.2817932671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all.20841361 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 224090225 ps |
| CPU time | 8.36 seconds |
| Started | Oct 14 09:14:11 PM UTC 24 |
| Finished | Oct 14 09:14:20 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20841361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.20841361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_error.375400320 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 261664513 ps |
| CPU time | 13.89 seconds |
| Started | Oct 14 09:14:12 PM UTC 24 |
| Finished | Oct 14 09:14:27 PM UTC 24 |
| Peak memory | 210652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375400320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.375400320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_rand_reset.3887887670 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 1011336057 ps |
| CPU time | 136.51 seconds |
| Started | Oct 14 09:14:12 PM UTC 24 |
| Finished | Oct 14 09:16:31 PM UTC 24 |
| Peak memory | 216960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887887670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_rand_reset.3887887670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_stress_all_with_reset_error.3279888085 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 75547518 ps |
| CPU time | 11.53 seconds |
| Started | Oct 14 09:14:12 PM UTC 24 |
| Finished | Oct 14 09:14:25 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279888085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_reset_error.3279888085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/11.xbar_unmapped_addr.128645908 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 78356588 ps |
| CPU time | 7.7 seconds |
| Started | Oct 14 09:14:11 PM UTC 24 |
| Finished | Oct 14 09:14:20 PM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128645908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.128645908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/11.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device.3883410392 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 5226643112 ps |
| CPU time | 17.69 seconds |
| Started | Oct 14 09:14:18 PM UTC 24 |
| Finished | Oct 14 09:14:37 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883410392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device.3883410392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_access_same_device_slow_rsp.3119228845 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 15480219564 ps |
| CPU time | 86.63 seconds |
| Started | Oct 14 09:14:18 PM UTC 24 |
| Finished | Oct 14 09:15:46 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119228845 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device_slow_rsp.3119228845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_and_unmapped_addr.4199073945 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 63386914 ps |
| CPU time | 5.06 seconds |
| Started | Oct 14 09:14:22 PM UTC 24 |
| Finished | Oct 14 09:14:28 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199073945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr.4199073945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_error_random.2626005573 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 497119258 ps |
| CPU time | 12.6 seconds |
| Started | Oct 14 09:14:21 PM UTC 24 |
| Finished | Oct 14 09:14:35 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626005573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2626005573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random.1054955321 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3089801921 ps |
| CPU time | 11.01 seconds |
| Started | Oct 14 09:14:16 PM UTC 24 |
| Finished | Oct 14 09:14:28 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054955321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random.1054955321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_large_delays.422370619 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 6642027980 ps |
| CPU time | 8.14 seconds |
| Started | Oct 14 09:14:16 PM UTC 24 |
| Finished | Oct 14 09:14:26 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422370619 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.422370619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_slow_rsp.2272774526 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3313478579 ps |
| CPU time | 28.66 seconds |
| Started | Oct 14 09:14:18 PM UTC 24 |
| Finished | Oct 14 09:14:48 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272774526 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2272774526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_random_zero_delays.800770457 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 51096488 ps |
| CPU time | 5.03 seconds |
| Started | Oct 14 09:14:16 PM UTC 24 |
| Finished | Oct 14 09:14:22 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800770457 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_delays.800770457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_same_source.3314195183 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 684220892 ps |
| CPU time | 5.62 seconds |
| Started | Oct 14 09:14:20 PM UTC 24 |
| Finished | Oct 14 09:14:27 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314195183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3314195183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke.449740028 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 58363051 ps |
| CPU time | 2.81 seconds |
| Started | Oct 14 09:14:12 PM UTC 24 |
| Finished | Oct 14 09:14:16 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449740028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.449740028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_large_delays.2674211615 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2352114166 ps |
| CPU time | 18.84 seconds |
| Started | Oct 14 09:14:14 PM UTC 24 |
| Finished | Oct 14 09:14:34 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674211615 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2674211615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_slow_rsp.3393288270 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 13136099820 ps |
| CPU time | 11.32 seconds |
| Started | Oct 14 09:14:14 PM UTC 24 |
| Finished | Oct 14 09:14:26 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393288270 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3393288270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_smoke_zero_delays.3166830278 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 12525493 ps |
| CPU time | 1.52 seconds |
| Started | Oct 14 09:14:13 PM UTC 24 |
| Finished | Oct 14 09:14:15 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166830278 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays.3166830278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all.1354681069 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 5998719607 ps |
| CPU time | 78.08 seconds |
| Started | Oct 14 09:14:22 PM UTC 24 |
| Finished | Oct 14 09:15:41 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354681069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1354681069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_error.1206606478 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2796181430 ps |
| CPU time | 26.57 seconds |
| Started | Oct 14 09:14:23 PM UTC 24 |
| Finished | Oct 14 09:14:51 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206606478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1206606478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_rand_reset.345607052 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3951888076 ps |
| CPU time | 165.75 seconds |
| Started | Oct 14 09:14:23 PM UTC 24 |
| Finished | Oct 14 09:17:11 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345607052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_rand_reset.345607052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_stress_all_with_reset_error.1164587095 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 413739256 ps |
| CPU time | 15.31 seconds |
| Started | Oct 14 09:14:24 PM UTC 24 |
| Finished | Oct 14 09:14:41 PM UTC 24 |
| Peak memory | 213104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164587095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_reset_error.1164587095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/12.xbar_unmapped_addr.1778882152 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2058811224 ps |
| CPU time | 13.54 seconds |
| Started | Oct 14 09:14:22 PM UTC 24 |
| Finished | Oct 14 09:14:36 PM UTC 24 |
| Peak memory | 212924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778882152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1778882152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/12.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device.2905752736 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2277361453 ps |
| CPU time | 22.19 seconds |
| Started | Oct 14 09:14:29 PM UTC 24 |
| Finished | Oct 14 09:14:53 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905752736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device.2905752736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_access_same_device_slow_rsp.1651881116 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 13291933207 ps |
| CPU time | 58.24 seconds |
| Started | Oct 14 09:14:29 PM UTC 24 |
| Finished | Oct 14 09:15:29 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651881116 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device_slow_rsp.1651881116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_and_unmapped_addr.4029095742 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1190450012 ps |
| CPU time | 10.86 seconds |
| Started | Oct 14 09:14:35 PM UTC 24 |
| Finished | Oct 14 09:14:47 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029095742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.4029095742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_error_random.2681867945 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 851102331 ps |
| CPU time | 7.6 seconds |
| Started | Oct 14 09:14:31 PM UTC 24 |
| Finished | Oct 14 09:14:40 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681867945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2681867945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random.1384283872 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 50443572 ps |
| CPU time | 7.67 seconds |
| Started | Oct 14 09:14:28 PM UTC 24 |
| Finished | Oct 14 09:14:37 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384283872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random.1384283872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_large_delays.725242092 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 15424117874 ps |
| CPU time | 42.96 seconds |
| Started | Oct 14 09:14:29 PM UTC 24 |
| Finished | Oct 14 09:15:14 PM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725242092 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.725242092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_slow_rsp.1153610301 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 17458587368 ps |
| CPU time | 65.47 seconds |
| Started | Oct 14 09:14:29 PM UTC 24 |
| Finished | Oct 14 09:15:37 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153610301 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.1153610301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_random_zero_delays.1010512560 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 76611916 ps |
| CPU time | 6.54 seconds |
| Started | Oct 14 09:14:28 PM UTC 24 |
| Finished | Oct 14 09:14:36 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010512560 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_delays.1010512560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_same_source.1642452522 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 83831275 ps |
| CPU time | 7.7 seconds |
| Started | Oct 14 09:14:30 PM UTC 24 |
| Finished | Oct 14 09:14:39 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642452522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1642452522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke.3527412257 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 59409213 ps |
| CPU time | 2.01 seconds |
| Started | Oct 14 09:14:25 PM UTC 24 |
| Finished | Oct 14 09:14:28 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527412257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3527412257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_large_delays.2424882095 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1588265172 ps |
| CPU time | 11.28 seconds |
| Started | Oct 14 09:14:27 PM UTC 24 |
| Finished | Oct 14 09:14:40 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424882095 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2424882095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_slow_rsp.2703772197 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2123727044 ps |
| CPU time | 9.99 seconds |
| Started | Oct 14 09:14:28 PM UTC 24 |
| Finished | Oct 14 09:14:39 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703772197 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2703772197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_smoke_zero_delays.914903413 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 14589122 ps |
| CPU time | 1.6 seconds |
| Started | Oct 14 09:14:27 PM UTC 24 |
| Finished | Oct 14 09:14:30 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914903413 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays.914903413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all.64108067 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2909384100 ps |
| CPU time | 26.04 seconds |
| Started | Oct 14 09:14:35 PM UTC 24 |
| Finished | Oct 14 09:15:03 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64108067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.64108067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_error.827080055 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3348916492 ps |
| CPU time | 40.72 seconds |
| Started | Oct 14 09:14:37 PM UTC 24 |
| Finished | Oct 14 09:15:19 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827080055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.827080055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_rand_reset.334326889 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 88670351 ps |
| CPU time | 10.95 seconds |
| Started | Oct 14 09:14:36 PM UTC 24 |
| Finished | Oct 14 09:14:49 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334326889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_rand_reset.334326889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_stress_all_with_reset_error.2196761753 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 174686905 ps |
| CPU time | 15.63 seconds |
| Started | Oct 14 09:14:37 PM UTC 24 |
| Finished | Oct 14 09:14:53 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196761753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_reset_error.2196761753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/13.xbar_unmapped_addr.40412347 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 99008637 ps |
| CPU time | 6.74 seconds |
| Started | Oct 14 09:14:33 PM UTC 24 |
| Finished | Oct 14 09:14:41 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40412347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.40412347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/13.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device.623631986 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 96089975 ps |
| CPU time | 6.58 seconds |
| Started | Oct 14 09:14:41 PM UTC 24 |
| Finished | Oct 14 09:14:49 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623631986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.623631986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_access_same_device_slow_rsp.2704966915 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 73317951786 ps |
| CPU time | 91 seconds |
| Started | Oct 14 09:14:43 PM UTC 24 |
| Finished | Oct 14 09:16:16 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704966915 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device_slow_rsp.2704966915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_and_unmapped_addr.3422817359 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 37891090 ps |
| CPU time | 1.97 seconds |
| Started | Oct 14 09:14:43 PM UTC 24 |
| Finished | Oct 14 09:14:46 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422817359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr.3422817359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_error_random.1637275995 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 144524103 ps |
| CPU time | 3.02 seconds |
| Started | Oct 14 09:14:43 PM UTC 24 |
| Finished | Oct 14 09:14:47 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637275995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1637275995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random.2827574042 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 1133226568 ps |
| CPU time | 14.41 seconds |
| Started | Oct 14 09:14:39 PM UTC 24 |
| Finished | Oct 14 09:14:54 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827574042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random.2827574042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_large_delays.1851504669 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 8564087459 ps |
| CPU time | 41.61 seconds |
| Started | Oct 14 09:14:40 PM UTC 24 |
| Finished | Oct 14 09:15:23 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851504669 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1851504669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_slow_rsp.1849020083 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 7493419167 ps |
| CPU time | 48.12 seconds |
| Started | Oct 14 09:14:41 PM UTC 24 |
| Finished | Oct 14 09:15:31 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849020083 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.1849020083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_random_zero_delays.2737939710 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 63160042 ps |
| CPU time | 3.39 seconds |
| Started | Oct 14 09:14:40 PM UTC 24 |
| Finished | Oct 14 09:14:44 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737939710 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delays.2737939710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_same_source.4149641245 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 51346938 ps |
| CPU time | 2.09 seconds |
| Started | Oct 14 09:14:43 PM UTC 24 |
| Finished | Oct 14 09:14:46 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149641245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4149641245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke.3158741923 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 12231911 ps |
| CPU time | 1.7 seconds |
| Started | Oct 14 09:14:38 PM UTC 24 |
| Finished | Oct 14 09:14:41 PM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158741923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3158741923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_large_delays.1190508569 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4463537429 ps |
| CPU time | 17.35 seconds |
| Started | Oct 14 09:14:38 PM UTC 24 |
| Finished | Oct 14 09:14:57 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190508569 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.1190508569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_slow_rsp.3894578118 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1057922749 ps |
| CPU time | 10.06 seconds |
| Started | Oct 14 09:14:38 PM UTC 24 |
| Finished | Oct 14 09:14:50 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894578118 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3894578118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_smoke_zero_delays.27158624 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 14215832 ps |
| CPU time | 1.79 seconds |
| Started | Oct 14 09:14:38 PM UTC 24 |
| Finished | Oct 14 09:14:41 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27158624 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays.27158624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all.2818451107 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2817384874 ps |
| CPU time | 37.46 seconds |
| Started | Oct 14 09:14:43 PM UTC 24 |
| Finished | Oct 14 09:15:22 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818451107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2818451107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_error.2557715392 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4721777291 ps |
| CPU time | 86.27 seconds |
| Started | Oct 14 09:14:49 PM UTC 24 |
| Finished | Oct 14 09:16:18 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557715392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2557715392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_stress_all_with_reset_error.900470995 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2051990415 ps |
| CPU time | 78.11 seconds |
| Started | Oct 14 09:14:49 PM UTC 24 |
| Finished | Oct 14 09:16:10 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900470995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_reset_error.900470995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/14.xbar_unmapped_addr.2227730622 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 257508045 ps |
| CPU time | 6.78 seconds |
| Started | Oct 14 09:14:43 PM UTC 24 |
| Finished | Oct 14 09:14:51 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227730622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2227730622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/14.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_access_same_device.1632544499 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 98170034 ps |
| CPU time | 7.81 seconds |
| Started | Oct 14 09:14:51 PM UTC 24 |
| Finished | Oct 14 09:15:00 PM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632544499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1632544499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_and_unmapped_addr.1957160200 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 93737452 ps |
| CPU time | 3.7 seconds |
| Started | Oct 14 09:14:52 PM UTC 24 |
| Finished | Oct 14 09:14:57 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957160200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr.1957160200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_error_random.2510644373 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 594620895 ps |
| CPU time | 7.99 seconds |
| Started | Oct 14 09:14:51 PM UTC 24 |
| Finished | Oct 14 09:15:00 PM UTC 24 |
| Peak memory | 213072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510644373 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2510644373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random.4090336342 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 339563733 ps |
| CPU time | 6.3 seconds |
| Started | Oct 14 09:14:50 PM UTC 24 |
| Finished | Oct 14 09:14:57 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090336342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random.4090336342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_large_delays.1435157430 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 43875815082 ps |
| CPU time | 76.79 seconds |
| Started | Oct 14 09:14:50 PM UTC 24 |
| Finished | Oct 14 09:16:09 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435157430 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1435157430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_slow_rsp.1165695570 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 47402812378 ps |
| CPU time | 106.38 seconds |
| Started | Oct 14 09:14:50 PM UTC 24 |
| Finished | Oct 14 09:16:39 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165695570 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1165695570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_random_zero_delays.1985216979 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 24028471 ps |
| CPU time | 2.92 seconds |
| Started | Oct 14 09:14:50 PM UTC 24 |
| Finished | Oct 14 09:14:54 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985216979 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_delays.1985216979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_same_source.3516869919 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 730566496 ps |
| CPU time | 13.08 seconds |
| Started | Oct 14 09:14:51 PM UTC 24 |
| Finished | Oct 14 09:15:06 PM UTC 24 |
| Peak memory | 212912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516869919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3516869919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke.3118980425 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 117882300 ps |
| CPU time | 2.42 seconds |
| Started | Oct 14 09:14:49 PM UTC 24 |
| Finished | Oct 14 09:14:53 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118980425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3118980425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_large_delays.1447963106 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 1501191709 ps |
| CPU time | 9.1 seconds |
| Started | Oct 14 09:14:50 PM UTC 24 |
| Finished | Oct 14 09:15:00 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447963106 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1447963106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_slow_rsp.3294352226 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 683637946 ps |
| CPU time | 4.5 seconds |
| Started | Oct 14 09:14:50 PM UTC 24 |
| Finished | Oct 14 09:14:55 PM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294352226 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3294352226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_smoke_zero_delays.3826009882 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 10311640 ps |
| CPU time | 1.71 seconds |
| Started | Oct 14 09:14:49 PM UTC 24 |
| Finished | Oct 14 09:14:53 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826009882 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays.3826009882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all.2249450878 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3874075398 ps |
| CPU time | 14.34 seconds |
| Started | Oct 14 09:14:54 PM UTC 24 |
| Finished | Oct 14 09:15:09 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249450878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2249450878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_error.4244723529 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1336954015 ps |
| CPU time | 25.56 seconds |
| Started | Oct 14 09:14:54 PM UTC 24 |
| Finished | Oct 14 09:15:21 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244723529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.4244723529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_rand_reset.328773566 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 498820814 ps |
| CPU time | 96.33 seconds |
| Started | Oct 14 09:14:54 PM UTC 24 |
| Finished | Oct 14 09:16:32 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328773566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_rand_reset.328773566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_stress_all_with_reset_error.2220393971 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 10813760663 ps |
| CPU time | 81.05 seconds |
| Started | Oct 14 09:14:55 PM UTC 24 |
| Finished | Oct 14 09:16:18 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220393971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_reset_error.2220393971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/15.xbar_unmapped_addr.3709362515 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 32524760 ps |
| CPU time | 3.95 seconds |
| Started | Oct 14 09:14:52 PM UTC 24 |
| Finished | Oct 14 09:14:57 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709362515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3709362515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/15.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device.4159776032 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 222823454 ps |
| CPU time | 5.39 seconds |
| Started | Oct 14 09:14:59 PM UTC 24 |
| Finished | Oct 14 09:15:06 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159776032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device.4159776032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_access_same_device_slow_rsp.2602819923 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 5753620286 ps |
| CPU time | 32.4 seconds |
| Started | Oct 14 09:14:59 PM UTC 24 |
| Finished | Oct 14 09:15:33 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602819923 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device_slow_rsp.2602819923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_and_unmapped_addr.3926049062 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 53398808 ps |
| CPU time | 3.99 seconds |
| Started | Oct 14 09:15:01 PM UTC 24 |
| Finished | Oct 14 09:15:06 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926049062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr.3926049062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_error_random.4009816266 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 805134129 ps |
| CPU time | 8.76 seconds |
| Started | Oct 14 09:15:01 PM UTC 24 |
| Finished | Oct 14 09:15:11 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009816266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.4009816266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random.1229967490 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 86994375 ps |
| CPU time | 2.44 seconds |
| Started | Oct 14 09:14:58 PM UTC 24 |
| Finished | Oct 14 09:15:01 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229967490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random.1229967490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_large_delays.926643941 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 20584717817 ps |
| CPU time | 110.01 seconds |
| Started | Oct 14 09:14:59 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926643941 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.926643941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_slow_rsp.1142119097 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 10733523128 ps |
| CPU time | 23.29 seconds |
| Started | Oct 14 09:14:59 PM UTC 24 |
| Finished | Oct 14 09:15:24 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142119097 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1142119097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_random_zero_delays.3284554651 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 72461571 ps |
| CPU time | 10.99 seconds |
| Started | Oct 14 09:14:59 PM UTC 24 |
| Finished | Oct 14 09:15:11 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284554651 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delays.3284554651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_same_source.4063048353 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 160082926 ps |
| CPU time | 6.03 seconds |
| Started | Oct 14 09:15:01 PM UTC 24 |
| Finished | Oct 14 09:15:08 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063048353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.4063048353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke.388881299 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 281578056 ps |
| CPU time | 2.26 seconds |
| Started | Oct 14 09:14:55 PM UTC 24 |
| Finished | Oct 14 09:14:58 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388881299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.388881299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_large_delays.1429446860 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1803775540 ps |
| CPU time | 11.94 seconds |
| Started | Oct 14 09:14:56 PM UTC 24 |
| Finished | Oct 14 09:15:09 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429446860 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1429446860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_slow_rsp.3918582792 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1669246013 ps |
| CPU time | 20.24 seconds |
| Started | Oct 14 09:14:58 PM UTC 24 |
| Finished | Oct 14 09:15:19 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918582792 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3918582792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_smoke_zero_delays.2971128886 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 11621024 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 09:14:55 PM UTC 24 |
| Finished | Oct 14 09:14:58 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971128886 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays.2971128886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all.1273167240 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 13922354531 ps |
| CPU time | 68.41 seconds |
| Started | Oct 14 09:15:02 PM UTC 24 |
| Finished | Oct 14 09:16:12 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273167240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.1273167240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_error.1243837890 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1134573004 ps |
| CPU time | 35.72 seconds |
| Started | Oct 14 09:15:03 PM UTC 24 |
| Finished | Oct 14 09:15:41 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243837890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1243837890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_stress_all_with_reset_error.228209880 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 176492500 ps |
| CPU time | 17.58 seconds |
| Started | Oct 14 09:15:07 PM UTC 24 |
| Finished | Oct 14 09:15:26 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228209880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_reset_error.228209880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/16.xbar_unmapped_addr.696760457 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1652585753 ps |
| CPU time | 17.05 seconds |
| Started | Oct 14 09:15:01 PM UTC 24 |
| Finished | Oct 14 09:15:19 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696760457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.696760457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/16.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device.2467366424 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 127595374 ps |
| CPU time | 1.77 seconds |
| Started | Oct 14 09:15:12 PM UTC 24 |
| Finished | Oct 14 09:15:15 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467366424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device.2467366424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_access_same_device_slow_rsp.3378071386 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 9864114148 ps |
| CPU time | 74.99 seconds |
| Started | Oct 14 09:15:12 PM UTC 24 |
| Finished | Oct 14 09:16:29 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378071386 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device_slow_rsp.3378071386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_and_unmapped_addr.2759609145 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1303406048 ps |
| CPU time | 10.55 seconds |
| Started | Oct 14 09:15:16 PM UTC 24 |
| Finished | Oct 14 09:15:27 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759609145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr.2759609145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_error_random.517522612 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 53553310 ps |
| CPU time | 6.29 seconds |
| Started | Oct 14 09:15:14 PM UTC 24 |
| Finished | Oct 14 09:15:22 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517522612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.517522612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random.2475429908 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1317997240 ps |
| CPU time | 15.02 seconds |
| Started | Oct 14 09:15:11 PM UTC 24 |
| Finished | Oct 14 09:15:27 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475429908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random.2475429908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_large_delays.564015813 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 11703649958 ps |
| CPU time | 65.04 seconds |
| Started | Oct 14 09:15:11 PM UTC 24 |
| Finished | Oct 14 09:16:17 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564015813 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.564015813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_slow_rsp.492338348 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 20774964218 ps |
| CPU time | 103.98 seconds |
| Started | Oct 14 09:15:11 PM UTC 24 |
| Finished | Oct 14 09:16:57 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492338348 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.492338348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_random_zero_delays.111391151 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 52634392 ps |
| CPU time | 6.96 seconds |
| Started | Oct 14 09:15:11 PM UTC 24 |
| Finished | Oct 14 09:15:19 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111391151 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_delays.111391151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_same_source.147386745 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 695064052 ps |
| CPU time | 7.85 seconds |
| Started | Oct 14 09:15:13 PM UTC 24 |
| Finished | Oct 14 09:15:22 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147386745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.147386745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke.2216556571 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 15826229 ps |
| CPU time | 1.52 seconds |
| Started | Oct 14 09:15:07 PM UTC 24 |
| Finished | Oct 14 09:15:09 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216556571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2216556571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_large_delays.3912422184 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 8838501246 ps |
| CPU time | 11.43 seconds |
| Started | Oct 14 09:15:08 PM UTC 24 |
| Finished | Oct 14 09:15:21 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912422184 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.3912422184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_slow_rsp.3815581993 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2557348987 ps |
| CPU time | 11.91 seconds |
| Started | Oct 14 09:15:09 PM UTC 24 |
| Finished | Oct 14 09:15:22 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815581993 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.3815581993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_smoke_zero_delays.2473966382 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 11906718 ps |
| CPU time | 1.74 seconds |
| Started | Oct 14 09:15:07 PM UTC 24 |
| Finished | Oct 14 09:15:10 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473966382 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delays.2473966382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all.1409484400 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 147391663 ps |
| CPU time | 12.93 seconds |
| Started | Oct 14 09:15:19 PM UTC 24 |
| Finished | Oct 14 09:15:33 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409484400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1409484400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_error.1017755367 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 636669712 ps |
| CPU time | 15.16 seconds |
| Started | Oct 14 09:15:20 PM UTC 24 |
| Finished | Oct 14 09:15:36 PM UTC 24 |
| Peak memory | 212924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017755367 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1017755367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_rand_reset.2018487474 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 20650883402 ps |
| CPU time | 285.77 seconds |
| Started | Oct 14 09:15:20 PM UTC 24 |
| Finished | Oct 14 09:20:10 PM UTC 24 |
| Peak memory | 222068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018487474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_rand_reset.2018487474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_stress_all_with_reset_error.1112769159 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 41365586 ps |
| CPU time | 7.97 seconds |
| Started | Oct 14 09:15:20 PM UTC 24 |
| Finished | Oct 14 09:15:29 PM UTC 24 |
| Peak memory | 210592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112769159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_reset_error.1112769159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/17.xbar_unmapped_addr.2880372543 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 111465778 ps |
| CPU time | 6.22 seconds |
| Started | Oct 14 09:15:14 PM UTC 24 |
| Finished | Oct 14 09:15:22 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880372543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.2880372543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/17.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_access_same_device.3352044437 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 108930064 ps |
| CPU time | 13.09 seconds |
| Started | Oct 14 09:15:23 PM UTC 24 |
| Finished | Oct 14 09:15:38 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352044437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device.3352044437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_and_unmapped_addr.3984104307 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 262274967 ps |
| CPU time | 5.1 seconds |
| Started | Oct 14 09:15:25 PM UTC 24 |
| Finished | Oct 14 09:15:31 PM UTC 24 |
| Peak memory | 212568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984104307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr.3984104307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_error_random.3712805592 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 16929330 ps |
| CPU time | 2.15 seconds |
| Started | Oct 14 09:15:25 PM UTC 24 |
| Finished | Oct 14 09:15:28 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712805592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3712805592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random.3962480491 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 198115434 ps |
| CPU time | 2.17 seconds |
| Started | Oct 14 09:15:23 PM UTC 24 |
| Finished | Oct 14 09:15:26 PM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962480491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random.3962480491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_large_delays.2704803784 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 74630792240 ps |
| CPU time | 81.29 seconds |
| Started | Oct 14 09:15:23 PM UTC 24 |
| Finished | Oct 14 09:16:46 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704803784 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2704803784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_slow_rsp.1366746260 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1785693109 ps |
| CPU time | 16.3 seconds |
| Started | Oct 14 09:15:23 PM UTC 24 |
| Finished | Oct 14 09:15:41 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366746260 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1366746260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_random_zero_delays.3187615243 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 57887985 ps |
| CPU time | 2.41 seconds |
| Started | Oct 14 09:15:23 PM UTC 24 |
| Finished | Oct 14 09:15:27 PM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187615243 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_delays.3187615243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_same_source.3548862916 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 63516794 ps |
| CPU time | 3.78 seconds |
| Started | Oct 14 09:15:25 PM UTC 24 |
| Finished | Oct 14 09:15:29 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548862916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3548862916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke.3195000404 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 8780494 ps |
| CPU time | 1.29 seconds |
| Started | Oct 14 09:15:20 PM UTC 24 |
| Finished | Oct 14 09:15:23 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195000404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3195000404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_large_delays.2519367368 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2244746204 ps |
| CPU time | 11.05 seconds |
| Started | Oct 14 09:15:22 PM UTC 24 |
| Finished | Oct 14 09:15:34 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519367368 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2519367368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_slow_rsp.2403260046 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1841999263 ps |
| CPU time | 11.39 seconds |
| Started | Oct 14 09:15:23 PM UTC 24 |
| Finished | Oct 14 09:15:36 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403260046 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2403260046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_smoke_zero_delays.1839609968 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 25078203 ps |
| CPU time | 1.6 seconds |
| Started | Oct 14 09:15:22 PM UTC 24 |
| Finished | Oct 14 09:15:24 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839609968 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays.1839609968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all.1534251937 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3687520460 ps |
| CPU time | 59.46 seconds |
| Started | Oct 14 09:15:26 PM UTC 24 |
| Finished | Oct 14 09:16:27 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534251937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1534251937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_error.1495464701 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 5580745800 ps |
| CPU time | 65.55 seconds |
| Started | Oct 14 09:15:27 PM UTC 24 |
| Finished | Oct 14 09:16:35 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495464701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1495464701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_rand_reset.1124011347 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 7460876993 ps |
| CPU time | 82.85 seconds |
| Started | Oct 14 09:15:26 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124011347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_rand_reset.1124011347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_stress_all_with_reset_error.3743538512 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 221779068 ps |
| CPU time | 22.26 seconds |
| Started | Oct 14 09:15:27 PM UTC 24 |
| Finished | Oct 14 09:15:51 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743538512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_reset_error.3743538512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/18.xbar_unmapped_addr.334515353 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 97314695 ps |
| CPU time | 1.89 seconds |
| Started | Oct 14 09:15:25 PM UTC 24 |
| Finished | Oct 14 09:15:28 PM UTC 24 |
| Peak memory | 209400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334515353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.334515353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/18.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_access_same_device.1522543028 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 22973437 ps |
| CPU time | 3.45 seconds |
| Started | Oct 14 09:15:32 PM UTC 24 |
| Finished | Oct 14 09:15:37 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522543028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device.1522543028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_and_unmapped_addr.32740268 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 526489503 ps |
| CPU time | 5.99 seconds |
| Started | Oct 14 09:15:36 PM UTC 24 |
| Finished | Oct 14 09:15:43 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32740268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr.32740268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_error_random.3345378327 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 50563478 ps |
| CPU time | 6.51 seconds |
| Started | Oct 14 09:15:32 PM UTC 24 |
| Finished | Oct 14 09:15:40 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345378327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3345378327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random.1116721839 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 121512289 ps |
| CPU time | 3.4 seconds |
| Started | Oct 14 09:15:30 PM UTC 24 |
| Finished | Oct 14 09:15:35 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116721839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random.1116721839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_large_delays.592669626 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 54740194447 ps |
| CPU time | 106.29 seconds |
| Started | Oct 14 09:15:31 PM UTC 24 |
| Finished | Oct 14 09:17:19 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592669626 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.592669626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_slow_rsp.2870737601 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5797230417 ps |
| CPU time | 38.15 seconds |
| Started | Oct 14 09:15:31 PM UTC 24 |
| Finished | Oct 14 09:16:10 PM UTC 24 |
| Peak memory | 213116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870737601 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2870737601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_random_zero_delays.2070671551 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 56971766 ps |
| CPU time | 8.24 seconds |
| Started | Oct 14 09:15:30 PM UTC 24 |
| Finished | Oct 14 09:15:40 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070671551 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delays.2070671551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_same_source.2948470895 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 5930107090 ps |
| CPU time | 11.39 seconds |
| Started | Oct 14 09:15:32 PM UTC 24 |
| Finished | Oct 14 09:15:45 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948470895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2948470895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke.2110701416 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9026053 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 09:15:28 PM UTC 24 |
| Finished | Oct 14 09:15:30 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110701416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2110701416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_large_delays.331559200 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 7146415369 ps |
| CPU time | 12.29 seconds |
| Started | Oct 14 09:15:29 PM UTC 24 |
| Finished | Oct 14 09:15:42 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331559200 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.331559200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_slow_rsp.4291932013 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1176017368 ps |
| CPU time | 6.35 seconds |
| Started | Oct 14 09:15:29 PM UTC 24 |
| Finished | Oct 14 09:15:36 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291932013 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.4291932013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_smoke_zero_delays.1842906290 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 16042712 ps |
| CPU time | 1.71 seconds |
| Started | Oct 14 09:15:29 PM UTC 24 |
| Finished | Oct 14 09:15:32 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842906290 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delays.1842906290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all.2786817073 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 133086649 ps |
| CPU time | 11.88 seconds |
| Started | Oct 14 09:15:36 PM UTC 24 |
| Finished | Oct 14 09:15:49 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786817073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2786817073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_error.1114031760 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 7340457628 ps |
| CPU time | 50.9 seconds |
| Started | Oct 14 09:15:36 PM UTC 24 |
| Finished | Oct 14 09:16:28 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114031760 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1114031760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_rand_reset.1418474258 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 293150787 ps |
| CPU time | 50.56 seconds |
| Started | Oct 14 09:15:36 PM UTC 24 |
| Finished | Oct 14 09:16:28 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418474258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_rand_reset.1418474258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_stress_all_with_reset_error.2952434453 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 860943620 ps |
| CPU time | 105.73 seconds |
| Started | Oct 14 09:15:37 PM UTC 24 |
| Finished | Oct 14 09:17:25 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952434453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_reset_error.2952434453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/19.xbar_unmapped_addr.2554130449 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 993458410 ps |
| CPU time | 11.53 seconds |
| Started | Oct 14 09:15:35 PM UTC 24 |
| Finished | Oct 14 09:15:48 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554130449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2554130449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/19.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_access_same_device.1552944159 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4950662730 ps |
| CPU time | 14.62 seconds |
| Started | Oct 14 09:12:30 PM UTC 24 |
| Finished | Oct 14 09:12:46 PM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552944159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device.1552944159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_and_unmapped_addr.1583094059 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 531430028 ps |
| CPU time | 8.61 seconds |
| Started | Oct 14 09:12:32 PM UTC 24 |
| Finished | Oct 14 09:12:42 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583094059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.1583094059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_error_random.2158991209 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 18325798 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 09:12:30 PM UTC 24 |
| Finished | Oct 14 09:12:33 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158991209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2158991209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random.861834848 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 117414249 ps |
| CPU time | 5.6 seconds |
| Started | Oct 14 09:12:27 PM UTC 24 |
| Finished | Oct 14 09:12:33 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861834848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random.861834848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_large_delays.2629010833 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1181036105 ps |
| CPU time | 9.22 seconds |
| Started | Oct 14 09:12:27 PM UTC 24 |
| Finished | Oct 14 09:12:37 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629010833 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2629010833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_slow_rsp.2367484705 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 31107507073 ps |
| CPU time | 58.13 seconds |
| Started | Oct 14 09:12:28 PM UTC 24 |
| Finished | Oct 14 09:13:28 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367484705 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2367484705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_random_zero_delays.3275621350 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 86945157 ps |
| CPU time | 3.88 seconds |
| Started | Oct 14 09:12:27 PM UTC 24 |
| Finished | Oct 14 09:12:32 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275621350 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delays.3275621350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_same_source.1978812554 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 153552159 ps |
| CPU time | 4.09 seconds |
| Started | Oct 14 09:12:30 PM UTC 24 |
| Finished | Oct 14 09:12:35 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978812554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1978812554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke.1827494189 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 10549568 ps |
| CPU time | 1.76 seconds |
| Started | Oct 14 09:12:26 PM UTC 24 |
| Finished | Oct 14 09:12:29 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827494189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1827494189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_large_delays.3777072654 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1744759041 ps |
| CPU time | 8.09 seconds |
| Started | Oct 14 09:12:26 PM UTC 24 |
| Finished | Oct 14 09:12:36 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777072654 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3777072654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_slow_rsp.2985950625 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1805233083 ps |
| CPU time | 12.66 seconds |
| Started | Oct 14 09:12:27 PM UTC 24 |
| Finished | Oct 14 09:12:40 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985950625 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2985950625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_smoke_zero_delays.1928328412 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 11474015 ps |
| CPU time | 1.54 seconds |
| Started | Oct 14 09:12:26 PM UTC 24 |
| Finished | Oct 14 09:12:29 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928328412 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays.1928328412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all.1448768351 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 213530669 ps |
| CPU time | 27.19 seconds |
| Started | Oct 14 09:12:32 PM UTC 24 |
| Finished | Oct 14 09:13:01 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448768351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1448768351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_error.1634155648 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5015706098 ps |
| CPU time | 68.48 seconds |
| Started | Oct 14 09:12:34 PM UTC 24 |
| Finished | Oct 14 09:13:45 PM UTC 24 |
| Peak memory | 213096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634155648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1634155648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_stress_all_with_reset_error.3452384832 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 363465356 ps |
| CPU time | 30.1 seconds |
| Started | Oct 14 09:12:37 PM UTC 24 |
| Finished | Oct 14 09:13:08 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452384832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_reset_error.3452384832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/2.xbar_unmapped_addr.1317967766 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 87830333 ps |
| CPU time | 5.17 seconds |
| Started | Oct 14 09:12:30 PM UTC 24 |
| Finished | Oct 14 09:12:37 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317967766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1317967766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/2.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_access_same_device.762817233 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 290503231 ps |
| CPU time | 9.13 seconds |
| Started | Oct 14 09:15:41 PM UTC 24 |
| Finished | Oct 14 09:15:51 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762817233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device.762817233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_and_unmapped_addr.4050834511 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 390062089 ps |
| CPU time | 7.57 seconds |
| Started | Oct 14 09:15:43 PM UTC 24 |
| Finished | Oct 14 09:15:51 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050834511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr.4050834511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_error_random.216486485 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3364428647 ps |
| CPU time | 14.5 seconds |
| Started | Oct 14 09:15:41 PM UTC 24 |
| Finished | Oct 14 09:15:57 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216486485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.216486485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random.1352058570 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2035475140 ps |
| CPU time | 15 seconds |
| Started | Oct 14 09:15:37 PM UTC 24 |
| Finished | Oct 14 09:15:53 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352058570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random.1352058570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_large_delays.1296029469 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 111430608386 ps |
| CPU time | 65.29 seconds |
| Started | Oct 14 09:15:39 PM UTC 24 |
| Finished | Oct 14 09:16:46 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296029469 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1296029469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_slow_rsp.1182363429 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 14034089430 ps |
| CPU time | 91.18 seconds |
| Started | Oct 14 09:15:39 PM UTC 24 |
| Finished | Oct 14 09:17:12 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182363429 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1182363429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_random_zero_delays.2860265812 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 43256124 ps |
| CPU time | 2.5 seconds |
| Started | Oct 14 09:15:39 PM UTC 24 |
| Finished | Oct 14 09:15:42 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860265812 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_delays.2860265812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_same_source.1832388581 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 676563834 ps |
| CPU time | 4.69 seconds |
| Started | Oct 14 09:15:41 PM UTC 24 |
| Finished | Oct 14 09:15:47 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832388581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1832388581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke.3658724353 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 9195526 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 09:15:37 PM UTC 24 |
| Finished | Oct 14 09:15:40 PM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658724353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.3658724353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_large_delays.1641358847 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2671646024 ps |
| CPU time | 12.11 seconds |
| Started | Oct 14 09:15:37 PM UTC 24 |
| Finished | Oct 14 09:15:51 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641358847 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1641358847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_slow_rsp.2376125434 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 6328448933 ps |
| CPU time | 10.34 seconds |
| Started | Oct 14 09:15:37 PM UTC 24 |
| Finished | Oct 14 09:15:49 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376125434 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2376125434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_smoke_zero_delays.1814058730 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 9572229 ps |
| CPU time | 1.57 seconds |
| Started | Oct 14 09:15:37 PM UTC 24 |
| Finished | Oct 14 09:15:40 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814058730 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays.1814058730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all.3619643382 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 415758084 ps |
| CPU time | 10.04 seconds |
| Started | Oct 14 09:15:43 PM UTC 24 |
| Finished | Oct 14 09:15:54 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619643382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3619643382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_error.359892453 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2387561872 ps |
| CPU time | 31.21 seconds |
| Started | Oct 14 09:15:43 PM UTC 24 |
| Finished | Oct 14 09:16:15 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359892453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.359892453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_rand_reset.2451652036 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 795645299 ps |
| CPU time | 75.73 seconds |
| Started | Oct 14 09:15:43 PM UTC 24 |
| Finished | Oct 14 09:17:00 PM UTC 24 |
| Peak memory | 215008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451652036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_rand_reset.2451652036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_stress_all_with_reset_error.1101993572 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7850623155 ps |
| CPU time | 165.61 seconds |
| Started | Oct 14 09:15:44 PM UTC 24 |
| Finished | Oct 14 09:18:32 PM UTC 24 |
| Peak memory | 217564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101993572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_reset_error.1101993572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/20.xbar_unmapped_addr.529309713 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 565431156 ps |
| CPU time | 11.7 seconds |
| Started | Oct 14 09:15:41 PM UTC 24 |
| Finished | Oct 14 09:15:54 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529309713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.529309713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/20.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device.808077725 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 21662726 ps |
| CPU time | 4.45 seconds |
| Started | Oct 14 09:15:51 PM UTC 24 |
| Finished | Oct 14 09:15:57 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808077725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device.808077725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_access_same_device_slow_rsp.1873600724 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2432062674 ps |
| CPU time | 29.41 seconds |
| Started | Oct 14 09:15:52 PM UTC 24 |
| Finished | Oct 14 09:16:23 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873600724 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device_slow_rsp.1873600724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_and_unmapped_addr.732355047 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 32058539 ps |
| CPU time | 1.94 seconds |
| Started | Oct 14 09:15:55 PM UTC 24 |
| Finished | Oct 14 09:15:58 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732355047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr.732355047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_error_random.373137414 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 4189798495 ps |
| CPU time | 17.33 seconds |
| Started | Oct 14 09:15:52 PM UTC 24 |
| Finished | Oct 14 09:16:11 PM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373137414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.373137414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random.1405294223 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 637724755 ps |
| CPU time | 15.61 seconds |
| Started | Oct 14 09:15:50 PM UTC 24 |
| Finished | Oct 14 09:16:07 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405294223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random.1405294223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_large_delays.157557732 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 23874234670 ps |
| CPU time | 37.42 seconds |
| Started | Oct 14 09:15:50 PM UTC 24 |
| Finished | Oct 14 09:16:29 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157557732 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.157557732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_slow_rsp.1568164419 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 11529474861 ps |
| CPU time | 61.61 seconds |
| Started | Oct 14 09:15:51 PM UTC 24 |
| Finished | Oct 14 09:16:54 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568164419 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1568164419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_random_zero_delays.1966970942 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 14082493 ps |
| CPU time | 2.16 seconds |
| Started | Oct 14 09:15:50 PM UTC 24 |
| Finished | Oct 14 09:15:53 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966970942 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_delays.1966970942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_same_source.62275813 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 65716396 ps |
| CPU time | 8.15 seconds |
| Started | Oct 14 09:15:52 PM UTC 24 |
| Finished | Oct 14 09:16:02 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62275813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.62275813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke.1467505475 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 46498717 ps |
| CPU time | 2.19 seconds |
| Started | Oct 14 09:15:45 PM UTC 24 |
| Finished | Oct 14 09:15:48 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467505475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1467505475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_large_delays.3110107724 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2146391455 ps |
| CPU time | 14.01 seconds |
| Started | Oct 14 09:15:47 PM UTC 24 |
| Finished | Oct 14 09:16:03 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110107724 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3110107724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_slow_rsp.3289677499 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 749816503 ps |
| CPU time | 6.2 seconds |
| Started | Oct 14 09:15:49 PM UTC 24 |
| Finished | Oct 14 09:15:56 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289677499 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3289677499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_smoke_zero_delays.3959515872 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 14314868 ps |
| CPU time | 1.64 seconds |
| Started | Oct 14 09:15:47 PM UTC 24 |
| Finished | Oct 14 09:15:50 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959515872 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays.3959515872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all.4157608313 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 495014473 ps |
| CPU time | 6.4 seconds |
| Started | Oct 14 09:15:55 PM UTC 24 |
| Finished | Oct 14 09:16:02 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157608313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.4157608313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_error.4230139673 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 237703585 ps |
| CPU time | 22.69 seconds |
| Started | Oct 14 09:15:57 PM UTC 24 |
| Finished | Oct 14 09:16:21 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230139673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.4230139673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_rand_reset.3853001713 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 6920468674 ps |
| CPU time | 80.72 seconds |
| Started | Oct 14 09:15:55 PM UTC 24 |
| Finished | Oct 14 09:17:18 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853001713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_rand_reset.3853001713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_stress_all_with_reset_error.2664393055 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2436620966 ps |
| CPU time | 39.34 seconds |
| Started | Oct 14 09:15:58 PM UTC 24 |
| Finished | Oct 14 09:16:39 PM UTC 24 |
| Peak memory | 213104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664393055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_reset_error.2664393055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/21.xbar_unmapped_addr.3752217786 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 165864550 ps |
| CPU time | 4.02 seconds |
| Started | Oct 14 09:15:54 PM UTC 24 |
| Finished | Oct 14 09:15:59 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752217786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3752217786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/21.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device.2132248267 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 25795349 ps |
| CPU time | 6 seconds |
| Started | Oct 14 09:16:03 PM UTC 24 |
| Finished | Oct 14 09:16:11 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132248267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device.2132248267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_access_same_device_slow_rsp.1659692866 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 17598709704 ps |
| CPU time | 137.61 seconds |
| Started | Oct 14 09:16:04 PM UTC 24 |
| Finished | Oct 14 09:18:25 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659692866 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device_slow_rsp.1659692866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_and_unmapped_addr.4235277174 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2225297019 ps |
| CPU time | 6.69 seconds |
| Started | Oct 14 09:16:11 PM UTC 24 |
| Finished | Oct 14 09:16:19 PM UTC 24 |
| Peak memory | 211052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235277174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr.4235277174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_error_random.1682891864 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 650506480 ps |
| CPU time | 2.29 seconds |
| Started | Oct 14 09:16:08 PM UTC 24 |
| Finished | Oct 14 09:16:11 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682891864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1682891864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random.3124876205 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 5307433135 ps |
| CPU time | 18.25 seconds |
| Started | Oct 14 09:16:02 PM UTC 24 |
| Finished | Oct 14 09:16:22 PM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124876205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random.3124876205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_large_delays.1527317254 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 28589376950 ps |
| CPU time | 53.8 seconds |
| Started | Oct 14 09:16:03 PM UTC 24 |
| Finished | Oct 14 09:16:59 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527317254 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1527317254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_slow_rsp.638260280 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 19861375542 ps |
| CPU time | 52.18 seconds |
| Started | Oct 14 09:16:03 PM UTC 24 |
| Finished | Oct 14 09:16:57 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638260280 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.638260280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_random_zero_delays.33979138 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 26572621 ps |
| CPU time | 3.78 seconds |
| Started | Oct 14 09:16:02 PM UTC 24 |
| Finished | Oct 14 09:16:07 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33979138 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_delays.33979138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_same_source.1814653454 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 42896008 ps |
| CPU time | 5.1 seconds |
| Started | Oct 14 09:16:08 PM UTC 24 |
| Finished | Oct 14 09:16:14 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814653454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1814653454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke.3637404691 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 19535323 ps |
| CPU time | 1.62 seconds |
| Started | Oct 14 09:15:58 PM UTC 24 |
| Finished | Oct 14 09:16:01 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637404691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3637404691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_large_delays.4030785562 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 3776964429 ps |
| CPU time | 16.38 seconds |
| Started | Oct 14 09:16:00 PM UTC 24 |
| Finished | Oct 14 09:16:18 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030785562 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.4030785562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_slow_rsp.2535888570 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4879337118 ps |
| CPU time | 22.18 seconds |
| Started | Oct 14 09:16:02 PM UTC 24 |
| Finished | Oct 14 09:16:26 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535888570 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2535888570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_smoke_zero_delays.682222224 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 10307050 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 09:15:59 PM UTC 24 |
| Finished | Oct 14 09:16:01 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682222224 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.682222224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all.1865292552 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2287779134 ps |
| CPU time | 37.81 seconds |
| Started | Oct 14 09:16:12 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865292552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1865292552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_error.3029470156 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 4893573310 ps |
| CPU time | 12.73 seconds |
| Started | Oct 14 09:16:12 PM UTC 24 |
| Finished | Oct 14 09:16:26 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029470156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3029470156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_rand_reset.1987057345 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 400099362 ps |
| CPU time | 45.86 seconds |
| Started | Oct 14 09:16:12 PM UTC 24 |
| Finished | Oct 14 09:16:59 PM UTC 24 |
| Peak memory | 215000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987057345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_rand_reset.1987057345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_stress_all_with_reset_error.4190400229 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 924208338 ps |
| CPU time | 94.51 seconds |
| Started | Oct 14 09:16:13 PM UTC 24 |
| Finished | Oct 14 09:17:49 PM UTC 24 |
| Peak memory | 215088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190400229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_reset_error.4190400229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/22.xbar_unmapped_addr.235589166 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 27227640 ps |
| CPU time | 2.26 seconds |
| Started | Oct 14 09:16:10 PM UTC 24 |
| Finished | Oct 14 09:16:13 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235589166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.235589166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/22.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device.527020179 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1886606671 ps |
| CPU time | 18.01 seconds |
| Started | Oct 14 09:16:18 PM UTC 24 |
| Finished | Oct 14 09:16:37 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527020179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device.527020179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_access_same_device_slow_rsp.621423413 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 10176087303 ps |
| CPU time | 75.8 seconds |
| Started | Oct 14 09:16:18 PM UTC 24 |
| Finished | Oct 14 09:17:36 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621423413 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device_slow_rsp.621423413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_and_unmapped_addr.260198638 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 155337731 ps |
| CPU time | 4.97 seconds |
| Started | Oct 14 09:16:21 PM UTC 24 |
| Finished | Oct 14 09:16:27 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260198638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_addr.260198638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_error_random.2624149176 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 402147703 ps |
| CPU time | 2.58 seconds |
| Started | Oct 14 09:16:20 PM UTC 24 |
| Finished | Oct 14 09:16:24 PM UTC 24 |
| Peak memory | 210888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624149176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2624149176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random.3296503424 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1229421304 ps |
| CPU time | 19.08 seconds |
| Started | Oct 14 09:16:16 PM UTC 24 |
| Finished | Oct 14 09:16:37 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296503424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random.3296503424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_large_delays.1795750184 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 33242064962 ps |
| CPU time | 101.47 seconds |
| Started | Oct 14 09:16:18 PM UTC 24 |
| Finished | Oct 14 09:18:01 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795750184 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1795750184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_slow_rsp.3499746903 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 5275524197 ps |
| CPU time | 23.29 seconds |
| Started | Oct 14 09:16:18 PM UTC 24 |
| Finished | Oct 14 09:16:42 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499746903 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3499746903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_random_zero_delays.209222129 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 49489022 ps |
| CPU time | 3.55 seconds |
| Started | Oct 14 09:16:16 PM UTC 24 |
| Finished | Oct 14 09:16:21 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209222129 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_delays.209222129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_same_source.3458135267 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 508464606 ps |
| CPU time | 11.99 seconds |
| Started | Oct 14 09:16:20 PM UTC 24 |
| Finished | Oct 14 09:16:34 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458135267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3458135267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke.3957606441 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 60573296 ps |
| CPU time | 2 seconds |
| Started | Oct 14 09:16:13 PM UTC 24 |
| Finished | Oct 14 09:16:16 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957606441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3957606441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_large_delays.3614281592 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4251821078 ps |
| CPU time | 18.32 seconds |
| Started | Oct 14 09:16:14 PM UTC 24 |
| Finished | Oct 14 09:16:34 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614281592 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3614281592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_slow_rsp.1977375327 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1395038784 ps |
| CPU time | 9.05 seconds |
| Started | Oct 14 09:16:16 PM UTC 24 |
| Finished | Oct 14 09:16:26 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977375327 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.1977375327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_smoke_zero_delays.3688567256 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 9345055 ps |
| CPU time | 1.44 seconds |
| Started | Oct 14 09:16:13 PM UTC 24 |
| Finished | Oct 14 09:16:16 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688567256 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays.3688567256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all.1387743884 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 463920416 ps |
| CPU time | 9.02 seconds |
| Started | Oct 14 09:16:21 PM UTC 24 |
| Finished | Oct 14 09:16:31 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387743884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1387743884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_error.660050353 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 7182875651 ps |
| CPU time | 52.09 seconds |
| Started | Oct 14 09:16:22 PM UTC 24 |
| Finished | Oct 14 09:17:16 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660050353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.660050353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_rand_reset.4233724524 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 7435181 ps |
| CPU time | 11.3 seconds |
| Started | Oct 14 09:16:22 PM UTC 24 |
| Finished | Oct 14 09:16:34 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233724524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_rand_reset.4233724524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_stress_all_with_reset_error.3177263285 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 233041145 ps |
| CPU time | 16.12 seconds |
| Started | Oct 14 09:16:22 PM UTC 24 |
| Finished | Oct 14 09:16:39 PM UTC 24 |
| Peak memory | 213044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177263285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_reset_error.3177263285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/23.xbar_unmapped_addr.1965589301 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3436654906 ps |
| CPU time | 17.86 seconds |
| Started | Oct 14 09:16:21 PM UTC 24 |
| Finished | Oct 14 09:16:40 PM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965589301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1965589301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/23.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device.2130527976 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 48757654 ps |
| CPU time | 7.61 seconds |
| Started | Oct 14 09:16:29 PM UTC 24 |
| Finished | Oct 14 09:16:38 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130527976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.2130527976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_access_same_device_slow_rsp.1056558140 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 10641998504 ps |
| CPU time | 81 seconds |
| Started | Oct 14 09:16:30 PM UTC 24 |
| Finished | Oct 14 09:17:52 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056558140 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device_slow_rsp.1056558140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_and_unmapped_addr.1839438728 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 24572494 ps |
| CPU time | 1.91 seconds |
| Started | Oct 14 09:16:30 PM UTC 24 |
| Finished | Oct 14 09:16:33 PM UTC 24 |
| Peak memory | 211964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839438728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_addr.1839438728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_error_random.2434628420 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2876697179 ps |
| CPU time | 7.25 seconds |
| Started | Oct 14 09:16:30 PM UTC 24 |
| Finished | Oct 14 09:16:38 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434628420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2434628420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random.3098143524 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 75027751 ps |
| CPU time | 2.36 seconds |
| Started | Oct 14 09:16:27 PM UTC 24 |
| Finished | Oct 14 09:16:31 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098143524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random.3098143524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_large_delays.4138148573 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 5692840735 ps |
| CPU time | 20.43 seconds |
| Started | Oct 14 09:16:27 PM UTC 24 |
| Finished | Oct 14 09:16:49 PM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138148573 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.4138148573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_slow_rsp.2676756535 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5251750295 ps |
| CPU time | 43.86 seconds |
| Started | Oct 14 09:16:27 PM UTC 24 |
| Finished | Oct 14 09:17:13 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676756535 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2676756535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_random_zero_delays.2405603635 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 75149961 ps |
| CPU time | 10.57 seconds |
| Started | Oct 14 09:16:27 PM UTC 24 |
| Finished | Oct 14 09:16:39 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405603635 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_delays.2405603635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_same_source.2433999185 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 932371019 ps |
| CPU time | 7.92 seconds |
| Started | Oct 14 09:16:30 PM UTC 24 |
| Finished | Oct 14 09:16:39 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433999185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.2433999185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke.1682199443 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 50174838 ps |
| CPU time | 2.11 seconds |
| Started | Oct 14 09:16:24 PM UTC 24 |
| Finished | Oct 14 09:16:27 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682199443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1682199443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_large_delays.852275674 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 4169713181 ps |
| CPU time | 15.63 seconds |
| Started | Oct 14 09:16:25 PM UTC 24 |
| Finished | Oct 14 09:16:42 PM UTC 24 |
| Peak memory | 213088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852275674 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.852275674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_slow_rsp.572934644 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2385558999 ps |
| CPU time | 9.33 seconds |
| Started | Oct 14 09:16:25 PM UTC 24 |
| Finished | Oct 14 09:16:36 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572934644 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.572934644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_smoke_zero_delays.2415418410 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 11606035 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 09:16:24 PM UTC 24 |
| Finished | Oct 14 09:16:26 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415418410 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays.2415418410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all.323947736 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 6014023677 ps |
| CPU time | 24.86 seconds |
| Started | Oct 14 09:16:31 PM UTC 24 |
| Finished | Oct 14 09:16:57 PM UTC 24 |
| Peak memory | 213100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323947736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.323947736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_error.2622032661 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 18622675862 ps |
| CPU time | 127.51 seconds |
| Started | Oct 14 09:16:33 PM UTC 24 |
| Finished | Oct 14 09:18:43 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622032661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2622032661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_rand_reset.2576461151 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 259932365 ps |
| CPU time | 14.59 seconds |
| Started | Oct 14 09:16:31 PM UTC 24 |
| Finished | Oct 14 09:16:47 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576461151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_rand_reset.2576461151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_stress_all_with_reset_error.1131242246 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 168012882 ps |
| CPU time | 23.15 seconds |
| Started | Oct 14 09:16:33 PM UTC 24 |
| Finished | Oct 14 09:16:57 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131242246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_reset_error.1131242246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/24.xbar_unmapped_addr.1235660185 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 157779770 ps |
| CPU time | 2.81 seconds |
| Started | Oct 14 09:16:30 PM UTC 24 |
| Finished | Oct 14 09:16:34 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235660185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1235660185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/24.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_access_same_device_slow_rsp.2823875385 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 26592395215 ps |
| CPU time | 216.08 seconds |
| Started | Oct 14 09:16:38 PM UTC 24 |
| Finished | Oct 14 09:20:17 PM UTC 24 |
| Peak memory | 214760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823875385 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device_slow_rsp.2823875385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_and_unmapped_addr.2988343145 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 56259688 ps |
| CPU time | 3.45 seconds |
| Started | Oct 14 09:16:39 PM UTC 24 |
| Finished | Oct 14 09:16:44 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988343145 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr.2988343145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_error_random.2891815914 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4235951489 ps |
| CPU time | 10.33 seconds |
| Started | Oct 14 09:16:39 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 213112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891815914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2891815914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random.3188059076 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1940326558 ps |
| CPU time | 14.17 seconds |
| Started | Oct 14 09:16:37 PM UTC 24 |
| Finished | Oct 14 09:16:53 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188059076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random.3188059076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_large_delays.74085802 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 3895277301 ps |
| CPU time | 21.68 seconds |
| Started | Oct 14 09:16:38 PM UTC 24 |
| Finished | Oct 14 09:17:00 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74085802 -assert nopostproc +UVM_T ESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.74085802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_slow_rsp.4251920159 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 5078812248 ps |
| CPU time | 31.95 seconds |
| Started | Oct 14 09:16:38 PM UTC 24 |
| Finished | Oct 14 09:17:11 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251920159 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.4251920159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_random_zero_delays.865226046 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 148652180 ps |
| CPU time | 5.9 seconds |
| Started | Oct 14 09:16:38 PM UTC 24 |
| Finished | Oct 14 09:16:44 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865226046 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_delays.865226046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_same_source.253180615 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 454017813 ps |
| CPU time | 9.2 seconds |
| Started | Oct 14 09:16:39 PM UTC 24 |
| Finished | Oct 14 09:16:50 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253180615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.253180615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke.4075504391 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 8896342 ps |
| CPU time | 1.65 seconds |
| Started | Oct 14 09:16:33 PM UTC 24 |
| Finished | Oct 14 09:16:36 PM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075504391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.4075504391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_large_delays.2061488360 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1789241842 ps |
| CPU time | 12.97 seconds |
| Started | Oct 14 09:16:35 PM UTC 24 |
| Finished | Oct 14 09:16:49 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061488360 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2061488360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_slow_rsp.909115409 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2161354274 ps |
| CPU time | 6.99 seconds |
| Started | Oct 14 09:16:35 PM UTC 24 |
| Finished | Oct 14 09:16:43 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909115409 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.909115409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_smoke_zero_delays.2763683891 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 28233468 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 09:16:35 PM UTC 24 |
| Finished | Oct 14 09:16:37 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763683891 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays.2763683891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all.1597621103 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 5967869431 ps |
| CPU time | 96.34 seconds |
| Started | Oct 14 09:16:40 PM UTC 24 |
| Finished | Oct 14 09:18:18 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597621103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1597621103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_error.1744348060 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 7758113559 ps |
| CPU time | 42.65 seconds |
| Started | Oct 14 09:16:42 PM UTC 24 |
| Finished | Oct 14 09:17:26 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744348060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.1744348060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_rand_reset.908445289 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 8846193169 ps |
| CPU time | 172.72 seconds |
| Started | Oct 14 09:16:40 PM UTC 24 |
| Finished | Oct 14 09:19:35 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908445289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_rand_reset.908445289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_stress_all_with_reset_error.3192308982 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 189495484 ps |
| CPU time | 16.4 seconds |
| Started | Oct 14 09:16:42 PM UTC 24 |
| Finished | Oct 14 09:16:59 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192308982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_reset_error.3192308982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/25.xbar_unmapped_addr.3822488902 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1728788101 ps |
| CPU time | 10.39 seconds |
| Started | Oct 14 09:16:39 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822488902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3822488902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/25.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device.2901295841 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 75342126 ps |
| CPU time | 9.92 seconds |
| Started | Oct 14 09:16:45 PM UTC 24 |
| Finished | Oct 14 09:16:56 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901295841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device.2901295841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_access_same_device_slow_rsp.826863426 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3351456391 ps |
| CPU time | 18.85 seconds |
| Started | Oct 14 09:16:45 PM UTC 24 |
| Finished | Oct 14 09:17:05 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826863426 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device_slow_rsp.826863426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_and_unmapped_addr.317690505 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3853309254 ps |
| CPU time | 8.57 seconds |
| Started | Oct 14 09:16:47 PM UTC 24 |
| Finished | Oct 14 09:16:57 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317690505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr.317690505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_error_random.721583728 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 64576984 ps |
| CPU time | 6.04 seconds |
| Started | Oct 14 09:16:45 PM UTC 24 |
| Finished | Oct 14 09:16:52 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721583728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.721583728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random.2262441701 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 91246536 ps |
| CPU time | 7.43 seconds |
| Started | Oct 14 09:16:42 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262441701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random.2262441701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_large_delays.2056142184 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 10323676756 ps |
| CPU time | 24.5 seconds |
| Started | Oct 14 09:16:44 PM UTC 24 |
| Finished | Oct 14 09:17:09 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056142184 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2056142184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_slow_rsp.3487592548 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 9806772029 ps |
| CPU time | 49.64 seconds |
| Started | Oct 14 09:16:44 PM UTC 24 |
| Finished | Oct 14 09:17:35 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487592548 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3487592548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_random_zero_delays.1850440359 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 281583116 ps |
| CPU time | 7.39 seconds |
| Started | Oct 14 09:16:44 PM UTC 24 |
| Finished | Oct 14 09:16:52 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850440359 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_delays.1850440359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_same_source.1156205253 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 10315884 ps |
| CPU time | 1.73 seconds |
| Started | Oct 14 09:16:45 PM UTC 24 |
| Finished | Oct 14 09:16:48 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156205253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1156205253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke.3069914732 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 17614101 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 09:16:42 PM UTC 24 |
| Finished | Oct 14 09:16:44 PM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069914732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3069914732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_large_delays.3504404142 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3133420242 ps |
| CPU time | 7.61 seconds |
| Started | Oct 14 09:16:42 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504404142 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.3504404142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_slow_rsp.2388145723 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 745601875 ps |
| CPU time | 7.27 seconds |
| Started | Oct 14 09:16:42 PM UTC 24 |
| Finished | Oct 14 09:16:50 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388145723 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.2388145723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_smoke_zero_delays.1177190289 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 23145397 ps |
| CPU time | 1.62 seconds |
| Started | Oct 14 09:16:42 PM UTC 24 |
| Finished | Oct 14 09:16:45 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177190289 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays.1177190289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all.3595687055 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 3737674385 ps |
| CPU time | 53.79 seconds |
| Started | Oct 14 09:16:47 PM UTC 24 |
| Finished | Oct 14 09:17:43 PM UTC 24 |
| Peak memory | 213076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595687055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3595687055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_error.3107545432 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 8236373092 ps |
| CPU time | 45.39 seconds |
| Started | Oct 14 09:16:49 PM UTC 24 |
| Finished | Oct 14 09:17:36 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107545432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3107545432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_rand_reset.2157434450 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 901338638 ps |
| CPU time | 112 seconds |
| Started | Oct 14 09:16:49 PM UTC 24 |
| Finished | Oct 14 09:18:43 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157434450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_rand_reset.2157434450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_stress_all_with_reset_error.1598672196 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 965927072 ps |
| CPU time | 93.35 seconds |
| Started | Oct 14 09:16:50 PM UTC 24 |
| Finished | Oct 14 09:18:26 PM UTC 24 |
| Peak memory | 213104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598672196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_reset_error.1598672196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/26.xbar_unmapped_addr.3747966994 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 95855477 ps |
| CPU time | 2.54 seconds |
| Started | Oct 14 09:16:47 PM UTC 24 |
| Finished | Oct 14 09:16:51 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747966994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3747966994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/26.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_access_same_device_slow_rsp.2284000066 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 39093932258 ps |
| CPU time | 193.64 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:20:10 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284000066 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device_slow_rsp.2284000066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_and_unmapped_addr.1037447851 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 605800340 ps |
| CPU time | 11.57 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:07 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037447851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr.1037447851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_error_random.3611346330 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 56670910 ps |
| CPU time | 4.59 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:00 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611346330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3611346330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random.1943550193 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1701209468 ps |
| CPU time | 15.54 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:10 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943550193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random.1943550193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_large_delays.2274271190 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 12898025941 ps |
| CPU time | 61.18 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:57 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274271190 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2274271190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_slow_rsp.4267250631 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 7031540210 ps |
| CPU time | 38.78 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:34 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267250631 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.4267250631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_random_zero_delays.3781242209 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 95756194 ps |
| CPU time | 6.48 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:01 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781242209 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_delays.3781242209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_same_source.992979541 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 577120966 ps |
| CPU time | 8.05 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:03 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992979541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.992979541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke.3591699863 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 52929496 ps |
| CPU time | 2.02 seconds |
| Started | Oct 14 09:16:50 PM UTC 24 |
| Finished | Oct 14 09:16:53 PM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591699863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3591699863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_large_delays.2840553213 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2639841666 ps |
| CPU time | 11.2 seconds |
| Started | Oct 14 09:16:51 PM UTC 24 |
| Finished | Oct 14 09:17:03 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840553213 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2840553213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_slow_rsp.3585097186 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 4643717682 ps |
| CPU time | 7.32 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:17:02 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585097186 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.3585097186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_smoke_zero_delays.2928392863 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 10123464 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 09:16:50 PM UTC 24 |
| Finished | Oct 14 09:16:53 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928392863 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays.2928392863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all.2972315739 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 6705626412 ps |
| CPU time | 93.34 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:18:29 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972315739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2972315739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_error.4021178593 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3752559588 ps |
| CPU time | 12.33 seconds |
| Started | Oct 14 09:16:56 PM UTC 24 |
| Finished | Oct 14 09:17:09 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021178593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.4021178593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_rand_reset.3450389376 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 7845640870 ps |
| CPU time | 149.45 seconds |
| Started | Oct 14 09:16:56 PM UTC 24 |
| Finished | Oct 14 09:19:28 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450389376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_rand_reset.3450389376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_stress_all_with_reset_error.3139817813 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 516031350 ps |
| CPU time | 92.83 seconds |
| Started | Oct 14 09:16:56 PM UTC 24 |
| Finished | Oct 14 09:18:31 PM UTC 24 |
| Peak memory | 217136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139817813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_reset_error.3139817813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/27.xbar_unmapped_addr.636849107 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 72393132 ps |
| CPU time | 1.42 seconds |
| Started | Oct 14 09:16:54 PM UTC 24 |
| Finished | Oct 14 09:16:56 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636849107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.636849107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/27.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device.2624076131 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 160058857 ps |
| CPU time | 4.6 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:07 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624076131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device.2624076131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_access_same_device_slow_rsp.2493324417 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 16178308744 ps |
| CPU time | 130.23 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:19:13 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493324417 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device_slow_rsp.2493324417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_and_unmapped_addr.2231813971 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 30534714 ps |
| CPU time | 3.95 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:06 PM UTC 24 |
| Peak memory | 212908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231813971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr.2231813971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_error_random.66325339 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 529772863 ps |
| CPU time | 9.28 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:12 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66325339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.66325339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random.1389797481 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 90199704 ps |
| CPU time | 4.6 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:06 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389797481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random.1389797481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_large_delays.4230410657 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 15244886134 ps |
| CPU time | 30.93 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:33 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230410657 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.4230410657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_slow_rsp.1894164516 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3579345502 ps |
| CPU time | 32.31 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:35 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894164516 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1894164516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_random_zero_delays.2991016873 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 56138368 ps |
| CPU time | 8.87 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:11 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991016873 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_delays.2991016873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_same_source.1577629027 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 539670079 ps |
| CPU time | 9.13 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:11 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577629027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1577629027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke.2058560910 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 206619098 ps |
| CPU time | 1.55 seconds |
| Started | Oct 14 09:16:56 PM UTC 24 |
| Finished | Oct 14 09:16:59 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058560910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2058560910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_large_delays.3360684201 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2595899765 ps |
| CPU time | 7.75 seconds |
| Started | Oct 14 09:16:58 PM UTC 24 |
| Finished | Oct 14 09:17:07 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360684201 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3360684201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_slow_rsp.3683502988 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 819238590 ps |
| CPU time | 6.08 seconds |
| Started | Oct 14 09:16:58 PM UTC 24 |
| Finished | Oct 14 09:17:06 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683502988 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3683502988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_smoke_zero_delays.3991095090 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 28503476 ps |
| CPU time | 1.25 seconds |
| Started | Oct 14 09:16:58 PM UTC 24 |
| Finished | Oct 14 09:17:00 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991095090 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays.3991095090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all.3339044530 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 172270411 ps |
| CPU time | 12.23 seconds |
| Started | Oct 14 09:17:03 PM UTC 24 |
| Finished | Oct 14 09:17:17 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339044530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.3339044530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_error.3869520202 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2241414531 ps |
| CPU time | 28.17 seconds |
| Started | Oct 14 09:17:03 PM UTC 24 |
| Finished | Oct 14 09:17:33 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869520202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.3869520202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_rand_reset.4181225278 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 1390184542 ps |
| CPU time | 101.52 seconds |
| Started | Oct 14 09:17:03 PM UTC 24 |
| Finished | Oct 14 09:18:47 PM UTC 24 |
| Peak memory | 217060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181225278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_rand_reset.4181225278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_stress_all_with_reset_error.1521945858 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 82858460 ps |
| CPU time | 5.61 seconds |
| Started | Oct 14 09:17:03 PM UTC 24 |
| Finished | Oct 14 09:17:10 PM UTC 24 |
| Peak memory | 210992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521945858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_reset_error.1521945858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/28.xbar_unmapped_addr.744634808 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 573591420 ps |
| CPU time | 12.56 seconds |
| Started | Oct 14 09:17:01 PM UTC 24 |
| Finished | Oct 14 09:17:15 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744634808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.744634808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/28.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device.3390183649 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 883895702 ps |
| CPU time | 9.54 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:17:19 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390183649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device.3390183649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_access_same_device_slow_rsp.491548370 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 20596129070 ps |
| CPU time | 158.76 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:19:50 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491548370 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device_slow_rsp.491548370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_and_unmapped_addr.408702700 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 60002013 ps |
| CPU time | 1.98 seconds |
| Started | Oct 14 09:17:13 PM UTC 24 |
| Finished | Oct 14 09:17:16 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408702700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.408702700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_error_random.124629199 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 352454704 ps |
| CPU time | 4.84 seconds |
| Started | Oct 14 09:17:13 PM UTC 24 |
| Finished | Oct 14 09:17:18 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124629199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.124629199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random.3798419016 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1405825292 ps |
| CPU time | 11.81 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:17:21 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798419016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random.3798419016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_large_delays.2528781255 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 7269450484 ps |
| CPU time | 20.69 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:17:30 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528781255 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2528781255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_slow_rsp.1035377020 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 41453354196 ps |
| CPU time | 57.61 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:18:08 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035377020 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1035377020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_random_zero_delays.959389317 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 34417227 ps |
| CPU time | 4.69 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:17:14 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959389317 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_delays.959389317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_same_source.813679529 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 141543118 ps |
| CPU time | 6.62 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:17:16 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813679529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.813679529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke.495125193 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 13621194 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 09:17:05 PM UTC 24 |
| Finished | Oct 14 09:17:08 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495125193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.495125193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_large_delays.1452338070 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3059366389 ps |
| CPU time | 12.16 seconds |
| Started | Oct 14 09:17:06 PM UTC 24 |
| Finished | Oct 14 09:17:19 PM UTC 24 |
| Peak memory | 213096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452338070 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1452338070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_slow_rsp.1239525280 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1673948695 ps |
| CPU time | 8 seconds |
| Started | Oct 14 09:17:08 PM UTC 24 |
| Finished | Oct 14 09:17:17 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239525280 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1239525280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_smoke_zero_delays.2600118775 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 10246090 ps |
| CPU time | 1.41 seconds |
| Started | Oct 14 09:17:05 PM UTC 24 |
| Finished | Oct 14 09:17:07 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600118775 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays.2600118775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all.1138894896 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 99593518 ps |
| CPU time | 7.05 seconds |
| Started | Oct 14 09:17:13 PM UTC 24 |
| Finished | Oct 14 09:17:21 PM UTC 24 |
| Peak memory | 212888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138894896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1138894896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_error.4254436664 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 573147060 ps |
| CPU time | 26.08 seconds |
| Started | Oct 14 09:17:13 PM UTC 24 |
| Finished | Oct 14 09:17:40 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254436664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.4254436664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_rand_reset.116612111 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1166822986 ps |
| CPU time | 137.3 seconds |
| Started | Oct 14 09:17:13 PM UTC 24 |
| Finished | Oct 14 09:19:33 PM UTC 24 |
| Peak memory | 217032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116612111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_rand_reset.116612111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_stress_all_with_reset_error.2477351648 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 624162347 ps |
| CPU time | 82.19 seconds |
| Started | Oct 14 09:17:13 PM UTC 24 |
| Finished | Oct 14 09:18:37 PM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477351648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_reset_error.2477351648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/29.xbar_unmapped_addr.1447050527 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 517046224 ps |
| CPU time | 10.36 seconds |
| Started | Oct 14 09:17:13 PM UTC 24 |
| Finished | Oct 14 09:17:24 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447050527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1447050527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/29.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device.2316657253 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 18356157 ps |
| CPU time | 4.49 seconds |
| Started | Oct 14 09:12:41 PM UTC 24 |
| Finished | Oct 14 09:12:47 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316657253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.2316657253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_access_same_device_slow_rsp.2104624528 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5344123714 ps |
| CPU time | 31.8 seconds |
| Started | Oct 14 09:12:41 PM UTC 24 |
| Finished | Oct 14 09:13:14 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104624528 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device_slow_rsp.2104624528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_and_unmapped_addr.1530774101 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1051375821 ps |
| CPU time | 6.91 seconds |
| Started | Oct 14 09:12:46 PM UTC 24 |
| Finished | Oct 14 09:12:54 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530774101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr.1530774101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_error_random.387250202 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 14481203 ps |
| CPU time | 1.52 seconds |
| Started | Oct 14 09:12:43 PM UTC 24 |
| Finished | Oct 14 09:12:45 PM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387250202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.387250202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_large_delays.589734712 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3253705336 ps |
| CPU time | 9.93 seconds |
| Started | Oct 14 09:12:41 PM UTC 24 |
| Finished | Oct 14 09:12:52 PM UTC 24 |
| Peak memory | 212792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589734712 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.589734712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_slow_rsp.2083240009 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 10751168443 ps |
| CPU time | 80.23 seconds |
| Started | Oct 14 09:12:41 PM UTC 24 |
| Finished | Oct 14 09:14:03 PM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083240009 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.2083240009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_random_zero_delays.1740172690 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 194406055 ps |
| CPU time | 8.02 seconds |
| Started | Oct 14 09:12:38 PM UTC 24 |
| Finished | Oct 14 09:12:47 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740172690 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delays.1740172690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_same_source.76616285 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2752646035 ps |
| CPU time | 12.37 seconds |
| Started | Oct 14 09:12:43 PM UTC 24 |
| Finished | Oct 14 09:12:56 PM UTC 24 |
| Peak memory | 213056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76616285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.76616285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke.3669848853 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 8362041 ps |
| CPU time | 1.47 seconds |
| Started | Oct 14 09:12:37 PM UTC 24 |
| Finished | Oct 14 09:12:39 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669848853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3669848853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_large_delays.884864457 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1943219597 ps |
| CPU time | 8.76 seconds |
| Started | Oct 14 09:12:37 PM UTC 24 |
| Finished | Oct 14 09:12:47 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884864457 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.884864457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_slow_rsp.1460556930 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 4073429748 ps |
| CPU time | 8.6 seconds |
| Started | Oct 14 09:12:37 PM UTC 24 |
| Finished | Oct 14 09:12:47 PM UTC 24 |
| Peak memory | 213068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460556930 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1460556930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_smoke_zero_delays.4021981895 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11008265 ps |
| CPU time | 1.63 seconds |
| Started | Oct 14 09:12:37 PM UTC 24 |
| Finished | Oct 14 09:12:40 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021981895 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays.4021981895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all.484520393 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 852673564 ps |
| CPU time | 55.99 seconds |
| Started | Oct 14 09:12:46 PM UTC 24 |
| Finished | Oct 14 09:13:44 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484520393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.484520393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_stress_all_with_rand_reset.4105532942 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 44110891 ps |
| CPU time | 8.23 seconds |
| Started | Oct 14 09:12:46 PM UTC 24 |
| Finished | Oct 14 09:12:56 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105532942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_rand_reset.4105532942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/3.xbar_unmapped_addr.416419244 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 837524922 ps |
| CPU time | 11.76 seconds |
| Started | Oct 14 09:12:46 PM UTC 24 |
| Finished | Oct 14 09:12:59 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416419244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.416419244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/3.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device.2189003574 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 198877319 ps |
| CPU time | 1.91 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:20 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189003574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device.2189003574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_access_same_device_slow_rsp.2783575955 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 8054882034 ps |
| CPU time | 45.95 seconds |
| Started | Oct 14 09:17:19 PM UTC 24 |
| Finished | Oct 14 09:18:07 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783575955 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device_slow_rsp.2783575955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_and_unmapped_addr.2923891066 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 16562020 ps |
| CPU time | 2.22 seconds |
| Started | Oct 14 09:17:20 PM UTC 24 |
| Finished | Oct 14 09:17:23 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923891066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr.2923891066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_error_random.3976993261 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 64054228 ps |
| CPU time | 1.92 seconds |
| Started | Oct 14 09:17:20 PM UTC 24 |
| Finished | Oct 14 09:17:23 PM UTC 24 |
| Peak memory | 209848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976993261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3976993261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random.3313511351 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 25995798 ps |
| CPU time | 2.58 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:20 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313511351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random.3313511351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_large_delays.2663579711 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 6286493206 ps |
| CPU time | 22.92 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:41 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663579711 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2663579711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_slow_rsp.1367682834 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2904597735 ps |
| CPU time | 20.71 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:39 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367682834 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1367682834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_random_zero_delays.1203131667 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 36149049 ps |
| CPU time | 4.04 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:22 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203131667 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_delays.1203131667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_same_source.3033402390 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 140927119 ps |
| CPU time | 3.78 seconds |
| Started | Oct 14 09:17:20 PM UTC 24 |
| Finished | Oct 14 09:17:24 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033402390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3033402390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke.3448877998 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 123482989 ps |
| CPU time | 2.03 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:20 PM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448877998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.3448877998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_large_delays.1318890109 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2126176494 ps |
| CPU time | 8.74 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:26 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318890109 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1318890109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_slow_rsp.2040455323 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 597873585 ps |
| CPU time | 6.4 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:24 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040455323 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.2040455323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_smoke_zero_delays.4291931041 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 15687754 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 09:17:17 PM UTC 24 |
| Finished | Oct 14 09:17:19 PM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291931041 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delays.4291931041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all.1792865591 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 237034793 ps |
| CPU time | 26.21 seconds |
| Started | Oct 14 09:17:24 PM UTC 24 |
| Finished | Oct 14 09:17:52 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792865591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1792865591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_error.2038822391 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 439518544 ps |
| CPU time | 42.23 seconds |
| Started | Oct 14 09:17:24 PM UTC 24 |
| Finished | Oct 14 09:18:08 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038822391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2038822391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_rand_reset.4237590852 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 3118686769 ps |
| CPU time | 95.19 seconds |
| Started | Oct 14 09:17:24 PM UTC 24 |
| Finished | Oct 14 09:19:02 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237590852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_rand_reset.4237590852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_stress_all_with_reset_error.2665317534 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 867911814 ps |
| CPU time | 95.56 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:19:02 PM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665317534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_reset_error.2665317534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/30.xbar_unmapped_addr.2432851420 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 702398395 ps |
| CPU time | 7.39 seconds |
| Started | Oct 14 09:17:20 PM UTC 24 |
| Finished | Oct 14 09:17:28 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432851420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2432851420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/30.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device.1450886168 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 51697174 ps |
| CPU time | 5.92 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:17:32 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450886168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device.1450886168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_access_same_device_slow_rsp.2807679063 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 13266589078 ps |
| CPU time | 79.63 seconds |
| Started | Oct 14 09:17:27 PM UTC 24 |
| Finished | Oct 14 09:18:49 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807679063 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device_slow_rsp.2807679063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_and_unmapped_addr.1129481230 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 77576461 ps |
| CPU time | 8.22 seconds |
| Started | Oct 14 09:17:27 PM UTC 24 |
| Finished | Oct 14 09:17:37 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129481230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_addr.1129481230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_error_random.1123686902 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 431233721 ps |
| CPU time | 7.44 seconds |
| Started | Oct 14 09:17:27 PM UTC 24 |
| Finished | Oct 14 09:17:36 PM UTC 24 |
| Peak memory | 210868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123686902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1123686902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random.1655617157 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1748401819 ps |
| CPU time | 12.59 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:17:39 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655617157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random.1655617157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_large_delays.1200819765 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 15068472881 ps |
| CPU time | 33.46 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:18:00 PM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200819765 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1200819765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_slow_rsp.2032104679 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 22811710023 ps |
| CPU time | 55.6 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:18:22 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032104679 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2032104679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_random_zero_delays.3025924724 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 67843952 ps |
| CPU time | 7.47 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:17:33 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025924724 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_delays.3025924724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_same_source.2642982791 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 237758867 ps |
| CPU time | 5.13 seconds |
| Started | Oct 14 09:17:27 PM UTC 24 |
| Finished | Oct 14 09:17:33 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642982791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2642982791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke.1852879733 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 8384270 ps |
| CPU time | 1.71 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:17:27 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852879733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1852879733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_large_delays.2493385796 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 7875413035 ps |
| CPU time | 8.87 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:17:35 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493385796 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2493385796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_slow_rsp.941881940 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 796265082 ps |
| CPU time | 8.17 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:17:34 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941881940 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.941881940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_smoke_zero_delays.3810509155 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 9007285 ps |
| CPU time | 1.26 seconds |
| Started | Oct 14 09:17:25 PM UTC 24 |
| Finished | Oct 14 09:17:27 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810509155 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays.3810509155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all.3073642861 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 19780237370 ps |
| CPU time | 109.99 seconds |
| Started | Oct 14 09:17:27 PM UTC 24 |
| Finished | Oct 14 09:19:19 PM UTC 24 |
| Peak memory | 212988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073642861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.3073642861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_error.4137262504 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 5424335666 ps |
| CPU time | 52.34 seconds |
| Started | Oct 14 09:17:29 PM UTC 24 |
| Finished | Oct 14 09:18:23 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137262504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4137262504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_rand_reset.1958406808 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 6341981765 ps |
| CPU time | 163.23 seconds |
| Started | Oct 14 09:17:29 PM UTC 24 |
| Finished | Oct 14 09:20:15 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958406808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_rand_reset.1958406808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_stress_all_with_reset_error.611544401 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 106708408 ps |
| CPU time | 9.14 seconds |
| Started | Oct 14 09:17:30 PM UTC 24 |
| Finished | Oct 14 09:17:40 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611544401 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_reset_error.611544401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/31.xbar_unmapped_addr.3454007506 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 141197513 ps |
| CPU time | 7.3 seconds |
| Started | Oct 14 09:17:27 PM UTC 24 |
| Finished | Oct 14 09:17:36 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454007506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3454007506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/31.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device.3412665355 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 51965771 ps |
| CPU time | 8.58 seconds |
| Started | Oct 14 09:17:37 PM UTC 24 |
| Finished | Oct 14 09:17:47 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412665355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device.3412665355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_access_same_device_slow_rsp.1977723572 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 35918152710 ps |
| CPU time | 39.03 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:18:21 PM UTC 24 |
| Peak memory | 211036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977723572 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device_slow_rsp.1977723572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_and_unmapped_addr.1068463754 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 61391400 ps |
| CPU time | 2.78 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:17:45 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068463754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr.1068463754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_error_random.26934786 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 369396199 ps |
| CPU time | 4.56 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:17:46 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26934786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.26934786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random.3201483996 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 265984564 ps |
| CPU time | 4.61 seconds |
| Started | Oct 14 09:17:37 PM UTC 24 |
| Finished | Oct 14 09:17:42 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201483996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random.3201483996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_large_delays.1130292489 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 7769247516 ps |
| CPU time | 26.51 seconds |
| Started | Oct 14 09:17:37 PM UTC 24 |
| Finished | Oct 14 09:18:05 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130292489 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1130292489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_slow_rsp.1131293814 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 14810790062 ps |
| CPU time | 64.5 seconds |
| Started | Oct 14 09:17:37 PM UTC 24 |
| Finished | Oct 14 09:18:43 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131293814 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1131293814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_random_zero_delays.2671003446 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 387822580 ps |
| CPU time | 6.6 seconds |
| Started | Oct 14 09:17:37 PM UTC 24 |
| Finished | Oct 14 09:17:44 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671003446 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_delays.2671003446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_same_source.855168749 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 37059388 ps |
| CPU time | 5.29 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:17:47 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855168749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.855168749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke.3337902496 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 40364508 ps |
| CPU time | 1.34 seconds |
| Started | Oct 14 09:17:32 PM UTC 24 |
| Finished | Oct 14 09:17:34 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337902496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3337902496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_large_delays.780060341 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2379606507 ps |
| CPU time | 10.73 seconds |
| Started | Oct 14 09:17:36 PM UTC 24 |
| Finished | Oct 14 09:17:48 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780060341 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.780060341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_slow_rsp.2339589833 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1264006341 ps |
| CPU time | 7.76 seconds |
| Started | Oct 14 09:17:36 PM UTC 24 |
| Finished | Oct 14 09:17:45 PM UTC 24 |
| Peak memory | 212924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339589833 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2339589833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_smoke_zero_delays.2262485801 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 14698473 ps |
| CPU time | 1.72 seconds |
| Started | Oct 14 09:17:33 PM UTC 24 |
| Finished | Oct 14 09:17:36 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262485801 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays.2262485801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all.2754815437 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 8076680028 ps |
| CPU time | 22.62 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:18:05 PM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754815437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2754815437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_error.1098595346 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 661841442 ps |
| CPU time | 12.44 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:17:55 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098595346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1098595346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_rand_reset.2128743581 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 409544999 ps |
| CPU time | 68.6 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:18:51 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128743581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_rand_reset.2128743581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_stress_all_with_reset_error.4115333848 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1254191411 ps |
| CPU time | 142.62 seconds |
| Started | Oct 14 09:17:41 PM UTC 24 |
| Finished | Oct 14 09:20:06 PM UTC 24 |
| Peak memory | 217076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115333848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_reset_error.4115333848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/32.xbar_unmapped_addr.1658814854 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 352669989 ps |
| CPU time | 11.13 seconds |
| Started | Oct 14 09:17:40 PM UTC 24 |
| Finished | Oct 14 09:17:53 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658814854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1658814854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/32.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_access_same_device_slow_rsp.4156595788 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 9021633926 ps |
| CPU time | 65.9 seconds |
| Started | Oct 14 09:17:46 PM UTC 24 |
| Finished | Oct 14 09:18:54 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156595788 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device_slow_rsp.4156595788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_and_unmapped_addr.3885653406 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2121396475 ps |
| CPU time | 13.13 seconds |
| Started | Oct 14 09:17:48 PM UTC 24 |
| Finished | Oct 14 09:18:03 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885653406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr.3885653406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_error_random.3785899120 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 21805727 ps |
| CPU time | 3.16 seconds |
| Started | Oct 14 09:17:47 PM UTC 24 |
| Finished | Oct 14 09:17:51 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785899120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3785899120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random.2802088722 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 106300711 ps |
| CPU time | 8.1 seconds |
| Started | Oct 14 09:17:42 PM UTC 24 |
| Finished | Oct 14 09:17:52 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802088722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random.2802088722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_large_delays.1658618272 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 16220038674 ps |
| CPU time | 60.67 seconds |
| Started | Oct 14 09:17:44 PM UTC 24 |
| Finished | Oct 14 09:18:47 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658618272 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1658618272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_slow_rsp.107460156 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 37043047842 ps |
| CPU time | 84.08 seconds |
| Started | Oct 14 09:17:44 PM UTC 24 |
| Finished | Oct 14 09:19:10 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107460156 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.107460156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_random_zero_delays.1180817282 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 15465915 ps |
| CPU time | 1.87 seconds |
| Started | Oct 14 09:17:43 PM UTC 24 |
| Finished | Oct 14 09:17:46 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180817282 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_delays.1180817282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_same_source.3134390555 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 880638767 ps |
| CPU time | 13.2 seconds |
| Started | Oct 14 09:17:47 PM UTC 24 |
| Finished | Oct 14 09:18:01 PM UTC 24 |
| Peak memory | 212920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134390555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3134390555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke.3000151008 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 52255259 ps |
| CPU time | 2.34 seconds |
| Started | Oct 14 09:17:41 PM UTC 24 |
| Finished | Oct 14 09:17:44 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000151008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3000151008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_large_delays.4217094882 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7502606114 ps |
| CPU time | 9.51 seconds |
| Started | Oct 14 09:17:42 PM UTC 24 |
| Finished | Oct 14 09:17:53 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217094882 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.4217094882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_slow_rsp.3809086331 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1275117784 ps |
| CPU time | 12.72 seconds |
| Started | Oct 14 09:17:42 PM UTC 24 |
| Finished | Oct 14 09:17:56 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809086331 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3809086331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_smoke_zero_delays.2892773746 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 9874334 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 09:17:41 PM UTC 24 |
| Finished | Oct 14 09:17:44 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892773746 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays.2892773746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all.3236396784 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 6192499 ps |
| CPU time | 1.14 seconds |
| Started | Oct 14 09:17:49 PM UTC 24 |
| Finished | Oct 14 09:17:51 PM UTC 24 |
| Peak memory | 201944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236396784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3236396784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_error.1449384272 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 469976411 ps |
| CPU time | 34.34 seconds |
| Started | Oct 14 09:17:49 PM UTC 24 |
| Finished | Oct 14 09:18:25 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449384272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.1449384272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_rand_reset.2556612249 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4088195600 ps |
| CPU time | 89.85 seconds |
| Started | Oct 14 09:17:49 PM UTC 24 |
| Finished | Oct 14 09:19:20 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556612249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_rand_reset.2556612249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_stress_all_with_reset_error.1579015297 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 922239953 ps |
| CPU time | 51.95 seconds |
| Started | Oct 14 09:17:50 PM UTC 24 |
| Finished | Oct 14 09:18:44 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579015297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_reset_error.1579015297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/33.xbar_unmapped_addr.329456163 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 46135047 ps |
| CPU time | 4.24 seconds |
| Started | Oct 14 09:17:47 PM UTC 24 |
| Finished | Oct 14 09:17:52 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329456163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.329456163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/33.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_access_same_device.3184312724 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 42426217 ps |
| CPU time | 6.66 seconds |
| Started | Oct 14 09:17:58 PM UTC 24 |
| Finished | Oct 14 09:18:06 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184312724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device.3184312724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_and_unmapped_addr.702488541 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 494028882 ps |
| CPU time | 9.24 seconds |
| Started | Oct 14 09:17:58 PM UTC 24 |
| Finished | Oct 14 09:18:09 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702488541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr.702488541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_error_random.2507487554 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 43399415 ps |
| CPU time | 3.18 seconds |
| Started | Oct 14 09:17:58 PM UTC 24 |
| Finished | Oct 14 09:18:02 PM UTC 24 |
| Peak memory | 213060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507487554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2507487554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random.3603906176 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 51344645 ps |
| CPU time | 2.31 seconds |
| Started | Oct 14 09:17:57 PM UTC 24 |
| Finished | Oct 14 09:18:01 PM UTC 24 |
| Peak memory | 210888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603906176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random.3603906176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_large_delays.3693809732 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 32166853332 ps |
| CPU time | 64.03 seconds |
| Started | Oct 14 09:17:57 PM UTC 24 |
| Finished | Oct 14 09:19:03 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693809732 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3693809732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_slow_rsp.2001754384 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 5652322909 ps |
| CPU time | 37.46 seconds |
| Started | Oct 14 09:17:57 PM UTC 24 |
| Finished | Oct 14 09:18:37 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001754384 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2001754384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_random_zero_delays.648433876 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 45170411 ps |
| CPU time | 2.41 seconds |
| Started | Oct 14 09:17:57 PM UTC 24 |
| Finished | Oct 14 09:18:01 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648433876 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_delays.648433876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_same_source.3598356257 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3982122923 ps |
| CPU time | 12.16 seconds |
| Started | Oct 14 09:17:58 PM UTC 24 |
| Finished | Oct 14 09:18:11 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598356257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.3598356257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke.2687547158 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 9012969 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 09:17:52 PM UTC 24 |
| Finished | Oct 14 09:17:55 PM UTC 24 |
| Peak memory | 209792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687547158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2687547158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_large_delays.3815324684 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2106334666 ps |
| CPU time | 8.42 seconds |
| Started | Oct 14 09:17:52 PM UTC 24 |
| Finished | Oct 14 09:18:02 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815324684 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3815324684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_slow_rsp.2572747033 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1932496358 ps |
| CPU time | 15.36 seconds |
| Started | Oct 14 09:17:57 PM UTC 24 |
| Finished | Oct 14 09:18:14 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572747033 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2572747033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_smoke_zero_delays.183083387 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 11205547 ps |
| CPU time | 1.57 seconds |
| Started | Oct 14 09:17:52 PM UTC 24 |
| Finished | Oct 14 09:17:55 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183083387 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays.183083387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all.989727229 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 438030230 ps |
| CPU time | 19.24 seconds |
| Started | Oct 14 09:17:59 PM UTC 24 |
| Finished | Oct 14 09:18:20 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989727229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.989727229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_error.1794788453 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 6818555952 ps |
| CPU time | 50.55 seconds |
| Started | Oct 14 09:18:01 PM UTC 24 |
| Finished | Oct 14 09:18:53 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794788453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1794788453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_rand_reset.1499967719 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 44908634 ps |
| CPU time | 7.97 seconds |
| Started | Oct 14 09:17:59 PM UTC 24 |
| Finished | Oct 14 09:18:09 PM UTC 24 |
| Peak memory | 212948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499967719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_rand_reset.1499967719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_stress_all_with_reset_error.2527165627 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 630564374 ps |
| CPU time | 35.93 seconds |
| Started | Oct 14 09:18:03 PM UTC 24 |
| Finished | Oct 14 09:18:41 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527165627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_reset_error.2527165627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/34.xbar_unmapped_addr.2286920634 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 649204060 ps |
| CPU time | 12.08 seconds |
| Started | Oct 14 09:17:58 PM UTC 24 |
| Finished | Oct 14 09:18:11 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286920634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2286920634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/34.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device.3721065257 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 177048831 ps |
| CPU time | 13.52 seconds |
| Started | Oct 14 09:18:07 PM UTC 24 |
| Finished | Oct 14 09:18:22 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721065257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device.3721065257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_access_same_device_slow_rsp.1521929430 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 16534357078 ps |
| CPU time | 140.57 seconds |
| Started | Oct 14 09:18:07 PM UTC 24 |
| Finished | Oct 14 09:20:30 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521929430 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device_slow_rsp.1521929430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_and_unmapped_addr.4181507721 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 698933054 ps |
| CPU time | 9.6 seconds |
| Started | Oct 14 09:18:10 PM UTC 24 |
| Finished | Oct 14 09:18:20 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181507721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr.4181507721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_error_random.300034147 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 719389220 ps |
| CPU time | 4.75 seconds |
| Started | Oct 14 09:18:08 PM UTC 24 |
| Finished | Oct 14 09:18:13 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300034147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.300034147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random.4232381530 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 917981593 ps |
| CPU time | 11.53 seconds |
| Started | Oct 14 09:18:03 PM UTC 24 |
| Finished | Oct 14 09:18:16 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232381530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random.4232381530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_large_delays.539733050 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 42750082923 ps |
| CPU time | 33.12 seconds |
| Started | Oct 14 09:18:05 PM UTC 24 |
| Finished | Oct 14 09:18:39 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539733050 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.539733050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_slow_rsp.3166643589 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3265319770 ps |
| CPU time | 33.22 seconds |
| Started | Oct 14 09:18:07 PM UTC 24 |
| Finished | Oct 14 09:18:42 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166643589 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3166643589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_random_zero_delays.2331876897 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 71889516 ps |
| CPU time | 9.93 seconds |
| Started | Oct 14 09:18:03 PM UTC 24 |
| Finished | Oct 14 09:18:15 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331876897 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_delays.2331876897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_same_source.156083502 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1667624695 ps |
| CPU time | 10.87 seconds |
| Started | Oct 14 09:18:07 PM UTC 24 |
| Finished | Oct 14 09:18:20 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156083502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.156083502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke.2371525908 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 10446336 ps |
| CPU time | 1.18 seconds |
| Started | Oct 14 09:18:03 PM UTC 24 |
| Finished | Oct 14 09:18:05 PM UTC 24 |
| Peak memory | 211952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371525908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2371525908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_large_delays.288931989 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 1747911292 ps |
| CPU time | 12.7 seconds |
| Started | Oct 14 09:18:03 PM UTC 24 |
| Finished | Oct 14 09:18:17 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288931989 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.288931989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_slow_rsp.2057264334 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 5296312930 ps |
| CPU time | 9.98 seconds |
| Started | Oct 14 09:18:03 PM UTC 24 |
| Finished | Oct 14 09:18:14 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057264334 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2057264334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_smoke_zero_delays.1462486552 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 9339054 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 09:18:03 PM UTC 24 |
| Finished | Oct 14 09:18:06 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462486552 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays.1462486552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all.31155388 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 440569112 ps |
| CPU time | 9.69 seconds |
| Started | Oct 14 09:18:10 PM UTC 24 |
| Finished | Oct 14 09:18:20 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31155388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-si m-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.31155388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_error.1784258278 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2165244974 ps |
| CPU time | 28.01 seconds |
| Started | Oct 14 09:18:10 PM UTC 24 |
| Finished | Oct 14 09:18:39 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784258278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1784258278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_rand_reset.1352524279 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 5503985146 ps |
| CPU time | 44.12 seconds |
| Started | Oct 14 09:18:10 PM UTC 24 |
| Finished | Oct 14 09:18:55 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352524279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_rand_reset.1352524279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_stress_all_with_reset_error.1920219687 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1038851691 ps |
| CPU time | 133.24 seconds |
| Started | Oct 14 09:18:13 PM UTC 24 |
| Finished | Oct 14 09:20:28 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920219687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_reset_error.1920219687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/35.xbar_unmapped_addr.1378817538 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 849413684 ps |
| CPU time | 11.45 seconds |
| Started | Oct 14 09:18:09 PM UTC 24 |
| Finished | Oct 14 09:18:22 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378817538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1378817538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/35.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device.1644602192 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 602776955 ps |
| CPU time | 8.34 seconds |
| Started | Oct 14 09:18:19 PM UTC 24 |
| Finished | Oct 14 09:18:28 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644602192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device.1644602192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_access_same_device_slow_rsp.2249274090 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 22198957589 ps |
| CPU time | 102.24 seconds |
| Started | Oct 14 09:18:22 PM UTC 24 |
| Finished | Oct 14 09:20:06 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249274090 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device_slow_rsp.2249274090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_and_unmapped_addr.2074010374 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 56834260 ps |
| CPU time | 4.58 seconds |
| Started | Oct 14 09:18:22 PM UTC 24 |
| Finished | Oct 14 09:18:27 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074010374 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.2074010374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_error_random.1710765424 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 147408913 ps |
| CPU time | 5.89 seconds |
| Started | Oct 14 09:18:22 PM UTC 24 |
| Finished | Oct 14 09:18:29 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710765424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1710765424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random.23122665 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 846997844 ps |
| CPU time | 12.21 seconds |
| Started | Oct 14 09:18:17 PM UTC 24 |
| Finished | Oct 14 09:18:30 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23122665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random.23122665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_large_delays.2747427020 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 43200036751 ps |
| CPU time | 52.78 seconds |
| Started | Oct 14 09:18:19 PM UTC 24 |
| Finished | Oct 14 09:19:13 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747427020 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2747427020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_slow_rsp.1885091685 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 12946466272 ps |
| CPU time | 54.84 seconds |
| Started | Oct 14 09:18:19 PM UTC 24 |
| Finished | Oct 14 09:19:15 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885091685 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1885091685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_random_zero_delays.2384996596 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 72592496 ps |
| CPU time | 8.56 seconds |
| Started | Oct 14 09:18:17 PM UTC 24 |
| Finished | Oct 14 09:18:26 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384996596 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_delays.2384996596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_same_source.3889721824 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 901760063 ps |
| CPU time | 10.89 seconds |
| Started | Oct 14 09:18:22 PM UTC 24 |
| Finished | Oct 14 09:18:34 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889721824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3889721824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke.3738917530 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 184642389 ps |
| CPU time | 2.23 seconds |
| Started | Oct 14 09:18:13 PM UTC 24 |
| Finished | Oct 14 09:18:16 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738917530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3738917530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_large_delays.3849488688 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2362084468 ps |
| CPU time | 10.52 seconds |
| Started | Oct 14 09:18:17 PM UTC 24 |
| Finished | Oct 14 09:18:28 PM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849488688 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3849488688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_slow_rsp.3610055612 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1811865388 ps |
| CPU time | 12.06 seconds |
| Started | Oct 14 09:18:17 PM UTC 24 |
| Finished | Oct 14 09:18:30 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610055612 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3610055612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_smoke_zero_delays.1826602382 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 11106370 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 09:18:14 PM UTC 24 |
| Finished | Oct 14 09:18:17 PM UTC 24 |
| Peak memory | 211960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826602382 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays.1826602382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all.3583589352 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 243380974 ps |
| CPU time | 15.88 seconds |
| Started | Oct 14 09:18:24 PM UTC 24 |
| Finished | Oct 14 09:18:41 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583589352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3583589352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_error.3937723967 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1258937687 ps |
| CPU time | 19.37 seconds |
| Started | Oct 14 09:18:24 PM UTC 24 |
| Finished | Oct 14 09:18:45 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937723967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.3937723967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_stress_all_with_reset_error.255501272 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1428240640 ps |
| CPU time | 100.37 seconds |
| Started | Oct 14 09:18:24 PM UTC 24 |
| Finished | Oct 14 09:20:06 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255501272 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_reset_error.255501272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/36.xbar_unmapped_addr.2261170324 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 33273921 ps |
| CPU time | 2.68 seconds |
| Started | Oct 14 09:18:22 PM UTC 24 |
| Finished | Oct 14 09:18:25 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261170324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2261170324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/36.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device.430299057 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 966478176 ps |
| CPU time | 15.63 seconds |
| Started | Oct 14 09:18:29 PM UTC 24 |
| Finished | Oct 14 09:18:46 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430299057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device.430299057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_access_same_device_slow_rsp.3763183628 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 18434941294 ps |
| CPU time | 122.33 seconds |
| Started | Oct 14 09:18:29 PM UTC 24 |
| Finished | Oct 14 09:20:34 PM UTC 24 |
| Peak memory | 218636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763183628 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device_slow_rsp.3763183628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_and_unmapped_addr.2204796161 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 42080049 ps |
| CPU time | 2.05 seconds |
| Started | Oct 14 09:18:33 PM UTC 24 |
| Finished | Oct 14 09:18:36 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204796161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.2204796161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_error_random.2430966123 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 24796996 ps |
| CPU time | 3.54 seconds |
| Started | Oct 14 09:18:32 PM UTC 24 |
| Finished | Oct 14 09:18:37 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430966123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2430966123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random.1522175087 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 17068332 ps |
| CPU time | 1.53 seconds |
| Started | Oct 14 09:18:29 PM UTC 24 |
| Finished | Oct 14 09:18:31 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522175087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random.1522175087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_large_delays.190684094 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 16068095019 ps |
| CPU time | 79.7 seconds |
| Started | Oct 14 09:18:29 PM UTC 24 |
| Finished | Oct 14 09:19:50 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190684094 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.190684094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_slow_rsp.3356635888 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 21470653210 ps |
| CPU time | 54.59 seconds |
| Started | Oct 14 09:18:29 PM UTC 24 |
| Finished | Oct 14 09:19:25 PM UTC 24 |
| Peak memory | 211032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356635888 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3356635888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_random_zero_delays.4041671528 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 130100501 ps |
| CPU time | 6.96 seconds |
| Started | Oct 14 09:18:29 PM UTC 24 |
| Finished | Oct 14 09:18:37 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041671528 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_delays.4041671528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_same_source.1981150941 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 589357325 ps |
| CPU time | 6.96 seconds |
| Started | Oct 14 09:18:32 PM UTC 24 |
| Finished | Oct 14 09:18:41 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981150941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1981150941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke.994598241 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 266938234 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 09:18:24 PM UTC 24 |
| Finished | Oct 14 09:18:27 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994598241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.994598241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_large_delays.2596781172 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 12927189909 ps |
| CPU time | 12.25 seconds |
| Started | Oct 14 09:18:26 PM UTC 24 |
| Finished | Oct 14 09:18:39 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596781172 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2596781172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_slow_rsp.2655616755 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2366106475 ps |
| CPU time | 13.4 seconds |
| Started | Oct 14 09:18:26 PM UTC 24 |
| Finished | Oct 14 09:18:41 PM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655616755 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2655616755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_smoke_zero_delays.1527879799 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 12748974 ps |
| CPU time | 1.64 seconds |
| Started | Oct 14 09:18:26 PM UTC 24 |
| Finished | Oct 14 09:18:29 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527879799 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays.1527879799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all.248489366 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 17802057 ps |
| CPU time | 1.79 seconds |
| Started | Oct 14 09:18:33 PM UTC 24 |
| Finished | Oct 14 09:18:36 PM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248489366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.248489366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_error.1265034647 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 362675429 ps |
| CPU time | 31.38 seconds |
| Started | Oct 14 09:18:33 PM UTC 24 |
| Finished | Oct 14 09:19:06 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265034647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1265034647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_rand_reset.2533061114 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3153590728 ps |
| CPU time | 71 seconds |
| Started | Oct 14 09:18:33 PM UTC 24 |
| Finished | Oct 14 09:19:45 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533061114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_rand_reset.2533061114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_stress_all_with_reset_error.2070835961 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 77057679 ps |
| CPU time | 11.17 seconds |
| Started | Oct 14 09:18:33 PM UTC 24 |
| Finished | Oct 14 09:18:45 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070835961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_reset_error.2070835961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/37.xbar_unmapped_addr.3887271883 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 412812079 ps |
| CPU time | 4.41 seconds |
| Started | Oct 14 09:18:33 PM UTC 24 |
| Finished | Oct 14 09:18:38 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887271883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3887271883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/37.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device.2232194561 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 184649221 ps |
| CPU time | 3.56 seconds |
| Started | Oct 14 09:18:40 PM UTC 24 |
| Finished | Oct 14 09:18:45 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232194561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device.2232194561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_access_same_device_slow_rsp.574608881 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 23114498151 ps |
| CPU time | 115.1 seconds |
| Started | Oct 14 09:18:41 PM UTC 24 |
| Finished | Oct 14 09:20:38 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574608881 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device_slow_rsp.574608881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_and_unmapped_addr.3630776668 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 321082882 ps |
| CPU time | 4.45 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:18:51 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630776668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr.3630776668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_error_random.259627753 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 60684075 ps |
| CPU time | 3.83 seconds |
| Started | Oct 14 09:18:41 PM UTC 24 |
| Finished | Oct 14 09:18:46 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259627753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.259627753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random.2407012108 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 355843782 ps |
| CPU time | 3.38 seconds |
| Started | Oct 14 09:18:40 PM UTC 24 |
| Finished | Oct 14 09:18:45 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407012108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random.2407012108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_large_delays.2617699231 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 11298496274 ps |
| CPU time | 60.04 seconds |
| Started | Oct 14 09:18:40 PM UTC 24 |
| Finished | Oct 14 09:19:42 PM UTC 24 |
| Peak memory | 212984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617699231 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2617699231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_slow_rsp.1379846134 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 7650968663 ps |
| CPU time | 48.27 seconds |
| Started | Oct 14 09:18:40 PM UTC 24 |
| Finished | Oct 14 09:19:30 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379846134 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1379846134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_random_zero_delays.2823104432 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 80940930 ps |
| CPU time | 2.3 seconds |
| Started | Oct 14 09:18:40 PM UTC 24 |
| Finished | Oct 14 09:18:44 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823104432 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_delays.2823104432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_same_source.1395011480 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2061745045 ps |
| CPU time | 12.91 seconds |
| Started | Oct 14 09:18:41 PM UTC 24 |
| Finished | Oct 14 09:18:55 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395011480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1395011480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke.1659047860 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 15939314 ps |
| CPU time | 1.65 seconds |
| Started | Oct 14 09:18:35 PM UTC 24 |
| Finished | Oct 14 09:18:38 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659047860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1659047860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_large_delays.3111018451 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2840823212 ps |
| CPU time | 11.12 seconds |
| Started | Oct 14 09:18:35 PM UTC 24 |
| Finished | Oct 14 09:18:47 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111018451 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.3111018451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_slow_rsp.1137696887 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2002103387 ps |
| CPU time | 5.14 seconds |
| Started | Oct 14 09:18:36 PM UTC 24 |
| Finished | Oct 14 09:18:43 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137696887 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1137696887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_smoke_zero_delays.654092183 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 10136343 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 09:18:35 PM UTC 24 |
| Finished | Oct 14 09:18:38 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654092183 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delays.654092183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all.441304897 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 11325155892 ps |
| CPU time | 41.73 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:19:29 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441304897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.441304897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_error.3996600869 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 16355383852 ps |
| CPU time | 66.39 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:19:54 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996600869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3996600869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_rand_reset.790889424 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 398240217 ps |
| CPU time | 48.6 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:19:36 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790889424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_rand_reset.790889424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_stress_all_with_reset_error.373482644 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 1462158252 ps |
| CPU time | 68.31 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:19:56 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373482644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_reset_error.373482644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/38.xbar_unmapped_addr.2480613140 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 47496326 ps |
| CPU time | 2.39 seconds |
| Started | Oct 14 09:18:45 PM UTC 24 |
| Finished | Oct 14 09:18:48 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480613140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.2480613140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/38.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_access_same_device.2059634456 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 925642914 ps |
| CPU time | 9.72 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:19:01 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059634456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device.2059634456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_and_unmapped_addr.3133070957 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 136616770 ps |
| CPU time | 3.06 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:18:54 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133070957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr.3133070957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_error_random.2550917739 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 105814750 ps |
| CPU time | 2.44 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:18:54 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550917739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.2550917739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random.552820518 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 235329992 ps |
| CPU time | 10.28 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:19:01 PM UTC 24 |
| Peak memory | 212980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552820518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random.552820518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_large_delays.878913310 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 41518855845 ps |
| CPU time | 62.23 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:19:54 PM UTC 24 |
| Peak memory | 213156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878913310 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.878913310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_slow_rsp.1219908423 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 15234553873 ps |
| CPU time | 48.61 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:19:40 PM UTC 24 |
| Peak memory | 213068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219908423 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.1219908423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_random_zero_delays.115423224 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 55833190 ps |
| CPU time | 3.67 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:18:55 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115423224 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delays.115423224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_same_source.3840227683 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 56341661 ps |
| CPU time | 7.38 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:18:59 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840227683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3840227683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke.2521860761 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 64911796 ps |
| CPU time | 1.49 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:18:49 PM UTC 24 |
| Peak memory | 209700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521860761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2521860761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_large_delays.3488606614 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 9101436722 ps |
| CPU time | 9.61 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:18:57 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488606614 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3488606614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_slow_rsp.3668756326 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5780583718 ps |
| CPU time | 7.06 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:18:54 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668756326 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3668756326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_smoke_zero_delays.1752500986 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 16357580 ps |
| CPU time | 1.54 seconds |
| Started | Oct 14 09:18:46 PM UTC 24 |
| Finished | Oct 14 09:18:49 PM UTC 24 |
| Peak memory | 209720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752500986 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays.1752500986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all.3953947925 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 25468236812 ps |
| CPU time | 81.58 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:20:14 PM UTC 24 |
| Peak memory | 213092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953947925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3953947925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_error.1727846981 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1189126256 ps |
| CPU time | 17.44 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:19:09 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727846981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1727846981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_rand_reset.886550766 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 357023760 ps |
| CPU time | 29.72 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:19:21 PM UTC 24 |
| Peak memory | 212916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886550766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_rand_reset.886550766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_stress_all_with_reset_error.972987935 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3231966792 ps |
| CPU time | 65.65 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:19:58 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972987935 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_reset_error.972987935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/39.xbar_unmapped_addr.1305143854 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 142523029 ps |
| CPU time | 5.48 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:18:57 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305143854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1305143854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/39.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_access_same_device.1705521166 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 419173442 ps |
| CPU time | 5.66 seconds |
| Started | Oct 14 09:12:54 PM UTC 24 |
| Finished | Oct 14 09:13:01 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705521166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.1705521166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_and_unmapped_addr.3725126493 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 86487280 ps |
| CPU time | 6.66 seconds |
| Started | Oct 14 09:12:57 PM UTC 24 |
| Finished | Oct 14 09:13:04 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725126493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr.3725126493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_error_random.1199613746 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 1072589623 ps |
| CPU time | 13.39 seconds |
| Started | Oct 14 09:12:57 PM UTC 24 |
| Finished | Oct 14 09:13:11 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199613746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1199613746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random.4186185713 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 234651369 ps |
| CPU time | 4.18 seconds |
| Started | Oct 14 09:12:51 PM UTC 24 |
| Finished | Oct 14 09:12:56 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186185713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random.4186185713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_large_delays.315352071 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 16310001067 ps |
| CPU time | 74.86 seconds |
| Started | Oct 14 09:12:52 PM UTC 24 |
| Finished | Oct 14 09:14:09 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315352071 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.315352071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_slow_rsp.3336119104 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 33916023783 ps |
| CPU time | 82.91 seconds |
| Started | Oct 14 09:12:54 PM UTC 24 |
| Finished | Oct 14 09:14:19 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336119104 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3336119104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_random_zero_delays.288962859 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 73576876 ps |
| CPU time | 7.25 seconds |
| Started | Oct 14 09:12:51 PM UTC 24 |
| Finished | Oct 14 09:13:00 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288962859 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delays.288962859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_same_source.1787477592 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 111043090 ps |
| CPU time | 6.05 seconds |
| Started | Oct 14 09:12:55 PM UTC 24 |
| Finished | Oct 14 09:13:03 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787477592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1787477592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke.4161785799 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 9195196 ps |
| CPU time | 1.66 seconds |
| Started | Oct 14 09:12:48 PM UTC 24 |
| Finished | Oct 14 09:12:50 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161785799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4161785799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_large_delays.2316412223 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3331227900 ps |
| CPU time | 12.91 seconds |
| Started | Oct 14 09:12:48 PM UTC 24 |
| Finished | Oct 14 09:13:02 PM UTC 24 |
| Peak memory | 213020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316412223 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2316412223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_slow_rsp.2511763078 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 701939565 ps |
| CPU time | 5.27 seconds |
| Started | Oct 14 09:12:49 PM UTC 24 |
| Finished | Oct 14 09:12:55 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511763078 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2511763078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_smoke_zero_delays.2889972372 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10691880 ps |
| CPU time | 1.68 seconds |
| Started | Oct 14 09:12:48 PM UTC 24 |
| Finished | Oct 14 09:12:51 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889972372 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays.2889972372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all.1064110863 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 69074349 ps |
| CPU time | 6.27 seconds |
| Started | Oct 14 09:12:58 PM UTC 24 |
| Finished | Oct 14 09:13:06 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064110863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1064110863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_error.2762147617 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 663395674 ps |
| CPU time | 32.93 seconds |
| Started | Oct 14 09:13:00 PM UTC 24 |
| Finished | Oct 14 09:13:35 PM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762147617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2762147617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_rand_reset.1487378594 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 480930818 ps |
| CPU time | 72.94 seconds |
| Started | Oct 14 09:12:58 PM UTC 24 |
| Finished | Oct 14 09:14:13 PM UTC 24 |
| Peak memory | 215140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487378594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_rand_reset.1487378594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_stress_all_with_reset_error.531786358 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 100776087 ps |
| CPU time | 12.71 seconds |
| Started | Oct 14 09:13:00 PM UTC 24 |
| Finished | Oct 14 09:13:14 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531786358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_reset_error.531786358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/4.xbar_unmapped_addr.2560406769 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 120864416 ps |
| CPU time | 7.8 seconds |
| Started | Oct 14 09:12:57 PM UTC 24 |
| Finished | Oct 14 09:13:06 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560406769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2560406769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/4.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device.3229265054 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 128582841 ps |
| CPU time | 8.29 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:19:04 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229265054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device.3229265054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_access_same_device_slow_rsp.3387736955 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 6257553953 ps |
| CPU time | 27.8 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:19:24 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387736955 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device_slow_rsp.3387736955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_and_unmapped_addr.1094993465 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 178592238 ps |
| CPU time | 6.94 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:07 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094993465 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr.1094993465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_error_random.1727114682 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 946195424 ps |
| CPU time | 7.77 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:08 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727114682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1727114682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random.4213521813 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 556398882 ps |
| CPU time | 9.9 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:19:06 PM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213521813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random.4213521813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_large_delays.3962631419 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 24586038089 ps |
| CPU time | 65.91 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:20:02 PM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962631419 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3962631419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_slow_rsp.1521566620 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 8998414133 ps |
| CPU time | 46.56 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:19:43 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521566620 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1521566620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_random_zero_delays.721800431 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 13961547 ps |
| CPU time | 1.88 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:18:58 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721800431 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_delays.721800431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_same_source.2258525409 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1739200459 ps |
| CPU time | 13.7 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:19:10 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258525409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2258525409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke.2715622549 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 271403068 ps |
| CPU time | 2 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:18:54 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715622549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2715622549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_large_delays.4291532124 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2132747201 ps |
| CPU time | 6.4 seconds |
| Started | Oct 14 09:18:51 PM UTC 24 |
| Finished | Oct 14 09:18:58 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291532124 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.4291532124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_slow_rsp.863920070 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2986811808 ps |
| CPU time | 10.11 seconds |
| Started | Oct 14 09:18:55 PM UTC 24 |
| Finished | Oct 14 09:19:06 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863920070 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.863920070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_smoke_zero_delays.2498464927 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 18708570 ps |
| CPU time | 1.55 seconds |
| Started | Oct 14 09:18:50 PM UTC 24 |
| Finished | Oct 14 09:18:53 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498464927 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays.2498464927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all.3545496050 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 1803256730 ps |
| CPU time | 6.79 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:07 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545496050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3545496050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_error.3994859876 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 207110503 ps |
| CPU time | 20.95 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:21 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994859876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.3994859876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_rand_reset.3699913308 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 108605908 ps |
| CPU time | 24.22 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:25 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699913308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_rand_reset.3699913308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_stress_all_with_reset_error.2923131977 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2290221948 ps |
| CPU time | 46.6 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:47 PM UTC 24 |
| Peak memory | 213036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923131977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_reset_error.2923131977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/40.xbar_unmapped_addr.3229204923 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2680512168 ps |
| CPU time | 9.97 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:10 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229204923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3229204923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/40.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device.3424141420 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 75803137 ps |
| CPU time | 11.35 seconds |
| Started | Oct 14 09:19:06 PM UTC 24 |
| Finished | Oct 14 09:19:19 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424141420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device.3424141420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_access_same_device_slow_rsp.371463008 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 27567954420 ps |
| CPU time | 107.08 seconds |
| Started | Oct 14 09:19:06 PM UTC 24 |
| Finished | Oct 14 09:20:55 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371463008 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device_slow_rsp.371463008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_and_unmapped_addr.1247682438 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 768517614 ps |
| CPU time | 5.63 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:19:17 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247682438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_addr.1247682438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_error_random.1674370695 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 618459276 ps |
| CPU time | 8.78 seconds |
| Started | Oct 14 09:19:06 PM UTC 24 |
| Finished | Oct 14 09:19:16 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674370695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1674370695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random.3322938350 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 113833933 ps |
| CPU time | 3.25 seconds |
| Started | Oct 14 09:19:02 PM UTC 24 |
| Finished | Oct 14 09:19:06 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322938350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random.3322938350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_large_delays.1302409109 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 14572399690 ps |
| CPU time | 50.96 seconds |
| Started | Oct 14 09:19:06 PM UTC 24 |
| Finished | Oct 14 09:19:59 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302409109 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1302409109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_slow_rsp.259186116 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 6190289934 ps |
| CPU time | 46.38 seconds |
| Started | Oct 14 09:19:06 PM UTC 24 |
| Finished | Oct 14 09:19:54 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259186116 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.259186116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_random_zero_delays.1891831230 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 146527328 ps |
| CPU time | 8.39 seconds |
| Started | Oct 14 09:19:06 PM UTC 24 |
| Finished | Oct 14 09:19:16 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891831230 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_delays.1891831230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_same_source.2472630317 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 69781425 ps |
| CPU time | 2.25 seconds |
| Started | Oct 14 09:19:06 PM UTC 24 |
| Finished | Oct 14 09:19:10 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472630317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2472630317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke.2554846647 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 51163139 ps |
| CPU time | 2.31 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:03 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554846647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.2554846647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_large_delays.2702352062 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 6746834964 ps |
| CPU time | 11.73 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:12 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702352062 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2702352062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_slow_rsp.3167799359 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1477906021 ps |
| CPU time | 9.39 seconds |
| Started | Oct 14 09:19:02 PM UTC 24 |
| Finished | Oct 14 09:19:12 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167799359 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.3167799359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_smoke_zero_delays.1327074850 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 12147476 ps |
| CPU time | 1.43 seconds |
| Started | Oct 14 09:18:59 PM UTC 24 |
| Finished | Oct 14 09:19:02 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327074850 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays.1327074850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all.3044360693 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 712870166 ps |
| CPU time | 34.54 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:19:46 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044360693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.3044360693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_error.3718867887 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4886434658 ps |
| CPU time | 46.01 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:19:58 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718867887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3718867887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_rand_reset.1351438664 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 394365825 ps |
| CPU time | 60.46 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:20:13 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351438664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_rand_reset.1351438664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_stress_all_with_reset_error.2100907700 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 88823402 ps |
| CPU time | 14.58 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:19:27 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100907700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_reset_error.2100907700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/41.xbar_unmapped_addr.321012542 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 35299333 ps |
| CPU time | 4.63 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:19:16 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321012542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.321012542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/41.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device.1081359295 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 11801081 ps |
| CPU time | 2.41 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:19:18 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081359295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device.1081359295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_access_same_device_slow_rsp.2301394284 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 7320089957 ps |
| CPU time | 46 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:20:02 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301394284 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device_slow_rsp.2301394284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_and_unmapped_addr.1708905896 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 2135651847 ps |
| CPU time | 8.44 seconds |
| Started | Oct 14 09:19:18 PM UTC 24 |
| Finished | Oct 14 09:19:29 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708905896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.1708905896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_error_random.1416006979 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 301121421 ps |
| CPU time | 7.37 seconds |
| Started | Oct 14 09:19:18 PM UTC 24 |
| Finished | Oct 14 09:19:27 PM UTC 24 |
| Peak memory | 212936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416006979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1416006979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random.1121941720 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 637830070 ps |
| CPU time | 12.23 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:19:28 PM UTC 24 |
| Peak memory | 213004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121941720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random.1121941720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_large_delays.2486305568 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 20241035896 ps |
| CPU time | 73.34 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:20:30 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486305568 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.2486305568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_slow_rsp.1929182391 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 7067456837 ps |
| CPU time | 37.03 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:19:53 PM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929182391 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1929182391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_random_zero_delays.162036923 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 175957092 ps |
| CPU time | 6.22 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:19:22 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162036923 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delays.162036923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_same_source.317637219 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 70400264 ps |
| CPU time | 4.67 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:19:21 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317637219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.317637219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke.3974213620 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 8730795 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:19:13 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974213620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3974213620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_large_delays.1482597000 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2544620973 ps |
| CPU time | 14.01 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:19:30 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482597000 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1482597000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_slow_rsp.3510762241 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2754782862 ps |
| CPU time | 7.46 seconds |
| Started | Oct 14 09:19:15 PM UTC 24 |
| Finished | Oct 14 09:19:23 PM UTC 24 |
| Peak memory | 213008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510762241 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3510762241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_smoke_zero_delays.281808108 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 9155160 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 09:19:11 PM UTC 24 |
| Finished | Oct 14 09:19:14 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281808108 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays.281808108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all.196364318 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 521829633 ps |
| CPU time | 24.19 seconds |
| Started | Oct 14 09:19:18 PM UTC 24 |
| Finished | Oct 14 09:19:45 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196364318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.196364318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_error.610871836 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 8391783061 ps |
| CPU time | 35.6 seconds |
| Started | Oct 14 09:19:18 PM UTC 24 |
| Finished | Oct 14 09:19:56 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610871836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.610871836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_rand_reset.1074279893 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 532595772 ps |
| CPU time | 70.48 seconds |
| Started | Oct 14 09:19:18 PM UTC 24 |
| Finished | Oct 14 09:20:31 PM UTC 24 |
| Peak memory | 215004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074279893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_rand_reset.1074279893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_stress_all_with_reset_error.991672032 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 10005048010 ps |
| CPU time | 71.47 seconds |
| Started | Oct 14 09:19:22 PM UTC 24 |
| Finished | Oct 14 09:20:36 PM UTC 24 |
| Peak memory | 215084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991672032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_reset_error.991672032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/42.xbar_unmapped_addr.2832046302 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 248314191 ps |
| CPU time | 5.37 seconds |
| Started | Oct 14 09:19:18 PM UTC 24 |
| Finished | Oct 14 09:19:26 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832046302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2832046302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/42.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device.296445537 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 31813181 ps |
| CPU time | 4.67 seconds |
| Started | Oct 14 09:19:26 PM UTC 24 |
| Finished | Oct 14 09:19:32 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296445537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device.296445537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_access_same_device_slow_rsp.1461738859 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 60554733622 ps |
| CPU time | 83.94 seconds |
| Started | Oct 14 09:19:26 PM UTC 24 |
| Finished | Oct 14 09:20:52 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461738859 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device_slow_rsp.1461738859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_and_unmapped_addr.1456529628 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 78204708 ps |
| CPU time | 4.61 seconds |
| Started | Oct 14 09:19:27 PM UTC 24 |
| Finished | Oct 14 09:19:32 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456529628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_addr.1456529628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_error_random.3306039894 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 32429346 ps |
| CPU time | 3.25 seconds |
| Started | Oct 14 09:19:27 PM UTC 24 |
| Finished | Oct 14 09:19:31 PM UTC 24 |
| Peak memory | 212812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306039894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.3306039894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random.3827630555 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2819935298 ps |
| CPU time | 11.23 seconds |
| Started | Oct 14 09:19:23 PM UTC 24 |
| Finished | Oct 14 09:19:36 PM UTC 24 |
| Peak memory | 212976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827630555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random.3827630555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_large_delays.4228225846 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 15570008674 ps |
| CPU time | 65.4 seconds |
| Started | Oct 14 09:19:26 PM UTC 24 |
| Finished | Oct 14 09:20:33 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228225846 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.4228225846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_slow_rsp.2216779401 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 13615130792 ps |
| CPU time | 60.82 seconds |
| Started | Oct 14 09:19:26 PM UTC 24 |
| Finished | Oct 14 09:20:29 PM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216779401 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2216779401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_random_zero_delays.314854611 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 63824412 ps |
| CPU time | 7.06 seconds |
| Started | Oct 14 09:19:26 PM UTC 24 |
| Finished | Oct 14 09:19:35 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314854611 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_delays.314854611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_same_source.768894446 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 57350573 ps |
| CPU time | 8.1 seconds |
| Started | Oct 14 09:19:26 PM UTC 24 |
| Finished | Oct 14 09:19:36 PM UTC 24 |
| Peak memory | 210972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768894446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.768894446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke.3709177915 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 53571142 ps |
| CPU time | 1.9 seconds |
| Started | Oct 14 09:19:22 PM UTC 24 |
| Finished | Oct 14 09:19:26 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709177915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.3709177915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_large_delays.575304600 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2721946416 ps |
| CPU time | 13.59 seconds |
| Started | Oct 14 09:19:23 PM UTC 24 |
| Finished | Oct 14 09:19:38 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575304600 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.575304600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_slow_rsp.95357625 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2890128121 ps |
| CPU time | 12.53 seconds |
| Started | Oct 14 09:19:23 PM UTC 24 |
| Finished | Oct 14 09:19:37 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95357625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.95357625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_smoke_zero_delays.2712721046 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 10877886 ps |
| CPU time | 1.47 seconds |
| Started | Oct 14 09:19:22 PM UTC 24 |
| Finished | Oct 14 09:19:25 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712721046 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays.2712721046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all.2880860521 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 13943664945 ps |
| CPU time | 84.5 seconds |
| Started | Oct 14 09:19:31 PM UTC 24 |
| Finished | Oct 14 09:20:57 PM UTC 24 |
| Peak memory | 215072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880860521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2880860521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_error.3945315423 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3386471984 ps |
| CPU time | 32.95 seconds |
| Started | Oct 14 09:19:31 PM UTC 24 |
| Finished | Oct 14 09:20:05 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945315423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.3945315423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_rand_reset.49561453 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 3693197462 ps |
| CPU time | 84.48 seconds |
| Started | Oct 14 09:19:31 PM UTC 24 |
| Finished | Oct 14 09:20:57 PM UTC 24 |
| Peak memory | 215152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49561453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_rand_reset.49561453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_stress_all_with_reset_error.352151241 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 226449692 ps |
| CPU time | 36.39 seconds |
| Started | Oct 14 09:19:31 PM UTC 24 |
| Finished | Oct 14 09:20:09 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352151241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_reset_error.352151241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/43.xbar_unmapped_addr.168288648 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 645544996 ps |
| CPU time | 11.93 seconds |
| Started | Oct 14 09:19:27 PM UTC 24 |
| Finished | Oct 14 09:19:40 PM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168288648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.168288648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/43.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device.524751852 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 236552182 ps |
| CPU time | 6.39 seconds |
| Started | Oct 14 09:19:36 PM UTC 24 |
| Finished | Oct 14 09:19:44 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524751852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device.524751852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_access_same_device_slow_rsp.1542023322 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 4602360979 ps |
| CPU time | 34.23 seconds |
| Started | Oct 14 09:19:36 PM UTC 24 |
| Finished | Oct 14 09:20:11 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542023322 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device_slow_rsp.1542023322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_and_unmapped_addr.2326961294 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 46341143 ps |
| CPU time | 3.65 seconds |
| Started | Oct 14 09:19:40 PM UTC 24 |
| Finished | Oct 14 09:19:45 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326961294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr.2326961294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_error_random.108459502 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 38444585 ps |
| CPU time | 2.06 seconds |
| Started | Oct 14 09:19:39 PM UTC 24 |
| Finished | Oct 14 09:19:42 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108459502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.108459502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random.3146943009 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 170738568 ps |
| CPU time | 9.73 seconds |
| Started | Oct 14 09:19:36 PM UTC 24 |
| Finished | Oct 14 09:19:47 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146943009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random.3146943009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_large_delays.1218646908 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 14557860528 ps |
| CPU time | 34.87 seconds |
| Started | Oct 14 09:19:36 PM UTC 24 |
| Finished | Oct 14 09:20:12 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218646908 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1218646908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_slow_rsp.686881499 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4316353905 ps |
| CPU time | 18.53 seconds |
| Started | Oct 14 09:19:36 PM UTC 24 |
| Finished | Oct 14 09:19:55 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686881499 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.686881499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_random_zero_delays.1664054280 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 109486524 ps |
| CPU time | 6.96 seconds |
| Started | Oct 14 09:19:36 PM UTC 24 |
| Finished | Oct 14 09:19:44 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664054280 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_delays.1664054280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_same_source.317100414 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 45188951 ps |
| CPU time | 2.71 seconds |
| Started | Oct 14 09:19:36 PM UTC 24 |
| Finished | Oct 14 09:19:40 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317100414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.317100414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke.1484208504 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 9173360 ps |
| CPU time | 1.48 seconds |
| Started | Oct 14 09:19:31 PM UTC 24 |
| Finished | Oct 14 09:19:33 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484208504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.1484208504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_large_delays.3936566559 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2269718194 ps |
| CPU time | 8.45 seconds |
| Started | Oct 14 09:19:35 PM UTC 24 |
| Finished | Oct 14 09:19:45 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936566559 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3936566559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_slow_rsp.4233876483 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4509348731 ps |
| CPU time | 13.43 seconds |
| Started | Oct 14 09:19:35 PM UTC 24 |
| Finished | Oct 14 09:19:50 PM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233876483 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.4233876483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_smoke_zero_delays.999493320 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 8913944 ps |
| CPU time | 1.69 seconds |
| Started | Oct 14 09:19:31 PM UTC 24 |
| Finished | Oct 14 09:19:34 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999493320 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays.999493320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all.1331982294 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 573916021 ps |
| CPU time | 10.13 seconds |
| Started | Oct 14 09:19:40 PM UTC 24 |
| Finished | Oct 14 09:19:51 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331982294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1331982294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_error.2842075203 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 668713414 ps |
| CPU time | 5.24 seconds |
| Started | Oct 14 09:19:40 PM UTC 24 |
| Finished | Oct 14 09:19:47 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842075203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2842075203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_rand_reset.1874529795 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5926114264 ps |
| CPU time | 93.59 seconds |
| Started | Oct 14 09:19:40 PM UTC 24 |
| Finished | Oct 14 09:21:16 PM UTC 24 |
| Peak memory | 215120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874529795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_rand_reset.1874529795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_stress_all_with_reset_error.3294394722 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 144909314 ps |
| CPU time | 17.33 seconds |
| Started | Oct 14 09:19:43 PM UTC 24 |
| Finished | Oct 14 09:20:01 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294394722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_reset_error.3294394722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/44.xbar_unmapped_addr.384959223 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 669971671 ps |
| CPU time | 13.55 seconds |
| Started | Oct 14 09:19:40 PM UTC 24 |
| Finished | Oct 14 09:19:55 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384959223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.384959223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/44.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device.3640479628 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3876676699 ps |
| CPU time | 22.29 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:20:10 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640479628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device.3640479628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_access_same_device_slow_rsp.614746270 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 9011888678 ps |
| CPU time | 72.48 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:21:01 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614746270 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device_slow_rsp.614746270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_and_unmapped_addr.3104488746 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 156338306 ps |
| CPU time | 1.82 seconds |
| Started | Oct 14 09:19:51 PM UTC 24 |
| Finished | Oct 14 09:19:54 PM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104488746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.3104488746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_error_random.1147624588 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 287616797 ps |
| CPU time | 5.69 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:19:54 PM UTC 24 |
| Peak memory | 212992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147624588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1147624588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random.118498088 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 78844430 ps |
| CPU time | 5.89 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:19:54 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118498088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random.118498088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_large_delays.2288437125 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 8792511283 ps |
| CPU time | 32.25 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:20:20 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288437125 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2288437125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_slow_rsp.903942087 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5720178973 ps |
| CPU time | 8.91 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:19:57 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903942087 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.903942087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_random_zero_delays.312702638 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 160282429 ps |
| CPU time | 4.51 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:19:52 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312702638 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_delays.312702638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_same_source.60484383 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3550884337 ps |
| CPU time | 5.7 seconds |
| Started | Oct 14 09:19:47 PM UTC 24 |
| Finished | Oct 14 09:19:54 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60484383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.60484383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke.1052291332 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 451661744 ps |
| CPU time | 2.32 seconds |
| Started | Oct 14 09:19:43 PM UTC 24 |
| Finished | Oct 14 09:19:46 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052291332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1052291332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_large_delays.3788654322 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 17371100703 ps |
| CPU time | 13.3 seconds |
| Started | Oct 14 09:19:43 PM UTC 24 |
| Finished | Oct 14 09:19:58 PM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788654322 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.3788654322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_slow_rsp.3844308956 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 1479872022 ps |
| CPU time | 7.69 seconds |
| Started | Oct 14 09:19:43 PM UTC 24 |
| Finished | Oct 14 09:19:52 PM UTC 24 |
| Peak memory | 212952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844308956 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.3844308956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_smoke_zero_delays.331069627 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 15353452 ps |
| CPU time | 1.48 seconds |
| Started | Oct 14 09:19:43 PM UTC 24 |
| Finished | Oct 14 09:19:46 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331069627 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays.331069627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all.4095643400 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 10567539550 ps |
| CPU time | 69.77 seconds |
| Started | Oct 14 09:19:51 PM UTC 24 |
| Finished | Oct 14 09:21:03 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095643400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4095643400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_error.559369774 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 15655860457 ps |
| CPU time | 73.72 seconds |
| Started | Oct 14 09:19:51 PM UTC 24 |
| Finished | Oct 14 09:21:07 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559369774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.559369774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_stress_all_with_reset_error.1099522681 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 9348366931 ps |
| CPU time | 72 seconds |
| Started | Oct 14 09:19:51 PM UTC 24 |
| Finished | Oct 14 09:21:05 PM UTC 24 |
| Peak memory | 215060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099522681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_reset_error.1099522681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/45.xbar_unmapped_addr.914565457 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 983973243 ps |
| CPU time | 4.04 seconds |
| Started | Oct 14 09:19:51 PM UTC 24 |
| Finished | Oct 14 09:19:56 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914565457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.914565457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/45.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device.240570270 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 1716300687 ps |
| CPU time | 18.08 seconds |
| Started | Oct 14 09:19:56 PM UTC 24 |
| Finished | Oct 14 09:20:15 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240570270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device.240570270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_access_same_device_slow_rsp.2099318796 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 47800512270 ps |
| CPU time | 61.6 seconds |
| Started | Oct 14 09:19:56 PM UTC 24 |
| Finished | Oct 14 09:20:59 PM UTC 24 |
| Peak memory | 213068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099318796 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device_slow_rsp.2099318796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_and_unmapped_addr.4113226249 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 18514164 ps |
| CPU time | 1.71 seconds |
| Started | Oct 14 09:20:00 PM UTC 24 |
| Finished | Oct 14 09:20:03 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113226249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr.4113226249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_error_random.3619633284 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 796200044 ps |
| CPU time | 8.42 seconds |
| Started | Oct 14 09:19:56 PM UTC 24 |
| Finished | Oct 14 09:20:05 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619633284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3619633284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random.2113301924 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 138779673 ps |
| CPU time | 5.42 seconds |
| Started | Oct 14 09:19:55 PM UTC 24 |
| Finished | Oct 14 09:20:02 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113301924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random.2113301924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_large_delays.112580025 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 4925717125 ps |
| CPU time | 12.95 seconds |
| Started | Oct 14 09:19:56 PM UTC 24 |
| Finished | Oct 14 09:20:10 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112580025 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.112580025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_slow_rsp.3116584259 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 1202413626 ps |
| CPU time | 7.75 seconds |
| Started | Oct 14 09:19:56 PM UTC 24 |
| Finished | Oct 14 09:20:04 PM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116584259 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3116584259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_random_zero_delays.2685555219 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 39444743 ps |
| CPU time | 6 seconds |
| Started | Oct 14 09:19:55 PM UTC 24 |
| Finished | Oct 14 09:20:03 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685555219 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delays.2685555219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_same_source.2833028133 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 43103771 ps |
| CPU time | 2.06 seconds |
| Started | Oct 14 09:19:56 PM UTC 24 |
| Finished | Oct 14 09:19:59 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833028133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2833028133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke.4026777949 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 286521482 ps |
| CPU time | 2.33 seconds |
| Started | Oct 14 09:19:51 PM UTC 24 |
| Finished | Oct 14 09:19:55 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026777949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4026777949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_large_delays.2622278340 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3025772365 ps |
| CPU time | 8.93 seconds |
| Started | Oct 14 09:19:55 PM UTC 24 |
| Finished | Oct 14 09:20:05 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622278340 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.2622278340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_slow_rsp.3407212838 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 993864150 ps |
| CPU time | 8.96 seconds |
| Started | Oct 14 09:19:55 PM UTC 24 |
| Finished | Oct 14 09:20:05 PM UTC 24 |
| Peak memory | 213016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407212838 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3407212838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_smoke_zero_delays.3961993951 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 8748665 ps |
| CPU time | 1.36 seconds |
| Started | Oct 14 09:19:55 PM UTC 24 |
| Finished | Oct 14 09:19:58 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961993951 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.3961993951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all.3917714923 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 718544117 ps |
| CPU time | 46.13 seconds |
| Started | Oct 14 09:20:00 PM UTC 24 |
| Finished | Oct 14 09:20:48 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917714923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3917714923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_error.2821729242 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2317169096 ps |
| CPU time | 14.02 seconds |
| Started | Oct 14 09:20:00 PM UTC 24 |
| Finished | Oct 14 09:20:16 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821729242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2821729242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_rand_reset.1965001140 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 1540739423 ps |
| CPU time | 75.1 seconds |
| Started | Oct 14 09:20:00 PM UTC 24 |
| Finished | Oct 14 09:21:17 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965001140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_rand_reset.1965001140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_stress_all_with_reset_error.3028203041 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 955953432 ps |
| CPU time | 61.54 seconds |
| Started | Oct 14 09:20:00 PM UTC 24 |
| Finished | Oct 14 09:21:04 PM UTC 24 |
| Peak memory | 215020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028203041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_reset_error.3028203041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/46.xbar_unmapped_addr.114638516 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 209749009 ps |
| CPU time | 3.94 seconds |
| Started | Oct 14 09:20:00 PM UTC 24 |
| Finished | Oct 14 09:20:05 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114638516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.114638516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/46.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device.2299933740 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 18515200 ps |
| CPU time | 2.31 seconds |
| Started | Oct 14 09:20:03 PM UTC 24 |
| Finished | Oct 14 09:20:06 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299933740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device.2299933740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_access_same_device_slow_rsp.317936535 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 28341144098 ps |
| CPU time | 73.79 seconds |
| Started | Oct 14 09:20:03 PM UTC 24 |
| Finished | Oct 14 09:21:19 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317936535 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device_slow_rsp.317936535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_and_unmapped_addr.1821302047 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 782689873 ps |
| CPU time | 3.79 seconds |
| Started | Oct 14 09:20:06 PM UTC 24 |
| Finished | Oct 14 09:20:11 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821302047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_addr.1821302047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_error_random.3011079867 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1559451843 ps |
| CPU time | 11.28 seconds |
| Started | Oct 14 09:20:03 PM UTC 24 |
| Finished | Oct 14 09:20:16 PM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011079867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3011079867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random.220896520 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 410423428 ps |
| CPU time | 5.7 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:20:08 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220896520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random.220896520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_large_delays.1035302594 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 16679969195 ps |
| CPU time | 92.26 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:21:35 PM UTC 24 |
| Peak memory | 213160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035302594 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1035302594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_slow_rsp.1005355372 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 53003979698 ps |
| CPU time | 44.6 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:20:47 PM UTC 24 |
| Peak memory | 210968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005355372 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1005355372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_random_zero_delays.2707112181 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 58726786 ps |
| CPU time | 7.11 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:20:09 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707112181 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delays.2707112181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_same_source.2066498830 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 242987954 ps |
| CPU time | 2.7 seconds |
| Started | Oct 14 09:20:03 PM UTC 24 |
| Finished | Oct 14 09:20:07 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066498830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2066498830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke.259911430 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 18571237 ps |
| CPU time | 1.31 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:20:03 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259911430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vc s/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.259911430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_large_delays.570911957 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2160270828 ps |
| CPU time | 12.23 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:20:14 PM UTC 24 |
| Peak memory | 212996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570911957 -assert nopostproc +UVM_TESTNAME=xbar_base _test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.570911957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_slow_rsp.3727749690 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1789312903 ps |
| CPU time | 8.17 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:20:10 PM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727749690 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.3727749690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_smoke_zero_delays.38210310 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 22542565 ps |
| CPU time | 1.62 seconds |
| Started | Oct 14 09:20:01 PM UTC 24 |
| Finished | Oct 14 09:20:03 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38210310 -assert nopostproc +UVM_TESTNAME=xbar_ base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays.38210310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all.3820982288 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2735224559 ps |
| CPU time | 25.88 seconds |
| Started | Oct 14 09:20:06 PM UTC 24 |
| Finished | Oct 14 09:20:33 PM UTC 24 |
| Peak memory | 211108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820982288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3820982288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_error.1000438197 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1209513036 ps |
| CPU time | 9.59 seconds |
| Started | Oct 14 09:20:06 PM UTC 24 |
| Finished | Oct 14 09:20:17 PM UTC 24 |
| Peak memory | 212928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000438197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1000438197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_stress_all_with_reset_error.1199652269 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 4214617777 ps |
| CPU time | 86.07 seconds |
| Started | Oct 14 09:20:06 PM UTC 24 |
| Finished | Oct 14 09:21:34 PM UTC 24 |
| Peak memory | 213040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199652269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_reset_error.1199652269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/47.xbar_unmapped_addr.2576400825 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 362336496 ps |
| CPU time | 5.78 seconds |
| Started | Oct 14 09:20:03 PM UTC 24 |
| Finished | Oct 14 09:20:10 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576400825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2576400825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/47.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device.1399026509 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 57298583 ps |
| CPU time | 5.13 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:20:17 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399026509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device.1399026509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_access_same_device_slow_rsp.341872350 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 24903879834 ps |
| CPU time | 108.06 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:22:01 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341872350 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device_slow_rsp.341872350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_and_unmapped_addr.3320413640 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 186868026 ps |
| CPU time | 3.56 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:18 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320413640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_addr.3320413640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_error_random.3144073777 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 109741926 ps |
| CPU time | 2.38 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:20:14 PM UTC 24 |
| Peak memory | 212932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144073777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3144073777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random.2568256887 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 65829008 ps |
| CPU time | 6.27 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:20:18 PM UTC 24 |
| Peak memory | 210848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568256887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random.2568256887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_large_delays.3248945847 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 9326715819 ps |
| CPU time | 40.59 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:20:53 PM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248945847 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3248945847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_slow_rsp.3792066538 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 18861350738 ps |
| CPU time | 43.92 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:20:56 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792066538 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3792066538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_random_zero_delays.591393738 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 29258792 ps |
| CPU time | 3.71 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:20:15 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591393738 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_delays.591393738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_same_source.3793077842 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1301280626 ps |
| CPU time | 12.67 seconds |
| Started | Oct 14 09:20:11 PM UTC 24 |
| Finished | Oct 14 09:20:25 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793077842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3793077842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke.3650980567 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 67987611 ps |
| CPU time | 2.4 seconds |
| Started | Oct 14 09:20:06 PM UTC 24 |
| Finished | Oct 14 09:20:10 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650980567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3650980567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_large_delays.2415314789 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4245532291 ps |
| CPU time | 9.09 seconds |
| Started | Oct 14 09:20:10 PM UTC 24 |
| Finished | Oct 14 09:20:21 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415314789 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2415314789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_slow_rsp.1156573130 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1263272044 ps |
| CPU time | 9.46 seconds |
| Started | Oct 14 09:20:10 PM UTC 24 |
| Finished | Oct 14 09:20:21 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156573130 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1156573130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_smoke_zero_delays.3609497800 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 8479932 ps |
| CPU time | 1.56 seconds |
| Started | Oct 14 09:20:10 PM UTC 24 |
| Finished | Oct 14 09:20:13 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609497800 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays.3609497800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all.2793969297 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 22601629305 ps |
| CPU time | 68.41 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:21:24 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793969297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.2793969297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_error.1191113031 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 321798892 ps |
| CPU time | 11.48 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:27 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191113031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1191113031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_rand_reset.157478086 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1442950454 ps |
| CPU time | 35.56 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:51 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157478086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_rand_reset.157478086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_stress_all_with_reset_error.439238768 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2293546586 ps |
| CPU time | 56.45 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:21:12 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439238768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_reset_error.439238768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/48.xbar_unmapped_addr.593225418 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 40939667 ps |
| CPU time | 3.77 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:19 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593225418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.593225418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/48.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device.2548321137 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 694347540 ps |
| CPU time | 13.54 seconds |
| Started | Oct 14 09:20:18 PM UTC 24 |
| Finished | Oct 14 09:20:33 PM UTC 24 |
| Peak memory | 210908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548321137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device.2548321137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_access_same_device_slow_rsp.1727522775 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 8334929533 ps |
| CPU time | 16.12 seconds |
| Started | Oct 14 09:20:18 PM UTC 24 |
| Finished | Oct 14 09:20:36 PM UTC 24 |
| Peak memory | 213080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727522775 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device_slow_rsp.1727522775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_and_unmapped_addr.2909337022 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 845726727 ps |
| CPU time | 7.54 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:20:27 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909337022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.2909337022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_error_random.1666008330 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1491410162 ps |
| CPU time | 9.39 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:20:29 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666008330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.1666008330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random.2564212537 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 1100737524 ps |
| CPU time | 14.31 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:30 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564212537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random.2564212537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_large_delays.1691793336 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 9033419884 ps |
| CPU time | 39.03 seconds |
| Started | Oct 14 09:20:18 PM UTC 24 |
| Finished | Oct 14 09:20:59 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691793336 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1691793336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_slow_rsp.3970160540 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3130994958 ps |
| CPU time | 19.89 seconds |
| Started | Oct 14 09:20:18 PM UTC 24 |
| Finished | Oct 14 09:20:39 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970160540 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3970160540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_random_zero_delays.3139634950 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 61292420 ps |
| CPU time | 9.32 seconds |
| Started | Oct 14 09:20:18 PM UTC 24 |
| Finished | Oct 14 09:20:29 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139634950 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_delays.3139634950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_same_source.1200892114 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1086507446 ps |
| CPU time | 13.52 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:20:33 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200892114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1200892114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke.1297401455 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 10568883 ps |
| CPU time | 1.5 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:17 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297401455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1297401455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_large_delays.4173085515 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4984085746 ps |
| CPU time | 9.4 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:25 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173085515 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4173085515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_slow_rsp.1356411906 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2412444280 ps |
| CPU time | 10.99 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:26 PM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356411906 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.1356411906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_smoke_zero_delays.446510103 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 12478920 ps |
| CPU time | 1.72 seconds |
| Started | Oct 14 09:20:14 PM UTC 24 |
| Finished | Oct 14 09:20:17 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446510103 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays.446510103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all.2836222968 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 9462738321 ps |
| CPU time | 46.26 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:21:07 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836222968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2836222968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_error.2163518911 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 544078705 ps |
| CPU time | 31.71 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:20:52 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163518911 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2163518911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_rand_reset.1664924358 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 7569870 ps |
| CPU time | 3.47 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:20:23 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664924358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_rand_reset.1664924358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_stress_all_with_reset_error.2385861678 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 221096903 ps |
| CPU time | 47.59 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:21:08 PM UTC 24 |
| Peak memory | 212960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385861678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_reset_error.2385861678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/49.xbar_unmapped_addr.2122531595 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 70160255 ps |
| CPU time | 2.75 seconds |
| Started | Oct 14 09:20:19 PM UTC 24 |
| Finished | Oct 14 09:20:22 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122531595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2122531595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/49.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_access_same_device.3948928810 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 581856129 ps |
| CPU time | 6.53 seconds |
| Started | Oct 14 09:13:05 PM UTC 24 |
| Finished | Oct 14 09:13:13 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948928810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device.3948928810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_and_unmapped_addr.3491398743 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1944321007 ps |
| CPU time | 10.59 seconds |
| Started | Oct 14 09:13:09 PM UTC 24 |
| Finished | Oct 14 09:13:22 PM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491398743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr.3491398743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_error_random.1965347953 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 419849251 ps |
| CPU time | 9.53 seconds |
| Started | Oct 14 09:13:06 PM UTC 24 |
| Finished | Oct 14 09:13:17 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965347953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1965347953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random.2852846094 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 587019765 ps |
| CPU time | 14.8 seconds |
| Started | Oct 14 09:13:04 PM UTC 24 |
| Finished | Oct 14 09:13:20 PM UTC 24 |
| Peak memory | 212900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852846094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random.2852846094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_large_delays.3693159208 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 15939514228 ps |
| CPU time | 51.33 seconds |
| Started | Oct 14 09:13:05 PM UTC 24 |
| Finished | Oct 14 09:13:58 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693159208 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.3693159208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_slow_rsp.1638814882 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 8969144337 ps |
| CPU time | 47.88 seconds |
| Started | Oct 14 09:13:05 PM UTC 24 |
| Finished | Oct 14 09:13:55 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638814882 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1638814882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_random_zero_delays.2960013572 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 85926201 ps |
| CPU time | 5.2 seconds |
| Started | Oct 14 09:13:04 PM UTC 24 |
| Finished | Oct 14 09:13:10 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960013572 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_delays.2960013572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke.3250265140 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 9893770 ps |
| CPU time | 1.7 seconds |
| Started | Oct 14 09:13:01 PM UTC 24 |
| Finished | Oct 14 09:13:04 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250265140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3250265140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_large_delays.2886960787 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3222479922 ps |
| CPU time | 16.69 seconds |
| Started | Oct 14 09:13:04 PM UTC 24 |
| Finished | Oct 14 09:13:22 PM UTC 24 |
| Peak memory | 211044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886960787 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2886960787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_slow_rsp.3710098695 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1048691269 ps |
| CPU time | 9.17 seconds |
| Started | Oct 14 09:13:04 PM UTC 24 |
| Finished | Oct 14 09:13:14 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710098695 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3710098695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_smoke_zero_delays.604892272 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 29731798 ps |
| CPU time | 1.83 seconds |
| Started | Oct 14 09:13:02 PM UTC 24 |
| Finished | Oct 14 09:13:04 PM UTC 24 |
| Peak memory | 211968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604892272 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays.604892272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all.698750893 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4132186258 ps |
| CPU time | 34.5 seconds |
| Started | Oct 14 09:13:10 PM UTC 24 |
| Finished | Oct 14 09:13:46 PM UTC 24 |
| Peak memory | 213096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698750893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-s im-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.698750893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_error.2097354664 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 867304356 ps |
| CPU time | 19.11 seconds |
| Started | Oct 14 09:13:13 PM UTC 24 |
| Finished | Oct 14 09:13:33 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097354664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.2097354664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_rand_reset.984370744 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 527290977 ps |
| CPU time | 92.88 seconds |
| Started | Oct 14 09:13:13 PM UTC 24 |
| Finished | Oct 14 09:14:48 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984370744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_rand_reset.984370744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_stress_all_with_reset_error.4250271787 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1949670664 ps |
| CPU time | 87.28 seconds |
| Started | Oct 14 09:13:13 PM UTC 24 |
| Finished | Oct 14 09:14:42 PM UTC 24 |
| Peak memory | 215016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250271787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_reset_error.4250271787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/5.xbar_unmapped_addr.254004042 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 78929872 ps |
| CPU time | 4.79 seconds |
| Started | Oct 14 09:13:09 PM UTC 24 |
| Finished | Oct 14 09:13:16 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254004042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_per i-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.254004042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/5.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_access_same_device.3372528678 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 117029685 ps |
| CPU time | 10.75 seconds |
| Started | Oct 14 09:13:18 PM UTC 24 |
| Finished | Oct 14 09:13:30 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372528678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.3372528678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_and_unmapped_addr.4049768039 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 54234115 ps |
| CPU time | 6.28 seconds |
| Started | Oct 14 09:13:22 PM UTC 24 |
| Finished | Oct 14 09:13:29 PM UTC 24 |
| Peak memory | 212972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049768039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr.4049768039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_error_random.2153642064 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 180762936 ps |
| CPU time | 7.98 seconds |
| Started | Oct 14 09:13:22 PM UTC 24 |
| Finished | Oct 14 09:13:31 PM UTC 24 |
| Peak memory | 210904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153642064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.2153642064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random.3225162154 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 918882212 ps |
| CPU time | 16.61 seconds |
| Started | Oct 14 09:13:15 PM UTC 24 |
| Finished | Oct 14 09:13:33 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225162154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random.3225162154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_large_delays.3844619668 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 10046303031 ps |
| CPU time | 30.99 seconds |
| Started | Oct 14 09:13:16 PM UTC 24 |
| Finished | Oct 14 09:13:49 PM UTC 24 |
| Peak memory | 213028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844619668 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.3844619668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_slow_rsp.1513595 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 7664234044 ps |
| CPU time | 52.46 seconds |
| Started | Oct 14 09:13:16 PM UTC 24 |
| Finished | Oct 14 09:14:11 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513595 -assert nopostproc +UVM_TESTNA ME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1513595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_random_zero_delays.1907443102 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 101424783 ps |
| CPU time | 6.62 seconds |
| Started | Oct 14 09:13:15 PM UTC 24 |
| Finished | Oct 14 09:13:23 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907443102 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays.1907443102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_same_source.2896727232 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 24361631 ps |
| CPU time | 1.86 seconds |
| Started | Oct 14 09:13:18 PM UTC 24 |
| Finished | Oct 14 09:13:21 PM UTC 24 |
| Peak memory | 209932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896727232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2896727232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke.2601782563 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 86130880 ps |
| CPU time | 2.22 seconds |
| Started | Oct 14 09:13:13 PM UTC 24 |
| Finished | Oct 14 09:13:16 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601782563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2601782563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_large_delays.3394878117 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3121368989 ps |
| CPU time | 15.81 seconds |
| Started | Oct 14 09:13:14 PM UTC 24 |
| Finished | Oct 14 09:13:31 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394878117 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3394878117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_slow_rsp.3442503273 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 7567096272 ps |
| CPU time | 12.28 seconds |
| Started | Oct 14 09:13:15 PM UTC 24 |
| Finished | Oct 14 09:13:29 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442503273 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.3442503273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_smoke_zero_delays.2311724667 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 11286929 ps |
| CPU time | 1.58 seconds |
| Started | Oct 14 09:13:13 PM UTC 24 |
| Finished | Oct 14 09:13:16 PM UTC 24 |
| Peak memory | 211956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311724667 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays.2311724667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all.1955572301 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3462041372 ps |
| CPU time | 46.29 seconds |
| Started | Oct 14 09:13:22 PM UTC 24 |
| Finished | Oct 14 09:14:10 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955572301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1955572301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_error.2198553052 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 824982061 ps |
| CPU time | 14.05 seconds |
| Started | Oct 14 09:13:23 PM UTC 24 |
| Finished | Oct 14 09:13:38 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198553052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2198553052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_rand_reset.3644909024 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 10263818165 ps |
| CPU time | 164.62 seconds |
| Started | Oct 14 09:13:22 PM UTC 24 |
| Finished | Oct 14 09:16:10 PM UTC 24 |
| Peak memory | 215204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644909024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_rand_reset.3644909024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_stress_all_with_reset_error.1013134033 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 735479581 ps |
| CPU time | 82.32 seconds |
| Started | Oct 14 09:13:23 PM UTC 24 |
| Finished | Oct 14 09:14:47 PM UTC 24 |
| Peak memory | 215000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013134033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_reset_error.1013134033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/6.xbar_unmapped_addr.2385022475 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 636038924 ps |
| CPU time | 4.77 seconds |
| Started | Oct 14 09:13:22 PM UTC 24 |
| Finished | Oct 14 09:13:28 PM UTC 24 |
| Peak memory | 212956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385022475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.2385022475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/6.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_access_same_device.1599456647 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 571666871 ps |
| CPU time | 11.56 seconds |
| Started | Oct 14 09:13:31 PM UTC 24 |
| Finished | Oct 14 09:13:44 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599456647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xb ar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.1599456647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_and_unmapped_addr.3427944785 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 256355021 ps |
| CPU time | 7.39 seconds |
| Started | Oct 14 09:13:34 PM UTC 24 |
| Finished | Oct 14 09:13:42 PM UTC 24 |
| Peak memory | 210988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427944785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr.3427944785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_error_random.854953474 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 1047501737 ps |
| CPU time | 10.71 seconds |
| Started | Oct 14 09:13:34 PM UTC 24 |
| Finished | Oct 14 09:13:45 PM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854953474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.854953474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random.598301003 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 14999229 ps |
| CPU time | 1.7 seconds |
| Started | Oct 14 09:13:30 PM UTC 24 |
| Finished | Oct 14 09:13:33 PM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598301003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random.598301003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_large_delays.455823470 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 13747655239 ps |
| CPU time | 49.41 seconds |
| Started | Oct 14 09:13:30 PM UTC 24 |
| Finished | Oct 14 09:14:21 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455823470 -assert nopostproc +UVM_ TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.455823470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_slow_rsp.2231614666 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 5793956164 ps |
| CPU time | 52.28 seconds |
| Started | Oct 14 09:13:31 PM UTC 24 |
| Finished | Oct 14 09:14:25 PM UTC 24 |
| Peak memory | 210964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231614666 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2231614666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_random_zero_delays.923977149 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 93385404 ps |
| CPU time | 7.72 seconds |
| Started | Oct 14 09:13:30 PM UTC 24 |
| Finished | Oct 14 09:13:39 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923977149 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delays.923977149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_same_source.2331758059 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 34512111 ps |
| CPU time | 2.82 seconds |
| Started | Oct 14 09:13:32 PM UTC 24 |
| Finished | Oct 14 09:13:36 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331758059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2331758059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke.1441039796 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 97538191 ps |
| CPU time | 2.63 seconds |
| Started | Oct 14 09:13:24 PM UTC 24 |
| Finished | Oct 14 09:13:28 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441039796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1441039796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_large_delays.2152817309 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1377990714 ps |
| CPU time | 8.52 seconds |
| Started | Oct 14 09:13:28 PM UTC 24 |
| Finished | Oct 14 09:13:38 PM UTC 24 |
| Peak memory | 212940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152817309 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2152817309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_slow_rsp.1179686359 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1218096135 ps |
| CPU time | 9.06 seconds |
| Started | Oct 14 09:13:29 PM UTC 24 |
| Finished | Oct 14 09:13:40 PM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179686359 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1179686359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_smoke_zero_delays.897208902 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 10552333 ps |
| CPU time | 1.78 seconds |
| Started | Oct 14 09:13:25 PM UTC 24 |
| Finished | Oct 14 09:13:28 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897208902 -assert nopostproc +UVM_TESTNAME=xbar _base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/x bar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays.897208902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all.2037553587 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 644346905 ps |
| CPU time | 51.67 seconds |
| Started | Oct 14 09:13:34 PM UTC 24 |
| Finished | Oct 14 09:14:27 PM UTC 24 |
| Peak memory | 215012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037553587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2037553587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_error.3392135086 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2707298796 ps |
| CPU time | 39.38 seconds |
| Started | Oct 14 09:13:36 PM UTC 24 |
| Finished | Oct 14 09:14:17 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392135086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3392135086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_rand_reset.156654487 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 556499448 ps |
| CPU time | 54.17 seconds |
| Started | Oct 14 09:13:36 PM UTC 24 |
| Finished | Oct 14 09:14:31 PM UTC 24 |
| Peak memory | 215080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156654487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_rand_reset.156654487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_stress_all_with_reset_error.1753120247 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 74648385 ps |
| CPU time | 15.02 seconds |
| Started | Oct 14 09:13:36 PM UTC 24 |
| Finished | Oct 14 09:13:52 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753120247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_reset_error.1753120247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/7.xbar_unmapped_addr.3750278393 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 517556622 ps |
| CPU time | 3.06 seconds |
| Started | Oct 14 09:13:34 PM UTC 24 |
| Finished | Oct 14 09:13:38 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750278393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3750278393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/7.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device.71020843 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 40033716 ps |
| CPU time | 4.99 seconds |
| Started | Oct 14 09:13:40 PM UTC 24 |
| Finished | Oct 14 09:13:46 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71020843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar _peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.71020843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_access_same_device_slow_rsp.79104455 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 14548052475 ps |
| CPU time | 113.55 seconds |
| Started | Oct 14 09:13:40 PM UTC 24 |
| Finished | Oct 14 09:15:35 PM UTC 24 |
| Peak memory | 211048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79104455 -assert nopostproc +UVM_TESTN AME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device_slow_rsp.79104455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_and_unmapped_addr.3289436301 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 122571286 ps |
| CPU time | 7.37 seconds |
| Started | Oct 14 09:13:42 PM UTC 24 |
| Finished | Oct 14 09:13:50 PM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289436301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.3289436301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_error_random.1926200189 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1811206381 ps |
| CPU time | 14.34 seconds |
| Started | Oct 14 09:13:40 PM UTC 24 |
| Finished | Oct 14 09:13:55 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926200189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1926200189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random.310096640 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 455395052 ps |
| CPU time | 9.19 seconds |
| Started | Oct 14 09:13:38 PM UTC 24 |
| Finished | Oct 14 09:13:49 PM UTC 24 |
| Peak memory | 212968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310096640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random.310096640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_large_delays.2449117125 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 16075061226 ps |
| CPU time | 79.58 seconds |
| Started | Oct 14 09:13:40 PM UTC 24 |
| Finished | Oct 14 09:15:01 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449117125 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2449117125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_slow_rsp.3791817856 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4065482932 ps |
| CPU time | 26.52 seconds |
| Started | Oct 14 09:13:40 PM UTC 24 |
| Finished | Oct 14 09:14:07 PM UTC 24 |
| Peak memory | 213000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791817856 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3791817856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_random_zero_delays.2466331593 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 133748962 ps |
| CPU time | 4.53 seconds |
| Started | Oct 14 09:13:38 PM UTC 24 |
| Finished | Oct 14 09:13:44 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466331593 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_delays.2466331593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_same_source.4208131118 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 18678436 ps |
| CPU time | 2.1 seconds |
| Started | Oct 14 09:13:40 PM UTC 24 |
| Finished | Oct 14 09:13:43 PM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208131118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.4208131118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke.3484581658 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 11359559 ps |
| CPU time | 1.75 seconds |
| Started | Oct 14 09:13:36 PM UTC 24 |
| Finished | Oct 14 09:13:39 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484581658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-v cs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3484581658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_large_delays.3802673979 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 5001713736 ps |
| CPU time | 15.29 seconds |
| Started | Oct 14 09:13:36 PM UTC 24 |
| Finished | Oct 14 09:13:52 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802673979 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3802673979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_slow_rsp.2573975424 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1510016381 ps |
| CPU time | 9.5 seconds |
| Started | Oct 14 09:13:37 PM UTC 24 |
| Finished | Oct 14 09:13:48 PM UTC 24 |
| Peak memory | 210892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573975424 -assert nopostproc +UVM_TESTNAME=xbar_base_te st +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2573975424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_smoke_zero_delays.3970308214 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 9481936 ps |
| CPU time | 1.52 seconds |
| Started | Oct 14 09:13:36 PM UTC 24 |
| Finished | Oct 14 09:13:39 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970308214 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays.3970308214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all.1312583009 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 264637162 ps |
| CPU time | 24.6 seconds |
| Started | Oct 14 09:13:42 PM UTC 24 |
| Finished | Oct 14 09:14:08 PM UTC 24 |
| Peak memory | 212964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312583009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1312583009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_error.1392031620 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 259183327 ps |
| CPU time | 16.85 seconds |
| Started | Oct 14 09:13:44 PM UTC 24 |
| Finished | Oct 14 09:14:02 PM UTC 24 |
| Peak memory | 210596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392031620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1392031620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_rand_reset.2815186620 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 8605475041 ps |
| CPU time | 104.44 seconds |
| Started | Oct 14 09:13:42 PM UTC 24 |
| Finished | Oct 14 09:15:29 PM UTC 24 |
| Peak memory | 215076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815186620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_rand_reset.2815186620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_stress_all_with_reset_error.3272721575 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 7222574217 ps |
| CPU time | 107.98 seconds |
| Started | Oct 14 09:13:44 PM UTC 24 |
| Finished | Oct 14 09:15:34 PM UTC 24 |
| Peak memory | 214732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272721575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_with_rand_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_reset_error.3272721575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/8.xbar_unmapped_addr.1076149144 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 316866137 ps |
| CPU time | 9.72 seconds |
| Started | Oct 14 09:13:42 PM UTC 24 |
| Finished | Oct 14 09:13:53 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076149144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1076149144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/8.xbar_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device.804923921 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 103393465 ps |
| CPU time | 2.67 seconds |
| Started | Oct 14 09:13:47 PM UTC 24 |
| Finished | Oct 14 09:13:50 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804923921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM _TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xba r_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.804923921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_access_same_device/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_access_same_device_slow_rsp.232672505 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 6737869865 ps |
| CPU time | 17.77 seconds |
| Started | Oct 14 09:13:47 PM UTC 24 |
| Finished | Oct 14 09:14:06 PM UTC 24 |
| Peak memory | 213032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232672505 -assert nopostproc +UVM_TEST NAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device_slow_rsp.232672505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_and_unmapped_addr.1690340435 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 35490851 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 09:13:49 PM UTC 24 |
| Finished | Oct 14 09:13:52 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690340435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_p eri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr.1690340435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_error_random.3144879234 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 734655300 ps |
| CPU time | 11.15 seconds |
| Started | Oct 14 09:13:49 PM UTC 24 |
| Finished | Oct 14 09:14:01 PM UTC 24 |
| Peak memory | 210900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144879234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim -vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3144879234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_error_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random.1556332908 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 532032648 ps |
| CPU time | 9.79 seconds |
| Started | Oct 14 09:13:45 PM UTC 24 |
| Finished | Oct 14 09:13:56 PM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556332908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim- vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random.1556332908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_large_delays.3312920379 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 9722195827 ps |
| CPU time | 46.37 seconds |
| Started | Oct 14 09:13:47 PM UTC 24 |
| Finished | Oct 14 09:14:34 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312920379 -assert nopostproc +UVM _TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3312920379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_random_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_slow_rsp.2390824427 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 6664866249 ps |
| CPU time | 58.01 seconds |
| Started | Oct 14 09:13:47 PM UTC 24 |
| Finished | Oct 14 09:14:46 PM UTC 24 |
| Peak memory | 213012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +max_num_trans=10 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390824427 -assert nopostproc +UVM_TES TNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2390824427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_random_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_random_zero_delays.2562031447 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 37113527 ps |
| CPU time | 4.78 seconds |
| Started | Oct 14 09:13:47 PM UTC 24 |
| Finished | Oct 14 09:13:52 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562031447 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_delays.2562031447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_random_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_same_source.3597841275 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 399389803 ps |
| CPU time | 3.74 seconds |
| Started | Oct 14 09:13:48 PM UTC 24 |
| Finished | Oct 14 09:13:53 PM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597841275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_same_source_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.3597841275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_same_source/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke.24784183 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 9519708 ps |
| CPU time | 1.43 seconds |
| Started | Oct 14 09:13:44 PM UTC 24 |
| Finished | Oct 14 09:13:46 PM UTC 24 |
| Peak memory | 211972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24784183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_ TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs /coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.24784183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_large_delays.1610298559 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 1302145983 ps |
| CPU time | 9.93 seconds |
| Started | Oct 14 09:13:45 PM UTC 24 |
| Finished | Oct 14 09:13:56 PM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device _req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610298559 -assert nopostproc +UVM_TESTNAME=xbar_bas e_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_ peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.1610298559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_smoke_large_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_slow_rsp.749555834 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1117923743 ps |
| CPU time | 11.3 seconds |
| Started | Oct 14 09:13:45 PM UTC 24 |
| Finished | Oct 14 09:13:58 PM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_r eq_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len=2000 +max_device_valid_len=2000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749555834 -assert nopostproc +UVM_TESTNAME=xbar_base_tes t +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.749555834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_smoke_zero_delays.3350824883 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 10432777 ps |
| CPU time | 1.45 seconds |
| Started | Oct 14 09:13:45 PM UTC 24 |
| Finished | Oct 14 09:13:48 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350824883 -assert nopostproc +UVM_TESTNAME=xba r_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ xbar_peri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays.3350824883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_smoke_zero_delays/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all.3832185177 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 19607269767 ps |
| CPU time | 45.52 seconds |
| Started | Oct 14 09:13:49 PM UTC 24 |
| Finished | Oct 14 09:14:36 PM UTC 24 |
| Peak memory | 213024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832185177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri- sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.3832185177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_stress_all_with_error.1942988281 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 22503930876 ps |
| CPU time | 84.82 seconds |
| Started | Oct 14 09:13:52 PM UTC 24 |
| Finished | Oct 14 09:15:18 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942988281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +U VM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri -sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1942988281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_stress_all_with_error/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/coverage/xbar_build_mode/9.xbar_unmapped_addr.1348878136 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2183489912 ps |
| CPU time | 9.14 seconds |
| Started | Oct 14 09:13:49 PM UTC 24 |
| Finished | Oct 14 09:13:59 PM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/xbar_build_mode/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348878136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UV M_TEST_SEQ=xbar_unmapped_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/xbar_pe ri-sim-vcs/coverage/xbar_build_mode.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1348878136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/xbar_peri-sim-vcs/9.xbar_unmapped_addr/latest |
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