Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65417785	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31823695

1

T34

14

T88

7866

T89

7866

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	15662770	1			T34	20		T88	3533		T89	3533
values[0x0]	39718995	1			T34	7		T88	2156		T89	2156
values[0x1]	41859715	1			T34	13		T88	2177		T89	2177

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55659475	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41582005

1

T34

18

T88

7866

T89

7866

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	377745	1			T88	18		T89	18		T90	2
valid_sources[0x01]	363370	1			T88	38		T89	38		T90	6
valid_sources[0x02]	376450	1			T88	20		T89	20		T90	16
valid_sources[0x03]	392200	1			T88	38		T89	38		T2	6
valid_sources[0x04]	366800	1			T88	37		T89	37		T90	11
valid_sources[0x05]	379125	1			T88	21		T89	21		T90	14
valid_sources[0x06]	372710	1			T88	14		T89	14		T90	2
valid_sources[0x07]	376820	1			T88	38		T89	38		T90	3
valid_sources[0x08]	398650	1			T88	12		T89	12		T90	1
valid_sources[0x09]	370260	1			T88	18		T89	18		T90	1
valid_sources[0x0a]	369865	1			T88	29		T89	29		T90	16
valid_sources[0x0b]	370070	1			T88	41		T89	41		T90	3
valid_sources[0x0c]	343890	1			T88	22		T89	22		T90	6
valid_sources[0x0d]	368260	1			T88	23		T89	23		T12	638
valid_sources[0x0e]	384715	1			T88	32		T89	32		T1	1
valid_sources[0x0f]	373385	1			T88	28		T89	28		T90	8
valid_sources[0x10]	368150	1			T88	33		T89	33		T1	6
valid_sources[0x11]	394260	1			T88	28		T89	28		T90	6
valid_sources[0x12]	361130	1			T88	48		T89	48		T90	9
valid_sources[0x13]	386090	1			T88	21		T89	21		T1	3
valid_sources[0x14]	407970	1			T88	45		T89	45		T90	4
valid_sources[0x15]	394935	1			T88	24		T89	24		T90	1
valid_sources[0x16]	358190	1			T88	42		T89	42		T90	3
valid_sources[0x17]	370315	1			T88	36		T89	36		T90	4
valid_sources[0x18]	400995	1			T88	49		T89	49		T90	2
valid_sources[0x19]	381255	1			T88	16		T89	16		T90	2
valid_sources[0x1a]	370895	1			T88	56		T89	56		T90	3
valid_sources[0x1b]	403460	1			T88	36		T89	36		T90	4
valid_sources[0x1c]	374715	1			T88	32		T89	32		T2	8
valid_sources[0x1d]	376365	1			T88	49		T89	49		T90	3
valid_sources[0x1e]	412965	1			T88	22		T89	22		T1	1
valid_sources[0x1f]	399370	1			T88	41		T89	41		T90	8
valid_sources[0x20]	387990	1			T88	23		T89	23		T90	3
valid_sources[0x21]	384805	1			T88	34		T89	34		T90	2
valid_sources[0x22]	387885	1			T88	38		T89	38		T90	8
valid_sources[0x23]	372020	1			T88	19		T89	19		T90	2
valid_sources[0x24]	382925	1			T88	60		T89	60		T90	1
valid_sources[0x25]	381010	1			T88	43		T89	43		T2	5
valid_sources[0x26]	350720	1			T88	17		T89	17		T2	2
valid_sources[0x27]	381210	1			T88	41		T89	41		T90	5
valid_sources[0x28]	388170	1			T88	20		T89	20		T90	16
valid_sources[0x29]	374350	1			T88	21		T89	21		T1	4
valid_sources[0x2a]	386190	1			T88	61		T89	61		T2	4
valid_sources[0x2b]	367510	1			T88	14		T89	14		T90	5
valid_sources[0x2c]	372085	1			T88	18		T89	18		T90	3
valid_sources[0x2d]	358785	1			T88	22		T89	22		T90	2
valid_sources[0x2e]	373125	1			T88	33		T89	33		T90	8
valid_sources[0x2f]	378220	1			T88	22		T89	22		T90	3
valid_sources[0x30]	386235	1			T88	37		T89	37		T90	1
valid_sources[0x31]	378080	1			T88	14		T89	14		T90	2
valid_sources[0x32]	396045	1			T88	11		T89	11		T90	8
valid_sources[0x33]	384325	1			T88	39		T89	39		T90	13
valid_sources[0x34]	379800	1			T88	23		T89	23		T90	3
valid_sources[0x35]	385080	1			T88	55		T89	55		T90	7
valid_sources[0x36]	395160	1			T88	22		T89	22		T90	8
valid_sources[0x37]	372700	1			T88	18		T89	18		T90	12
valid_sources[0x38]	378245	1			T88	61		T89	61		T90	2
valid_sources[0x39]	398110	1			T88	37		T89	37		T90	4
valid_sources[0x3a]	393660	1			T88	42		T89	42		T90	9
valid_sources[0x3b]	386400	1			T88	39		T89	39		T90	7
valid_sources[0x3c]	371120	1			T88	34		T89	34		T90	3
valid_sources[0x3d]	387615	1			T88	65		T89	65		T90	9
valid_sources[0x3e]	381525	1			T88	19		T89	19		T90	6
valid_sources[0x3f]	373620	1			T88	40		T89	40		T90	7
valid_sources[0x40]	384805	1			T88	41		T89	41		T90	2
valid_sources[0x41]	354325	1			T88	34		T89	34		T90	10
valid_sources[0x42]	362095	1			T88	39		T89	39		T90	13
valid_sources[0x43]	380415	1			T88	32		T89	32		T90	7
valid_sources[0x44]	372315	1			T88	45		T89	45		T90	7
valid_sources[0x45]	377490	1			T88	23		T89	23		T90	1
valid_sources[0x46]	410700	1			T88	57		T89	57		T90	1
valid_sources[0x47]	386340	1			T88	19		T89	19		T90	13
valid_sources[0x48]	376205	1			T88	40		T89	40		T90	16
valid_sources[0x49]	348745	1			T34	5		T88	51		T89	51
valid_sources[0x4a]	387685	1			T88	19		T89	19		T90	3
valid_sources[0x4b]	377145	1			T88	8		T89	8		T90	4
valid_sources[0x4c]	375270	1			T88	29		T89	29		T90	2
valid_sources[0x4d]	370840	1			T88	34		T89	34		T90	10
valid_sources[0x4e]	374280	1			T88	18		T89	18		T90	4
valid_sources[0x4f]	359445	1			T88	19		T89	19		T90	2
valid_sources[0x50]	382475	1			T88	19		T89	19		T90	3
valid_sources[0x51]	370270	1			T88	24		T89	24		T90	8
valid_sources[0x52]	360395	1			T88	26		T89	26		T90	4
valid_sources[0x53]	369935	1			T88	26		T89	26		T90	6
valid_sources[0x54]	368830	1			T88	38		T89	38		T90	2
valid_sources[0x55]	373060	1			T88	48		T89	48		T90	4
valid_sources[0x56]	381060	1			T88	41		T89	41		T90	1
valid_sources[0x57]	397490	1			T88	32		T89	32		T2	9
valid_sources[0x58]	363690	1			T88	43		T89	43		T90	10
valid_sources[0x59]	367980	1			T88	51		T89	51		T90	1
valid_sources[0x5a]	370295	1			T88	50		T89	50		T90	7
valid_sources[0x5b]	381700	1			T88	20		T89	20		T90	1
valid_sources[0x5c]	382900	1			T88	39		T89	39		T90	2
valid_sources[0x5d]	376030	1			T88	53		T89	53		T90	8
valid_sources[0x5e]	397685	1			T88	33		T89	33		T90	15
valid_sources[0x5f]	374420	1			T88	25		T89	25		T90	8
valid_sources[0x60]	372555	1			T88	28		T89	28		T90	4
valid_sources[0x61]	375180	1			T88	32		T89	32		T90	1
valid_sources[0x62]	378385	1			T88	30		T89	30		T90	3
valid_sources[0x63]	356900	1			T88	22		T89	22		T90	2
valid_sources[0x64]	381800	1			T88	39		T89	39		T90	12
valid_sources[0x65]	377290	1			T34	10		T88	29		T89	29
valid_sources[0x66]	368835	1			T88	20		T89	20		T90	7
valid_sources[0x67]	375890	1			T88	40		T89	40		T90	6
valid_sources[0x68]	383145	1			T88	38		T89	38		T90	7
valid_sources[0x69]	386070	1			T88	25		T89	25		T90	1
valid_sources[0x6a]	394310	1			T88	17		T89	17		T90	10
valid_sources[0x6b]	369175	1			T88	17		T89	17		T90	16
valid_sources[0x6c]	390450	1			T88	53		T89	53		T90	1
valid_sources[0x6d]	366235	1			T88	23		T89	23		T90	13
valid_sources[0x6e]	371170	1			T88	26		T89	26		T90	5
valid_sources[0x6f]	373085	1			T88	41		T89	41		T90	3
valid_sources[0x70]	385425	1			T88	21		T89	21		T90	1
valid_sources[0x71]	401795	1			T88	16		T89	16		T90	10
valid_sources[0x72]	397165	1			T88	21		T89	21		T1	8
valid_sources[0x73]	354935	1			T88	30		T89	30		T90	12
valid_sources[0x74]	411320	1			T88	54		T89	54		T1	9
valid_sources[0x75]	391195	1			T88	31		T89	31		T90	6
valid_sources[0x76]	379675	1			T88	17		T89	17		T90	9
valid_sources[0x77]	414740	1			T88	35		T89	35		T1	1
valid_sources[0x78]	390545	1			T88	38		T89	38		T90	4
valid_sources[0x79]	379760	1			T88	37		T89	37		T90	9
valid_sources[0x7a]	381385	1			T88	78		T89	78		T90	15
valid_sources[0x7b]	374250	1			T88	41		T89	41		T90	14
valid_sources[0x7c]	375575	1			T88	20		T89	20		T90	3
valid_sources[0x7d]	406195	1			T88	33		T89	33		T90	1
valid_sources[0x7e]	368870	1			T88	10		T89	10		T90	19
valid_sources[0x7f]	362300	1			T34	3		T88	13		T89	13
valid_sources[0x80]	385295	1			T88	20		T89	20		T90	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7704610

1

T34

9

T88

3533

T89

3533

values[0x0]

all_enables

biggest_size

15230720

1

T34

4

T88

2156

T89

2156

values[0x1]

all_enables

biggest_size

8888365

1

T34

1

T88

2177

T89

2177