Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en	100.00	100.00					100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00				100.00		u_alert_handler_lpg_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

SCORE	LINE
100.00	100.00

tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	72885	72885	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	2147483647	2147483647	0	92880
gen_no_flops.OutputDelay_A	2147483647	2147483647	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72885	72885	0	0
T17	113	113	0	0
T18	113	113	0	0
T19	113	113	0	0
T23	113	113	0	0
T24	113	113	0	0
T29	113	113	0	0
T30	113	113	0	0
T32	113	113	0	0
T35	113	113	0	0
T57	113	113	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T17	50539589	50538233	0	0
T18	109307838	109301058	0	0
T19	9170176	9163396	0	0
T23	8857505	8850725	0	0
T24	9170176	9163396	0	0
T29	8857505	8850725	0	0
T30	36925349	36924671	0	0
T32	109307838	109301058	0	0
T35	8857505	8850725	0	0
T57	9191307	9174809	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	92880
T17	21468144	21467376	0	144
T18	46431648	46428624	0	144
T19	3895296	3892272	0	144
T23	3762480	3759456	0	144
T24	3895296	3892272	0	144
T29	3762480	3759456	0	144
T30	15685104	15684768	0	144
T32	46431648	46428624	0	144
T35	3762480	3759456	0	144
T57	3904272	3896976	0	144

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T17	29071445	29070665	0	0
T18	62876190	62872290	0	0
T19	5274880	5270980	0	0
T23	5095025	5091125	0	0
T24	5274880	5270980	0	0
T29	5095025	5091125	0	0
T30	21240245	21239855	0	0
T32	62876190	62872290	0	0
T35	5095025	5091125	0	0
T57	5287035	5277545	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	874973625	874756560	0	1935

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874756560	0	1935
T17	447253	447237	0	3
T18	967326	967263	0	3
T19	81152	81089	0	3
T23	78385	78322	0	3
T24	81152	81089	0	3
T29	78385	78322	0	3
T30	326773	326766	0	3
T32	967326	967263	0	3
T35	78385	78322	0	3
T57	81339	81187	0	3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	645	645	0	0
OutputsKnown_A	874973625	874766355	0	0
gen_no_flops.OutputDelay_A	874973625	874766355	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	645	645	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0
T35	1	1	0	0
T57	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	874766355	0	0
T17	447253	447241	0	0
T18	967326	967266	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	326767	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	81193	0	0