Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	85.19	100.00	88.89				66.67
tb.dut.gen_classes[1].u_accu	85.19	100.00	88.89				66.67
tb.dut.gen_classes[2].u_accu	85.19	100.00	88.89				66.67
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	88.89				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	100.00	88.89	100.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	88.89				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	100.00	88.89	100.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	88.89				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	100.00	88.89	100.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T33,T114,T115
1	1	Covered	T17,T18,T19

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T23

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11000	0	0
DisabledNoTrigBkwd_A	2147483647	562820	0	0
DisabledNoTrigFwd_A	2147483647	1832481480	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11000	0	0
T27	172614	0	0	0
T28	172614	0	0	0
T31	391717	0	0	0
T33	2783	550	0	0
T49	78385	0	0	0
T50	87292	0	0	0
T51	967326	0	0	0
T61	72311	0	0	0
T83	81152	0	0	0
T114	2783	550	0	0
T115	0	550	0	0
T116	0	550	0	0
T117	0	550	0	0
T118	0	550	0	0
T119	0	550	0	0
T120	0	550	0	0
T121	0	550	0	0
T122	0	550	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	562820	0	0
T17	1789012	1509	0	0
T18	3869304	1	0	0
T19	324608	0	0	0
T23	313540	78	0	0
T24	324608	0	0	0
T25	0	414	0	0
T27	0	2267	0	0
T28	0	2256	0	0
T29	313540	78	0	0
T30	1307092	1094	0	0
T31	0	498	0	0
T32	3869304	1	0	0
T35	313540	78	0	0
T47	0	1	0	0
T48	0	78	0	0
T49	0	78	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	0	188	0	0
T53	0	1746	0	0
T54	0	104	0	0
T55	0	104	0	0
T57	325356	0	0	0
T58	0	31	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1832481480	0	0
T17	1789012	914115	0	0
T18	3869304	2686365	0	0
T19	324608	161124	0	0
T23	313540	240582	0	0
T24	324608	161124	0	0
T29	313540	240582	0	0
T30	1307092	382073	0	0
T32	3869304	2686365	0	0
T35	313540	240582	0	0
T57	325356	9269	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T23
1	1	Covered	T17,T19,T23

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Not Covered
1	1	Covered	T17,T19,T23

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T23
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T23,T29

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	874973625	0	0	0
DisabledNoTrigBkwd_A	874973625	111850	0	0
DisabledNoTrigFwd_A	874973625	462798115	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	111850	0	0
T17	447253	926	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	78	0	0
T24	81152	0	0	0
T27	0	11	0	0
T29	78385	78	0	0
T30	326773	372	0	0
T31	0	193	0	0
T32	967326	0	0	0
T35	78385	78	0	0
T48	0	78	0	0
T49	0	78	0	0
T50	0	4	0	0
T57	81339	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	462798115	0	0
T17	447253	132373	0	0
T18	967326	902402	0	0
T19	81152	5604	0	0
T23	78385	5607	0	0
T24	81152	5604	0	0
T29	78385	5607	0	0
T30	326773	7928	0	0
T32	967326	902402	0	0
T35	78385	5607	0	0
T57	81339	2301	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T24
1	1	Covered	T17,T18,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Not Covered
1	1	Covered	T17,T18,T19

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T57

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	874973625	0	0	0
DisabledNoTrigBkwd_A	874973625	200000	0	0
DisabledNoTrigFwd_A	874973625	353937765	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	200000	0	0
T17	447253	169	0	0
T18	967326	1	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	981	0	0
T28	0	981	0	0
T29	78385	0	0	0
T30	326773	1	0	0
T31	0	201	0	0
T32	967326	1	0	0
T35	78385	0	0	0
T47	0	1	0	0
T51	0	1	0	0
T53	0	1746	0	0
T57	81339	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	353937765	0	0
T17	447253	234042	0	0
T18	967326	2020	0	0
T19	81152	72374	0	0
T23	78385	78325	0	0
T24	81152	72374	0	0
T29	78385	78325	0	0
T30	326773	325673	0	0
T32	967326	2020	0	0
T35	78385	78325	0	0
T57	81339	2306	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T57
1	0	Covered	T17,T19,T24
1	1	Covered	T17,T30,T27

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Not Covered
1	1	Covered	T17,T30,T27

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T30,T27
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T30,T27

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	874973625	0	0	0
DisabledNoTrigBkwd_A	874973625	159650	0	0
DisabledNoTrigFwd_A	874973625	481809455	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	159650	0	0
T17	447253	414	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T25	0	414	0	0
T27	0	1275	0	0
T28	0	1275	0	0
T29	78385	0	0	0
T30	326773	721	0	0
T31	0	104	0	0
T32	967326	0	0	0
T35	78385	0	0	0
T52	0	188	0	0
T54	0	104	0	0
T55	0	104	0	0
T57	81339	0	0	0
T58	0	31	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	481809455	0	0
T17	447253	318262	0	0
T18	967326	814677	0	0
T19	81152	81092	0	0
T23	78385	78325	0	0
T24	81152	81092	0	0
T29	78385	78325	0	0
T30	326773	19165	0	0
T32	967326	814677	0	0
T35	78385	78325	0	0
T57	81339	2322	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T24
1	0	Covered	T17,T18,T32
1	1	Covered	T17,T19,T24

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T33,T114,T115
1	1	Covered	T17,T19,T24

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T24
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T30,T33

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	874973625	11000	0	0
DisabledNoTrigBkwd_A	874973625	91320	0	0
DisabledNoTrigFwd_A	874973625	533936145	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	11000	0	0
T27	172614	0	0	0
T28	172614	0	0	0
T31	391717	0	0	0
T33	2783	550	0	0
T49	78385	0	0	0
T50	87292	0	0	0
T51	967326	0	0	0
T61	72311	0	0	0
T83	81152	0	0	0
T114	2783	550	0	0
T115	0	550	0	0
T116	0	550	0	0
T117	0	550	0	0
T118	0	550	0	0
T119	0	550	0	0
T120	0	550	0	0
T121	0	550	0	0
T122	0	550	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	91320	0	0
T17	447253	589	0	0
T18	967326	0	0	0
T19	81152	0	0	0
T23	78385	0	0	0
T24	81152	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	78385	0	0	0
T30	326773	731	0	0
T31	0	230	0	0
T32	967326	0	0	0
T33	0	6	0	0
T35	78385	0	0	0
T52	0	26	0	0
T54	0	230	0	0
T55	0	230	0	0
T57	81339	0	0	0
T58	0	42	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	533936145	0	0
T17	447253	229438	0	0
T18	967326	967266	0	0
T19	81152	2054	0	0
T23	78385	78325	0	0
T24	81152	2054	0	0
T29	78385	78325	0	0
T30	326773	29307	0	0
T32	967326	967266	0	0
T35	78385	78325	0	0
T57	81339	2340	0	0