Module Definition
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Module : alert_handler_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.00 100.00 96.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg_wrap.u_reg 99.00 100.00 96.00 100.00 100.00

Line Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
TOTAL22282228100.00
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CONT_ASSIGN1693711100.00
CONT_ASSIGN1693811100.00
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CONT_ASSIGN1694111100.00
CONT_ASSIGN1694211100.00
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CONT_ASSIGN1694711100.00
CONT_ASSIGN1694911100.00
CONT_ASSIGN1695011100.00
CONT_ASSIGN1695111100.00
CONT_ASSIGN1695311100.00
CONT_ASSIGN1695411100.00
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CONT_ASSIGN1697011100.00
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CONT_ASSIGN1699011100.00
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CONT_ASSIGN1703011100.00
CONT_ASSIGN1703111100.00
CONT_ASSIGN1703311100.00
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CONT_ASSIGN1704011100.00
CONT_ASSIGN1704211100.00
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CONT_ASSIGN1706011100.00
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CONT_ASSIGN1706411100.00
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CONT_ASSIGN1707011100.00
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CONT_ASSIGN1707511100.00
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CONT_ASSIGN1707811100.00
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CONT_ASSIGN1708211100.00
CONT_ASSIGN1708411100.00
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CONT_ASSIGN1708711100.00
CONT_ASSIGN1708811100.00
CONT_ASSIGN1709011100.00
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CONT_ASSIGN1715011100.00
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CONT_ASSIGN1718011100.00
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CONT_ASSIGN1719011100.00
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CONT_ASSIGN1721111100.00
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CONT_ASSIGN1722211100.00
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CONT_ASSIGN1747111100.00
CONT_ASSIGN1747311100.00
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CONT_ASSIGN1748011100.00
CONT_ASSIGN1748111100.00
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CONT_ASSIGN1749111100.00
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CONT_ASSIGN1750211100.00
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CONT_ASSIGN1750911100.00
CONT_ASSIGN1751011100.00
CONT_ASSIGN1751111100.00
CONT_ASSIGN1751311100.00
CONT_ASSIGN1751411100.00
CONT_ASSIGN1751511100.00
CONT_ASSIGN1751611100.00
CONT_ASSIGN1751811100.00
CONT_ASSIGN1751911100.00
CONT_ASSIGN1752011100.00
CONT_ASSIGN1752211100.00
CONT_ASSIGN1752411100.00
CONT_ASSIGN1752611100.00
CONT_ASSIGN1752811100.00
CONT_ASSIGN1753011100.00
CONT_ASSIGN1753211100.00
CONT_ASSIGN1753411100.00
CONT_ASSIGN1753611100.00
CONT_ASSIGN1753811100.00
CONT_ASSIGN1754011100.00
CONT_ASSIGN1754111100.00
CONT_ASSIGN1754311100.00
CONT_ASSIGN1754411100.00
CONT_ASSIGN1754511100.00
CONT_ASSIGN1754711100.00
CONT_ASSIGN1754811100.00
CONT_ASSIGN1754911100.00
CONT_ASSIGN1755011100.00
CONT_ASSIGN1755211100.00
CONT_ASSIGN1755311100.00
CONT_ASSIGN1755411100.00
CONT_ASSIGN1755611100.00
CONT_ASSIGN1755711100.00
CONT_ASSIGN1755811100.00
CONT_ASSIGN1756011100.00
CONT_ASSIGN1756111100.00
CONT_ASSIGN1756211100.00
CONT_ASSIGN1756411100.00
CONT_ASSIGN1756511100.00
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CONT_ASSIGN1756811100.00
CONT_ASSIGN1756911100.00
CONT_ASSIGN1757011100.00
CONT_ASSIGN1757211100.00
CONT_ASSIGN1757311100.00
CONT_ASSIGN1757411100.00
CONT_ASSIGN1757611100.00
CONT_ASSIGN1757711100.00
CONT_ASSIGN1757811100.00
ALWAYS17582351351100.00
ALWAYS17937397397100.00
ALWAYS1939533100.00
ALWAYS1940333100.00
CONT_ASSIGN1941111100.00
CONT_ASSIGN1941411100.00
CONT_ASSIGN1963411100.00
CONT_ASSIGN1985611100.00
CONT_ASSIGN1986411100.00
CONT_ASSIGN1986511100.00

Click here to see the source line report.

Cond Coverage for Module : alert_handler_reg_top
TotalCoveredPercent
Conditions4802461096.00
Logical4802461096.00
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
65-7605100.00
7646-15418100.00
15458-15695100.00
15696-15823100.00
15824-15927100.00
15927100.00
15927100.00
15927100.00
15927-1634399.29
16346-1654696.92
16547-1670287.82
16703-1685887.50
16859-1701587.66
17018-1722398.61
17226-1742890.26
17431-1941186.81

Branch Coverage for Module : alert_handler_reg_top
Line No.TotalCoveredPercent
Branches 360 360 100.00
TERNARY 15923 2 2 100.00
IF 75 3 3 100.00
CASE 17938 351 351 100.00
IF 19395 2 2 100.00
IF 19403 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_alert_handler_reg_0.1/rtl/alert_handler_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 15923 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T34,T88,T89
0 Covered T34,T88,T89


LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 77 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T34,T88,T89
0 1 Covered T6,T7,T94
0 0 Covered T34,T88,T89


LineNo. Expression -1-: 17938 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T34,T88,T89
addr_hit[1] Covered T34,T88,T89
addr_hit[2] Covered T34,T88,T89
addr_hit[3] Covered T88,T89,T90
addr_hit[4] Covered T88,T89,T90
addr_hit[5] Covered T88,T89,T90
addr_hit[6] Covered T88,T89,T90
addr_hit[7] Covered T34,T88,T89
addr_hit[8] Covered T88,T89,T90
addr_hit[9] Covered T88,T89,T90
addr_hit[10] Covered T88,T89,T90
addr_hit[11] Covered T88,T89,T90
addr_hit[12] Covered T88,T89,T90
addr_hit[13] Covered T88,T89,T90
addr_hit[14] Covered T88,T89,T90
addr_hit[15] Covered T88,T89,T90
addr_hit[16] Covered T88,T89,T90
addr_hit[17] Covered T88,T89,T90
addr_hit[18] Covered T88,T89,T90
addr_hit[19] Covered T88,T89,T90
addr_hit[20] Covered T88,T89,T90
addr_hit[21] Covered T88,T89,T90
addr_hit[22] Covered T88,T89,T90
addr_hit[23] Covered T88,T89,T90
addr_hit[24] Covered T88,T89,T90
addr_hit[25] Covered T88,T89,T90
addr_hit[26] Covered T88,T89,T90
addr_hit[27] Covered T88,T89,T90
addr_hit[28] Covered T88,T89,T90
addr_hit[29] Covered T88,T89,T90
addr_hit[30] Covered T88,T89,T90
addr_hit[31] Covered T88,T89,T90
addr_hit[32] Covered T88,T89,T90
addr_hit[33] Covered T88,T89,T90
addr_hit[34] Covered T88,T89,T90
addr_hit[35] Covered T88,T89,T90
addr_hit[36] Covered T88,T89,T90
addr_hit[37] Covered T88,T89,T90
addr_hit[38] Covered T34,T88,T89
addr_hit[39] Covered T88,T89,T90
addr_hit[40] Covered T88,T89,T90
addr_hit[41] Covered T88,T89,T90
addr_hit[42] Covered T88,T89,T90
addr_hit[43] Covered T88,T89,T90
addr_hit[44] Covered T88,T89,T90
addr_hit[45] Covered T88,T89,T90
addr_hit[46] Covered T88,T89,T90
addr_hit[47] Covered T88,T89,T90
addr_hit[48] Covered T88,T89,T90
addr_hit[49] Covered T88,T89,T90
addr_hit[50] Covered T88,T89,T90
addr_hit[51] Covered T88,T89,T90
addr_hit[52] Covered T34,T88,T89
addr_hit[53] Covered T88,T89,T90
addr_hit[54] Covered T88,T89,T90
addr_hit[55] Covered T88,T89,T90
addr_hit[56] Covered T88,T89,T90
addr_hit[57] Covered T88,T89,T90
addr_hit[58] Covered T88,T89,T90
addr_hit[59] Covered T88,T89,T90
addr_hit[60] Covered T34,T88,T89
addr_hit[61] Covered T88,T89,T90
addr_hit[62] Covered T88,T89,T90
addr_hit[63] Covered T88,T89,T90
addr_hit[64] Covered T88,T89,T90
addr_hit[65] Covered T34,T88,T89
addr_hit[66] Covered T88,T89,T90
addr_hit[67] Covered T88,T89,T90
addr_hit[68] Covered T88,T89,T90
addr_hit[69] Covered T88,T89,T90
addr_hit[70] Covered T88,T89,T90
addr_hit[71] Covered T88,T89,T90
addr_hit[72] Covered T88,T89,T90
addr_hit[73] Covered T34,T88,T89
addr_hit[74] Covered T88,T89,T90
addr_hit[75] Covered T88,T89,T90
addr_hit[76] Covered T34,T88,T89
addr_hit[77] Covered T88,T89,T90
addr_hit[78] Covered T88,T89,T90
addr_hit[79] Covered T88,T89,T90
addr_hit[80] Covered T34,T88,T89
addr_hit[81] Covered T88,T89,T90
addr_hit[82] Covered T88,T89,T90
addr_hit[83] Covered T88,T89,T90
addr_hit[84] Covered T88,T89,T90
addr_hit[85] Covered T88,T89,T90
addr_hit[86] Covered T88,T89,T90
addr_hit[87] Covered T88,T89,T90
addr_hit[88] Covered T34,T88,T89
addr_hit[89] Covered T88,T89,T90
addr_hit[90] Covered T88,T89,T90
addr_hit[91] Covered T88,T89,T90
addr_hit[92] Covered T88,T89,T90
addr_hit[93] Covered T88,T89,T90
addr_hit[94] Covered T88,T89,T90
addr_hit[95] Covered T34,T88,T89
addr_hit[96] Covered T88,T89,T90
addr_hit[97] Covered T88,T89,T90
addr_hit[98] Covered T88,T89,T90
addr_hit[99] Covered T88,T89,T90
addr_hit[100] Covered T88,T89,T90
addr_hit[101] Covered T88,T89,T90
addr_hit[102] Covered T88,T89,T90
addr_hit[103] Covered T88,T89,T90
addr_hit[104] Covered T34,T88,T89
addr_hit[105] Covered T88,T89,T90
addr_hit[106] Covered T88,T89,T90
addr_hit[107] Covered T88,T89,T90
addr_hit[108] Covered T88,T89,T90
addr_hit[109] Covered T88,T89,T90
addr_hit[110] Covered T88,T89,T90
addr_hit[111] Covered T88,T89,T90
addr_hit[112] Covered T88,T89,T90
addr_hit[113] Covered T88,T89,T90
addr_hit[114] Covered T88,T89,T90
addr_hit[115] Covered T88,T89,T90
addr_hit[116] Covered T88,T89,T90
addr_hit[117] Covered T88,T89,T90
addr_hit[118] Covered T88,T89,T1
addr_hit[119] Covered T88,T89,T90
addr_hit[120] Covered T88,T89,T1
addr_hit[121] Covered T88,T89,T90
addr_hit[122] Covered T88,T89,T90
addr_hit[123] Covered T88,T89,T90
addr_hit[124] Covered T88,T89,T90
addr_hit[125] Covered T88,T89,T90
addr_hit[126] Covered T88,T89,T90
addr_hit[127] Covered T88,T89,T90
addr_hit[128] Covered T88,T89,T90
addr_hit[129] Covered T88,T89,T90
addr_hit[130] Covered T88,T89,T90
addr_hit[131] Covered T88,T89,T90
addr_hit[132] Covered T88,T89,T90
addr_hit[133] Covered T88,T89,T90
addr_hit[134] Covered T88,T89,T90
addr_hit[135] Covered T88,T89,T90
addr_hit[136] Covered T88,T89,T90
addr_hit[137] Covered T88,T89,T90
addr_hit[138] Covered T88,T89,T90
addr_hit[139] Covered T88,T89,T90
addr_hit[140] Covered T88,T89,T90
addr_hit[141] Covered T88,T89,T90
addr_hit[142] Covered T88,T89,T90
addr_hit[143] Covered T88,T89,T90
addr_hit[144] Covered T88,T89,T90
addr_hit[145] Covered T88,T89,T90
addr_hit[146] Covered T88,T89,T90
addr_hit[147] Covered T34,T88,T89
addr_hit[148] Covered T88,T89,T90
addr_hit[149] Covered T88,T89,T90
addr_hit[150] Covered T88,T89,T90
addr_hit[151] Covered T88,T89,T90
addr_hit[152] Covered T88,T89,T90
addr_hit[153] Covered T88,T89,T90
addr_hit[154] Covered T88,T89,T90
addr_hit[155] Covered T88,T89,T90
addr_hit[156] Covered T88,T89,T90
addr_hit[157] Covered T88,T89,T90
addr_hit[158] Covered T88,T89,T90
addr_hit[159] Covered T88,T89,T90
addr_hit[160] Covered T88,T89,T90
addr_hit[161] Covered T34,T88,T89
addr_hit[162] Covered T88,T89,T90
addr_hit[163] Covered T88,T89,T90
addr_hit[164] Covered T88,T89,T90
addr_hit[165] Covered T88,T89,T90
addr_hit[166] Covered T88,T89,T90
addr_hit[167] Covered T88,T89,T90
addr_hit[168] Covered T34,T88,T89
addr_hit[169] Covered T88,T89,T90
addr_hit[170] Covered T88,T89,T90
addr_hit[171] Covered T34,T88,T89
addr_hit[172] Covered T88,T89,T90
addr_hit[173] Covered T34,T88,T89
addr_hit[174] Covered T88,T89,T90
addr_hit[175] Covered T88,T89,T90
addr_hit[176] Covered T88,T89,T90
addr_hit[177] Covered T88,T89,T90
addr_hit[178] Covered T88,T89,T90
addr_hit[179] Covered T88,T89,T90
addr_hit[180] Covered T88,T89,T90
addr_hit[181] Covered T88,T89,T90
addr_hit[182] Covered T88,T89,T90
addr_hit[183] Covered T88,T89,T90
addr_hit[184] Covered T88,T89,T90
addr_hit[185] Covered T88,T89,T90
addr_hit[186] Covered T88,T89,T90
addr_hit[187] Covered T88,T89,T90
addr_hit[188] Covered T88,T89,T90
addr_hit[189] Covered T88,T89,T90
addr_hit[190] Covered T88,T89,T90
addr_hit[191] Covered T88,T89,T90
addr_hit[192] Covered T88,T89,T90
addr_hit[193] Covered T88,T89,T90
addr_hit[194] Covered T88,T89,T90
addr_hit[195] Covered T88,T89,T90
addr_hit[196] Covered T88,T89,T90
addr_hit[197] Covered T34,T88,T89
addr_hit[198] Covered T88,T89,T90
addr_hit[199] Covered T34,T88,T89
addr_hit[200] Covered T88,T89,T90
addr_hit[201] Covered T88,T89,T90
addr_hit[202] Covered T88,T89,T90
addr_hit[203] Covered T88,T89,T90
addr_hit[204] Covered T88,T89,T90
addr_hit[205] Covered T88,T89,T90
addr_hit[206] Covered T88,T89,T90
addr_hit[207] Covered T88,T89,T90
addr_hit[208] Covered T88,T89,T90
addr_hit[209] Covered T88,T89,T90
addr_hit[210] Covered T88,T89,T90
addr_hit[211] Covered T88,T89,T90
addr_hit[212] Covered T88,T89,T90
addr_hit[213] Covered T88,T89,T90
addr_hit[214] Covered T88,T89,T90
addr_hit[215] Covered T88,T89,T90
addr_hit[216] Covered T88,T89,T90
addr_hit[217] Covered T34,T88,T89
addr_hit[218] Covered T88,T89,T90
addr_hit[219] Covered T88,T89,T90
addr_hit[220] Covered T88,T89,T90
addr_hit[221] Covered T88,T89,T90
addr_hit[222] Covered T34,T88,T89
addr_hit[223] Covered T88,T89,T90
addr_hit[224] Covered T88,T89,T90
addr_hit[225] Covered T88,T89,T90
addr_hit[226] Covered T88,T89,T90
addr_hit[227] Covered T88,T89,T90
addr_hit[228] Covered T88,T89,T90
addr_hit[229] Covered T88,T89,T90
addr_hit[230] Covered T88,T89,T90
addr_hit[231] Covered T88,T89,T90
addr_hit[232] Covered T88,T89,T90
addr_hit[233] Covered T88,T89,T90
addr_hit[234] Covered T88,T89,T90
addr_hit[235] Covered T88,T89,T90
addr_hit[236] Covered T88,T89,T90
addr_hit[237] Covered T88,T89,T90
addr_hit[238] Covered T88,T89,T90
addr_hit[239] Covered T88,T89,T90
addr_hit[240] Covered T88,T89,T90
addr_hit[241] Covered T88,T89,T90
addr_hit[242] Covered T88,T89,T90
addr_hit[243] Covered T88,T89,T90
addr_hit[244] Covered T88,T89,T90
addr_hit[245] Covered T88,T89,T90
addr_hit[246] Covered T88,T89,T90
addr_hit[247] Covered T88,T89,T90
addr_hit[248] Covered T88,T89,T90
addr_hit[249] Covered T88,T89,T90
addr_hit[250] Covered T88,T89,T90
addr_hit[251] Covered T88,T89,T90
addr_hit[252] Covered T88,T89,T90
addr_hit[253] Covered T88,T89,T90
addr_hit[254] Covered T88,T89,T90
addr_hit[255] Covered T34,T88,T89
addr_hit[256] Covered T88,T89,T90
addr_hit[257] Covered T88,T89,T90
addr_hit[258] Covered T88,T89,T90
addr_hit[259] Covered T88,T89,T90
addr_hit[260] Covered T88,T89,T90
addr_hit[261] Covered T88,T89,T90
addr_hit[262] Covered T88,T89,T90
addr_hit[263] Covered T88,T89,T90
addr_hit[264] Covered T88,T89,T90
addr_hit[265] Covered T34,T88,T89
addr_hit[266] Covered T88,T89,T90
addr_hit[267] Covered T88,T89,T90
addr_hit[268] Covered T88,T89,T90
addr_hit[269] Covered T88,T89,T90
addr_hit[270] Covered T88,T89,T90
addr_hit[271] Covered T88,T89,T90
addr_hit[272] Covered T88,T89,T90
addr_hit[273] Covered T88,T89,T90
addr_hit[274] Covered T88,T89,T90
addr_hit[275] Covered T88,T89,T90
addr_hit[276] Covered T88,T89,T90
addr_hit[277] Covered T88,T89,T90
addr_hit[278] Covered T88,T89,T90
addr_hit[279] Covered T88,T89,T90
addr_hit[280] Covered T88,T89,T90
addr_hit[281] Covered T88,T89,T90
addr_hit[282] Covered T88,T89,T90
addr_hit[283] Covered T88,T89,T90
addr_hit[284] Covered T88,T89,T90
addr_hit[285] Covered T88,T89,T90
addr_hit[286] Covered T88,T89,T90
addr_hit[287] Covered T88,T89,T90
addr_hit[288] Covered T88,T89,T90
addr_hit[289] Covered T88,T89,T90
addr_hit[290] Covered T88,T89,T90
addr_hit[291] Covered T88,T89,T90
addr_hit[292] Covered T88,T89,T90
addr_hit[293] Covered T88,T89,T90
addr_hit[294] Covered T88,T89,T90
addr_hit[295] Covered T88,T89,T90
addr_hit[296] Covered T88,T89,T90
addr_hit[297] Covered T88,T89,T90
addr_hit[298] Covered T88,T89,T90
addr_hit[299] Covered T88,T89,T90
addr_hit[300] Covered T88,T89,T90
addr_hit[301] Covered T88,T89,T90
addr_hit[302] Covered T88,T89,T90
addr_hit[303] Covered T88,T89,T90
addr_hit[304] Covered T88,T89,T90
addr_hit[305] Covered T88,T89,T90
addr_hit[306] Covered T88,T89,T90
addr_hit[307] Covered T88,T89,T90
addr_hit[308] Covered T88,T89,T90
addr_hit[309] Covered T88,T89,T90
addr_hit[310] Covered T88,T89,T90
addr_hit[311] Covered T88,T89,T90
addr_hit[312] Covered T88,T89,T90
addr_hit[313] Covered T88,T89,T90
addr_hit[314] Covered T88,T89,T90
addr_hit[315] Covered T88,T89,T90
addr_hit[316] Covered T34,T88,T89
addr_hit[317] Covered T88,T89,T90
addr_hit[318] Covered T88,T89,T90
addr_hit[319] Covered T88,T89,T90
addr_hit[320] Covered T88,T89,T90
addr_hit[321] Covered T88,T89,T90
addr_hit[322] Covered T88,T89,T90
addr_hit[323] Covered T88,T89,T90
addr_hit[324] Covered T88,T89,T90
addr_hit[325] Covered T88,T89,T90
addr_hit[326] Covered T88,T89,T90
addr_hit[327] Covered T88,T89,T90
addr_hit[328] Covered T88,T89,T90
addr_hit[329] Covered T88,T89,T90
addr_hit[330] Covered T88,T89,T90
addr_hit[331] Covered T88,T89,T90
addr_hit[332] Covered T88,T89,T90
addr_hit[333] Covered T88,T89,T90
addr_hit[334] Covered T88,T89,T90
addr_hit[335] Covered T88,T89,T90
addr_hit[336] Covered T88,T89,T90
addr_hit[337] Covered T88,T89,T90
addr_hit[338] Covered T88,T89,T90
addr_hit[339] Covered T88,T89,T90
addr_hit[340] Covered T88,T89,T90
addr_hit[341] Covered T34,T88,T89
addr_hit[342] Covered T88,T89,T90
addr_hit[343] Covered T88,T89,T90
addr_hit[344] Covered T88,T89,T90
addr_hit[345] Covered T88,T89,T90
addr_hit[346] Covered T88,T89,T90
addr_hit[347] Covered T88,T89,T90
addr_hit[348] Covered T88,T89,T90
addr_hit[349] Covered T88,T89,T90
default Covered T34,T88,T89


LineNo. Expression -1-: 19395 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T34,T88,T89
0 Covered T34,T88,T89


LineNo. Expression -1-: 19403 if ((!rst_shadowed_ni))

Branches:
-1-StatusTests
1 Covered T34,T88,T89
0 Covered T34,T88,T89


Assert Coverage for Module : alert_handler_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 915916640 95306660 0 0
reAfterRv 915916640 95306660 0 0
rePulse 915916640 15180640 0 0
wePulse 915916640 80126020 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 915916640 95306660 0 0
T1 6197 710 0 0
T2 22835 428 0 0
T3 6197 710 0 0
T11 9081 1360 0 0
T12 123308 196126 0 0
T13 590 40 0 0
T34 590 40 0 0
T88 48603 7866 0 0
T89 48603 7866 0 0
T90 9081 1360 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 915916640 95306660 0 0
T1 6197 710 0 0
T2 22835 428 0 0
T3 6197 710 0 0
T11 9081 1360 0 0
T12 123308 196126 0 0
T13 590 40 0 0
T34 590 40 0 0
T88 48603 7866 0 0
T89 48603 7866 0 0
T90 9081 1360 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 915916640 15180640 0 0
T1 6197 702 0 0
T2 22835 14 0 0
T3 6197 702 0 0
T11 9081 560 0 0
T12 123308 114911 0 0
T13 590 20 0 0
T34 590 20 0 0
T88 48603 3533 0 0
T89 48603 3533 0 0
T90 9081 560 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 915916640 80126020 0 0
T1 6197 8 0 0
T2 22835 414 0 0
T3 6197 8 0 0
T11 9081 800 0 0
T12 123308 81215 0 0
T13 590 20 0 0
T34 590 20 0 0
T88 48603 4333 0 0
T89 48603 4333 0 0
T90 9081 800 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%