Unified Coverage Report :: Module :: prim_alert_receiver

Module : prim_alert_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_alerts[0].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[1].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[2].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[3].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[5].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[6].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[7].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[9].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[11].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[12].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[14].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[15].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[18].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[19].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[22].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[24].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[25].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[27].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[28].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[30].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[34].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[38].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[40].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[41].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[42].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[46].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[47].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[48].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[54].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[58].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[59].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[60].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[62].u_alert_receiver	93.75			93.75
tb.dut.gen_alerts[4].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[8].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[10].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[13].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[16].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[17].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[20].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[21].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[23].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[26].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[29].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[31].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[32].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[33].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[35].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[36].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[37].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[39].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[43].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[44].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[45].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[49].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[50].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[51].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[52].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[53].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[55].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[56].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[57].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[61].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[63].u_alert_receiver	100.00			100.00
tb.dut.gen_alerts[64].u_alert_receiver	100.00			100.00

---

Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75			93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	INPUT
ping_ok_o	Yes	Yes	T17,T57,T30	Yes	T17,T57,T30	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T18,T57,T32	Yes	T17,T57,T30	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T57,T30	Yes	T18,T57,T32	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T18,T57,T32	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T18,T57,T32	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T18,T57,T32	Yes	T57,T30,T86	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T30,T86	Yes	T18,T57,T32	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	INPUT
ping_ok_o	Yes	Yes	T17,T57,T30	Yes	T17,T57,T30	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T18,T57	Yes	T17,T57,T27	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T57,T27	Yes	T17,T18,T57	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T27,T28	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T27,T28	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T53,T107	Yes	T57,T53,T107	INPUT
ping_ok_o	Yes	Yes	T57,T53,T107	Yes	T57,T53,T107	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T53,T107	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T53,T107	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	INPUT
ping_ok_o	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T18,T57,T32	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T18,T57,T32	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	INPUT
ping_ok_o	Yes	Yes	T17,T57,T27	Yes	T17,T57,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T18,T57	Yes	T17,T57,T25	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T57,T25	Yes	T17,T18,T57	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	INPUT
ping_ok_o	Yes	Yes	T17,T57,T30	Yes	T17,T57,T30	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T18,T57	Yes	T17,T57,T25	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T57,T25	Yes	T17,T18,T57	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	INPUT
ping_ok_o	Yes	Yes	T17,T57,T30	Yes	T17,T57,T30	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T53	Yes	T57,T30,T53	INPUT
ping_ok_o	Yes	Yes	T57,T30,T53	Yes	T57,T30,T53	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T53,T107	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T53,T107	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T53	Yes	T57,T30,T53	INPUT
ping_ok_o	Yes	Yes	T57,T30,T53	Yes	T57,T30,T53	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T53,T107	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T53,T107	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	INPUT
ping_ok_o	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver

	Total	Covered	Percent
Totals	13	12	92.31
Total Bits	32	30	93.75
Total Bits 0->1	16	15	93.75
Total Bits 1->0	16	15	93.75

Ports	13	12	92.31
Port Bits	32	30	93.75
Port Bits 0->1	16	15	93.75
Port Bits 1->0	16	15	93.75

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	No	No		No		OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	INPUT
ping_ok_o	Yes	Yes	T17,T57,T27	Yes	T17,T57,T27	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T18,T57	Yes	T17,T57,T25	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T57,T25	Yes	T17,T18,T57	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T53	Yes	T57,T30,T53	INPUT
ping_ok_o	Yes	Yes	T57,T30,T53	Yes	T57,T30,T53	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T30,T53	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T30,T53	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T18,T57,T32	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T18,T57,T32	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	INPUT
ping_ok_o	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	INPUT
ping_ok_o	Yes	Yes	T57,T30,T86	Yes	T57,T30,T86	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T53,T107	Yes	T57,T53,T107	INPUT
ping_ok_o	Yes	Yes	T57,T53,T107	Yes	T57,T53,T107	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T53,T107	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T53,T107	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T27,T28	Yes	T57,T27,T28	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T30,T27	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T30,T27	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	INPUT
ping_ok_o	Yes	Yes	T17,T57,T30	Yes	T17,T57,T30	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T18,T57	Yes	T17,T57,T25	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T57,T25	Yes	T17,T18,T57	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T53,T107	Yes	T57,T53,T107	INPUT
ping_ok_o	Yes	Yes	T57,T53,T107	Yes	T57,T53,T107	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T53,T107	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T53,T107	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T57,T25	Yes	T17,T57,T25	INPUT
ping_ok_o	Yes	Yes	T17,T57,T25	Yes	T17,T57,T25	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T57,T25	Yes	T17,T57,T25	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T57,T25	Yes	T17,T57,T25	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	INPUT
ping_ok_o	Yes	Yes	T57,T30,T27	Yes	T57,T30,T27	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T30,T53	Yes	T57,T30,T53	INPUT
ping_ok_o	Yes	Yes	T57,T53,T107	Yes	T57,T53,T107	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T30,T53	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T30,T53	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T27,T28	Yes	T57,T27,T28	INPUT
ping_ok_o	Yes	Yes	T57,T27,T28	Yes	T57,T27,T28	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T27,T28	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T27,T28	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	INPUT
ping_ok_o	Yes	Yes	T17,T57,T30	Yes	T17,T57,T30	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T17,T18,T57	Yes	T17,T18,T57	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T18,T57,T32	Yes	T18,T57,T32	INPUT
ping_ok_o	Yes	Yes	T57,T27,T28	Yes	T57,T27,T28	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T18,T57,T32	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T18,T57,T32	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver

	Total	Covered	Percent
Totals	13	13	100.00
Total Bits	32	32	100.00
Total Bits 0->1	16	16	100.00
Total Bits 1->0	16	16	100.00

Ports	13	13	100.00
Port Bits	32	32	100.00
Port Bits 0->1	16	16	100.00
Port Bits 1->0	16	16	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T17,T57,T25	Yes	T17,T18,T19	INPUT
init_trig_i[3:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
ping_req_i	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	INPUT
ping_ok_o	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
integ_fail_o	Yes	Yes	T17,T27,T28	Yes	T17,T27,T28	OUTPUT
alert_o	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_rx_o.ack_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	OUTPUT
alert_rx_o.ping_n	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_rx_o.ping_p	Yes	Yes	T57,T113,T40	Yes	T57,T113,T40	OUTPUT
alert_tx_i.alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_tx_i.alert_p	Yes	Yes	T17,T19,T23	Yes	T17,T19,T23	INPUT