Unified Coverage Report :: Module :: alert_handler_csr_assert_fpv

Module : alert_handler_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.27						1.27

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_alert_handler_csr_assert_0/alert_handler_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.alert_handler_csr_assert	1.27						1.27

---

Module Instance : tb.dut.alert_handler_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.27						1.27

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.27						1.27

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : alert_handler_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	79	79	100.00	1	1.27
Cover properties	0	0		0
Cover sequences	0	0		0
Total	79	79	100.00	1	1.27

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	915916640	3203030	0	0
alert_regwen_0_rd_A	915916640	0	0	0
alert_regwen_10_rd_A	915916640	0	0	0
alert_regwen_11_rd_A	915916640	0	0	0
alert_regwen_12_rd_A	915916640	0	0	0
alert_regwen_13_rd_A	915916640	0	0	0
alert_regwen_14_rd_A	915916640	0	0	0
alert_regwen_15_rd_A	915916640	0	0	0
alert_regwen_16_rd_A	915916640	0	0	0
alert_regwen_17_rd_A	915916640	0	0	0
alert_regwen_18_rd_A	915916640	0	0	0
alert_regwen_19_rd_A	915916640	0	0	0
alert_regwen_1_rd_A	915916640	0	0	0
alert_regwen_20_rd_A	915916640	0	0	0
alert_regwen_21_rd_A	915916640	0	0	0
alert_regwen_22_rd_A	915916640	0	0	0
alert_regwen_23_rd_A	915916640	0	0	0
alert_regwen_24_rd_A	915916640	0	0	0
alert_regwen_25_rd_A	915916640	0	0	0
alert_regwen_26_rd_A	915916640	0	0	0
alert_regwen_27_rd_A	915916640	0	0	0
alert_regwen_28_rd_A	915916640	0	0	0
alert_regwen_29_rd_A	915916640	0	0	0
alert_regwen_2_rd_A	915916640	0	0	0
alert_regwen_30_rd_A	915916640	0	0	0
alert_regwen_31_rd_A	915916640	0	0	0
alert_regwen_32_rd_A	915916640	0	0	0
alert_regwen_33_rd_A	915916640	0	0	0
alert_regwen_34_rd_A	915916640	0	0	0
alert_regwen_35_rd_A	915916640	0	0	0
alert_regwen_36_rd_A	915916640	0	0	0
alert_regwen_37_rd_A	915916640	0	0	0
alert_regwen_38_rd_A	915916640	0	0	0
alert_regwen_39_rd_A	915916640	0	0	0
alert_regwen_3_rd_A	915916640	0	0	0
alert_regwen_40_rd_A	915916640	0	0	0
alert_regwen_41_rd_A	915916640	0	0	0
alert_regwen_42_rd_A	915916640	0	0	0
alert_regwen_43_rd_A	915916640	0	0	0
alert_regwen_44_rd_A	915916640	0	0	0
alert_regwen_45_rd_A	915916640	0	0	0
alert_regwen_46_rd_A	915916640	0	0	0
alert_regwen_47_rd_A	915916640	0	0	0
alert_regwen_48_rd_A	915916640	0	0	0
alert_regwen_49_rd_A	915916640	0	0	0
alert_regwen_4_rd_A	915916640	0	0	0
alert_regwen_50_rd_A	915916640	0	0	0
alert_regwen_51_rd_A	915916640	0	0	0
alert_regwen_52_rd_A	915916640	0	0	0
alert_regwen_53_rd_A	915916640	0	0	0
alert_regwen_54_rd_A	915916640	0	0	0
alert_regwen_55_rd_A	915916640	0	0	0
alert_regwen_56_rd_A	915916640	0	0	0
alert_regwen_57_rd_A	915916640	0	0	0
alert_regwen_58_rd_A	915916640	0	0	0
alert_regwen_59_rd_A	915916640	0	0	0
alert_regwen_5_rd_A	915916640	0	0	0
alert_regwen_60_rd_A	915916640	0	0	0
alert_regwen_61_rd_A	915916640	0	0	0
alert_regwen_62_rd_A	915916640	0	0	0
alert_regwen_63_rd_A	915916640	0	0	0
alert_regwen_64_rd_A	915916640	0	0	0
alert_regwen_6_rd_A	915916640	0	0	0
alert_regwen_7_rd_A	915916640	0	0	0
alert_regwen_8_rd_A	915916640	0	0	0
alert_regwen_9_rd_A	915916640	0	0	0
classa_regwen_rd_A	915916640	0	0	0
classb_regwen_rd_A	915916640	0	0	0
classc_regwen_rd_A	915916640	0	0	0
classd_regwen_rd_A	915916640	0	0	0
intr_enable_rd_A	915916640	0	0	0
loc_alert_regwen_0_rd_A	915916640	0	0	0
loc_alert_regwen_1_rd_A	915916640	0	0	0
loc_alert_regwen_2_rd_A	915916640	0	0	0
loc_alert_regwen_3_rd_A	915916640	0	0	0
loc_alert_regwen_4_rd_A	915916640	0	0	0
loc_alert_regwen_5_rd_A	915916640	0	0	0
loc_alert_regwen_6_rd_A	915916640	0	0	0
ping_timer_regwen_rd_A	915916640	0	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	3203030	0	0
T1	6197	68	0	0
T2	22835	806	0	0
T3	6197	68	0	0
T4	6197	68	0	0
T5	0	68	0	0
T6	0	5	0	0
T7	0	5	0	0
T8	0	68	0	0
T9	0	68	0	0
T10	0	68	0	0
T11	9081	0	0	0
T12	123308	0	0	0
T13	590	0	0	0
T14	590	0	0	0
T15	9081	0	0	0
T16	328507	0	0	0

alert_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_24_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_25_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_26_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_27_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_28_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_29_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_30_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_31_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_32_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_33_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_34_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_35_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_36_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_37_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_38_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_39_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_40_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_41_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_42_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_43_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_44_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_45_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_46_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_47_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_48_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_49_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_50_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_51_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_52_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_53_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_54_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_55_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_56_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_57_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_58_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_59_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_60_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_61_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_62_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_63_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_64_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

alert_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

classa_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

classb_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

classc_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

classd_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

loc_alert_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

loc_alert_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

loc_alert_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

loc_alert_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

loc_alert_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

loc_alert_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

loc_alert_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0

ping_timer_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	915916640	0	0	0