Unified Coverage Report :: Module :: prim_edn_req

Module : prim_edn_req

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_req	96.15	100.00	84.62			100.00	100.00

---

Module Instance : tb.dut.u_edn_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.96	100.00	92.86			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00		99.75			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_packer_fifo	74.32	100.00	97.30			100.00	0.00
u_prim_sync_reqack_data	95.83	100.00	83.33			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_edn_req

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
ALWAYS	143	3	3	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	163	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
139	1	1
143	1	1
144	1	1
146	1	1
149	1	1
163		unreachable
164		unreachable
165		unreachable
166		unreachable
167		unreachable
168		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_edn_req

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (req_i & ((~ack_o)))
             --1--   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T19

 LINE       139
 EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
             --------1-------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       139
 SUB-EXPRESSION (req_i && ack_o)
                 --1--    --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T18,T19
1	1	Covered	T17,T18,T19

 LINE       139
 SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
                 ----1---

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       139
 SUB-EXPRESSION (fips_q & word_fips)
                 ---1--   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T18,T57
1	1	Covered	T17,T18,T19

---

Branch Coverage for Module : prim_edn_req

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
TERNARY	139	3	3	100.00
IF	143	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	((req_i && ack_o)) ? 
-2-:	139	(word_ack) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T18,T19
0	1	Covered	T17,T18,T19
0	0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	143	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19

---

Assert Coverage for Module : prim_edn_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOutputDiffFromPrev_A	874973625	289089300	0	0
DataOutputValid_A	874973625	5280	0	0

DataOutputDiffFromPrev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	289089300	0	0
T26	0	120542	0	0
T27	172614	677482	0	0
T28	0	677482	0	0
T29	78385	0	0	0
T30	326773	221907	0	0
T32	967326	0	0	0
T33	2783	0	0	0
T35	78385	0	0	0
T47	967326	0	0	0
T48	78385	0	0	0
T49	78385	0	0	0
T53	0	164827	0	0
T57	81339	78835	0	0
T65	0	120542	0	0
T86	0	221907	0	0
T107	0	164827	0	0
T108	0	164827	0	0

DataOutputValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874973625	5280	0	0
T17	447253	16	0	0
T18	967326	2	0	0
T19	81152	1	0	0
T23	78385	1	0	0
T24	81152	1	0	0
T29	78385	1	0	0
T30	326773	7	0	0
T32	967326	2	0	0
T35	78385	1	0	0
T57	81339	80	0	0