ALERT_HANDLER Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: 4002b28ec4

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	57.430s	1.559ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.690s	171.671us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.230s	162.171us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.104m	10.186ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.907m	5.866ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.470s	110.672us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.230s	162.171us	20	20	100.00
		alert_handler_csr_aliasing	3.907m	5.866ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.427m	6.995ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	53.600s	1.449ms	50	50	100.00
V2	entropy	alert_handler_entropy	20.464m	30.824ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	52.270s	1.262ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	57.430s	1.559ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	53.120s	1.400ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	49.980s	1.291ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	7.048m	17.274ms	50	50	100.00
V2	lpg	alert_handler_lpg	33.084m	58.352ms	50	50	100.00
		alert_handler_lpg_stub_clk	28.468m	48.173ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	36.829m	63.383ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	37.420s	1.452ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.110s	49.708us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.560s	10.547us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	17.220s	407.776us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	17.220s	407.776us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.690s	171.671us	5	5	100.00
		alert_handler_csr_rw	8.230s	162.171us	20	20	100.00
		alert_handler_csr_aliasing	3.907m	5.866ms	5	5	100.00
		alert_handler_same_csr_outstanding	36.860s	867.915us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.690s	171.671us	5	5	100.00
		alert_handler_csr_rw	8.230s	162.171us	20	20	100.00
		alert_handler_csr_aliasing	3.907m	5.866ms	5	5	100.00
		alert_handler_same_csr_outstanding	36.860s	867.915us	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.432m	7.309ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.432m	7.309ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.432m	7.309ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.432m	7.309ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	16.031m	22.019ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
		alert_handler_tl_intg_err	1.132m	1.597ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.132m	1.597ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.432m	7.309ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	57.430s	1.559ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	57.430s	1.559ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	57.430s	1.559ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	57.430s	1.559ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	52.270s	1.262ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	33.084m	58.352ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	52.270s	1.262ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	20.464m	30.824ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	20.464m	30.824ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.640s	740.845us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	50.478m	79.866ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			850	850	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.73	99.75	95.12	98.85	79.03	99.82	92.92	83.63

Past Results

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