ALERT_HANDLER Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.332m	947.178us	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	15.000s	224.250us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	12.570s	636.442us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	7.041m	11.437ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.816m	3.391ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	15.240s	506.873us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	12.570s	636.442us	20	20	100.00
		alert_handler_csr_aliasing	5.816m	3.391ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.551m	8.611ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.645m	5.852ms	50	50	100.00
V2	entropy	alert_handler_entropy	56.737m	213.860ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.415m	3.887ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.332m	947.178us	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.360m	963.251us	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.262m	1.126ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.824m	15.541ms	50	50	100.00
V2	lpg	alert_handler_lpg	54.868m	434.116ms	50	50	100.00
		alert_handler_lpg_stub_clk	54.733m	54.943ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.130h	150.480ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.410s	3.324ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	6.380s	176.968us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.020s	19.607us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	32.670s	1.422ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	32.670s	1.422ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	15.000s	224.250us	5	5	100.00
		alert_handler_csr_rw	12.570s	636.442us	20	20	100.00
		alert_handler_csr_aliasing	5.816m	3.391ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.223m	7.546ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	15.000s	224.250us	5	5	100.00
		alert_handler_csr_rw	12.570s	636.442us	20	20	100.00
		alert_handler_csr_aliasing	5.816m	3.391ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.223m	7.546ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.695m	2.256ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.695m	2.256ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.695m	2.256ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.695m	2.256ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.980m	68.289ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
		alert_handler_tl_intg_err	1.779m	3.145ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.779m	3.145ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.695m	2.256ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.332m	947.178us	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.332m	947.178us	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.332m	947.178us	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.332m	947.178us	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.415m	3.887ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	54.868m	434.116ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.415m	3.887ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	56.737m	213.860ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	56.737m	213.860ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	32.740s	848.763us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	10.192m	17.072ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.20	99.99	98.69	97.09	100.00	100.00	99.38	99.28

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test alert_handler_stress_all_with_rand_reset has 23 failures.

    • 0.alert_handler_stress_all_with_rand_reset.45479335227861812887841036212586728458267388524306726595451069939916232537140
      Line 2213, in log /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2005162429 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2005162429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.alert_handler_stress_all_with_rand_reset.43722369223818101741273070666975957532779161495133948936643768098878034404390
      Line 6693, in log /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8937519735 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8937519735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

Past Results

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