ALERT_HANDLER Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.835m	1.257ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.330s	264.042us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	14.900s	1.154ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	10.770m	142.639ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.966m	4.061ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	14.410s	839.676us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	14.900s	1.154ms	20	20	100.00
		alert_handler_csr_aliasing	4.966m	4.061ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	7.638m	6.016ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.744m	3.901ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.776m	38.408ms	49	50	98.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.710m	2.147ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.835m	1.257ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.693m	5.535ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.910m	1.246ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	12.343m	25.792ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.588m	57.177ms	49	50	98.00
		alert_handler_lpg_stub_clk	57.694m	55.561ms	49	50	98.00
V2	stress_all	alert_handler_stress_all	1.266h	275.336ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.962m	6.671ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	7.140s	78.865us	20	20	100.00
V2	intr_test	alert_handler_intr_test	3.550s	28.989us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	35.080s	3.608ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	35.080s	3.608ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.330s	264.042us	5	5	100.00
		alert_handler_csr_rw	14.900s	1.154ms	20	20	100.00
		alert_handler_csr_aliasing	4.966m	4.061ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.243m	715.705us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.330s	264.042us	5	5	100.00
		alert_handler_csr_rw	14.900s	1.154ms	20	20	100.00
		alert_handler_csr_aliasing	4.966m	4.061ms	5	5	100.00
		alert_handler_same_csr_outstanding	1.243m	715.705us	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.767m	7.805ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.767m	7.805ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.767m	7.805ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.767m	7.805ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.586m	16.827ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
		alert_handler_tl_intg_err	1.926m	1.230ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.926m	1.230ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.767m	7.805ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.835m	1.257ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.835m	1.257ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.835m	1.257ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.835m	1.257ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.710m	2.147ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.588m	57.177ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.710m	2.147ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.776m	38.408ms	49	50	98.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.776m	38.408ms	49	50	98.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	37.260s	959.945us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.968h	1.125s	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			827	850	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.25	99.99	98.72	97.09	100.00	100.00	99.38	99.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test alert_handler_stress_all_with_rand_reset has 17 failures.
  - 3.alert_handler_stress_all_with_rand_reset.27377122345603134786571810810415269725346526187171948297036941817137363192837
    Line 20728, in log /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87882472691 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 87882472691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.alert_handler_stress_all_with_rand_reset.33593917203274608454205114848760677808793693859087994954285159665401250177677
    Line 77316, in log /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108447729136 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108447729136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
Job timed out after * minutes has 6 failures:
- Test alert_handler_entropy has 1 failures.
  - 7.alert_handler_entropy.65496058043174536781509770472110079762649199445395423335584119633997221383325
    Log /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_entropy/latest/run.log
```
  Job timed out after 60 minutes
```
- Test alert_handler_stress_all_with_rand_reset has 3 failures.
  - 7.alert_handler_stress_all_with_rand_reset.5920674433563533263690407519652554274548022655934002657940856058349500388998
    Log /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 10.alert_handler_stress_all_with_rand_reset.97609108474881371008129799603880824418168073098006752655367395282302956706440
    Log /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 1 more failures.
- Test alert_handler_lpg_stub_clk has 1 failures.
  - 27.alert_handler_lpg_stub_clk.1738059030831873170558527775164046459204340956004845928641632482344392169079
    Log /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest/run.log
```
  Job timed out after 60 minutes
```
- Test alert_handler_lpg has 1 failures.
  - 36.alert_handler_lpg.90954500775225724757675559971180539229395406949665186822647979051703597968898
    Log /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_lpg/latest/run.log
```
  Job timed out after 60 minutes
```

ALERT_HANDLER Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `9f20940d49`