ALERT_HANDLER Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	59.770s	10.437ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	10.340s	505.376us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.080s	136.377us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.902m	11.410ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.063m	13.995ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.150s	79.818us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.080s	136.377us	20	20	100.00
		alert_handler_csr_aliasing	4.063m	13.995ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.362m	23.997ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.130m	1.250ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.456m	228.138ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.075m	4.319ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	59.770s	10.437ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	47.050s	826.752us	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.148m	1.180ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	9.658m	81.327ms	50	50	100.00
V2	lpg	alert_handler_lpg	51.968m	408.521ms	50	50	100.00
		alert_handler_lpg_stub_clk	52.139m	218.066ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.355h	301.287ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	52.860s	2.787ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.030s	99.638us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.650s	13.562us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.240s	336.215us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.240s	336.215us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	10.340s	505.376us	5	5	100.00
		alert_handler_csr_rw	9.080s	136.377us	20	20	100.00
		alert_handler_csr_aliasing	4.063m	13.995ms	5	5	100.00
		alert_handler_same_csr_outstanding	33.420s	2.163ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	10.340s	505.376us	5	5	100.00
		alert_handler_csr_rw	9.080s	136.377us	20	20	100.00
		alert_handler_csr_aliasing	4.063m	13.995ms	5	5	100.00
		alert_handler_same_csr_outstanding	33.420s	2.163ms	20	20	100.00
V2		TOTAL			630	630	100.00
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	19.941m	58.876ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	19.941m	58.876ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	19.941m	58.876ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	19.941m	58.876ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	1.156h	61.597ms	19	20	95.00
V2S	tl_intg_err	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
		alert_handler_tl_intg_err	1.290m	3.306ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.290m	3.306ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	19.941m	58.876ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	59.770s	10.437ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	59.770s	10.437ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	59.770s	10.437ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	59.770s	10.437ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.075m	4.319ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	51.968m	408.521ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.075m	4.319ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.456m	228.138ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.456m	228.138ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.620m	2.626ms	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.547h	91.058ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			847	850	99.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	15	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.65	99.99	98.74	100.00	100.00	100.00	99.25	99.60

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test alert_handler_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.alert_handler_shadow_reg_errors_with_csr_rw.3568586569
      Line 220, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_d, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 2.alert_handler_stress_all_with_rand_reset.931183648
      Line 755, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 57082488319 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_d, is_local_err 1, local_alert_type LocalEscIntFail
        UVM_INFO @ 57082488319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 33.alert_handler_stress_all_with_rand_reset.1586429907
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:08a2138c-6c4a-4027-b0c6-991270787f25
      

Past Results

• Latest
• 2023.05.28_21.32.51
• 2023.05.27_19.12.29
• 2023.05.26_19.16.22
• 2023.05.25_18.30.23
• 2023.05.24_17.47.50
• 2023.05.23_18.09.35
• 2023.05.22_19.52.19