ALERT_HANDLER Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.136m	10.318ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.390s	480.729us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.450s	453.796us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	9.394m	34.289ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.189m	6.688ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.330s	154.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.450s	453.796us	20	20	100.00
		alert_handler_csr_aliasing	4.189m	6.688ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	6.640m	43.342ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.355m	1.236ms	50	50	100.00
V2	entropy	alert_handler_entropy	55.179m	444.937ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.167m	1.053ms	50	50	100.00
V2	clk_skew	alert_handler_smoke	1.136m	10.318ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.308m	5.953ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.144m	4.195ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	11.760m	16.904ms	50	50	100.00
V2	lpg	alert_handler_lpg	50.683m	416.071ms	49	50	98.00
		alert_handler_lpg_stub_clk	56.956m	58.417ms	48	50	96.00
V2	stress_all	alert_handler_stress_all	58.298m	506.342ms	48	50	96.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	35.490s	792.448us	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.800s	48.410us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.050s	25.341us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	24.660s	396.139us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	24.660s	396.139us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.390s	480.729us	5	5	100.00
		alert_handler_csr_rw	9.450s	453.796us	20	20	100.00
		alert_handler_csr_aliasing	4.189m	6.688ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.910s	2.642ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.390s	480.729us	5	5	100.00
		alert_handler_csr_rw	9.450s	453.796us	20	20	100.00
		alert_handler_csr_aliasing	4.189m	6.688ms	5	5	100.00
		alert_handler_same_csr_outstanding	53.910s	2.642ms	20	20	100.00
V2		TOTAL			625	630	99.21
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.343m	5.495ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.343m	5.495ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.343m	5.495ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.343m	5.495ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	21.916m	34.253ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
		alert_handler_tl_intg_err	1.039m	594.060us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.039m	594.060us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.343m	5.495ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.136m	10.318ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.136m	10.318ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.136m	10.318ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.136m	10.318ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.167m	1.053ms	50	50	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	50.683m	416.071ms	49	50	98.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.167m	1.053ms	50	50	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	55.179m	444.937ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	55.179m	444.937ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	1.670s	11.122us	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.316h	82.971ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			815	850	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	12	80.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.57	99.86	98.49	89.17	91.94	99.81	97.13	99.60

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test alert_handler_stress_all_with_rand_reset has 24 failures.

    • 3.alert_handler_stress_all_with_rand_reset.39789949785456459911337511526439365922693765677918496112726693353411642560135
      Line 10554, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 40692411059 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10014 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 40692411059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.alert_handler_stress_all_with_rand_reset.28958941888606823425820578965314066872413346184642495953594636275913337728944
      Line 6592, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12753640837 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12753640837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• Offending '(state_q == StateEncodings[esc_state_o])' has 5 failures:

  • Test alert_handler_sec_cm has 5 failures.

    • 0.alert_handler_sec_cm.87457752227044695672163717350550932774956444119387953595806054237670456987589
      Line 264, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @  15052957 ps: (alert_handler_esc_timer.sv:427) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @  15052957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.alert_handler_sec_cm.61579667619826144048007900468535805804498880602490575597206573378197744350310
      Line 261, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest/run.log

            Offending '(state_q == StateEncodings[esc_state_o])'
        UVM_ERROR @   1730726 ps: (alert_handler_esc_timer.sv:427) [ASSERT FAILED] EscStateOut_A
        UVM_INFO @   1730726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 3 more failures.

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:

  • Test alert_handler_lpg_stub_clk has 2 failures.

    • 2.alert_handler_lpg_stub_clk.69946010878992556938147252901785161209890967040566836160960814691521065982495
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:6e617100-0b06-40a3-9e95-dcc225acf593
      

    • 20.alert_handler_lpg_stub_clk.6947031768200784207164908933299160725111248721139292745752031922532896972381
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest/run.log

        Job ID: smart:0f8f8332-a541-43ee-9c1c-191bd506ec14
      

  • Test alert_handler_lpg has 1 failures.

    • 33.alert_handler_lpg.79723570543193607427320205916384120137427111400486377365133177081698018517988
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_lpg/latest/run.log

        Job ID: smart:400fa9e5-5931-43a3-9b69-571aab286f74
      

• UVM_ERROR (alert_handler_scoreboard.sv:332) [scoreboard] Check failed cycle_cnt == exp_cycle (* [*] vs * [*]) has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 33.alert_handler_stress_all.14415871591966698316552326119353540910002090829437819670283963873174458631913
      Line 43930, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 86642214527 ps: (alert_handler_scoreboard.sv:332) [uvm_test_top.env.scoreboard] Check failed cycle_cnt == exp_cycle (308 [0x134] vs 543 [0x21f])
        UVM_INFO @ 86642214527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:

  • Test alert_handler_stress_all has 1 failures.

    • 38.alert_handler_stress_all.38250665029190440072451776375774639473121384479220960698374560268693413382349
      Line 74695, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_stress_all/latest/run.log

        UVM_ERROR @ 26825951540 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (382 [0x17e] vs 383 [0x17f]) reg name: alert_handler_reg_block.classa_accum_cnt
        UVM_INFO @ 26825951540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:753) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 40.alert_handler_stress_all_with_rand_reset.52951321549933263427925074491780095523927587961953343859302278061508931210507
      Line 83464, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 301466081148 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 301466081148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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