Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	91292	1			T8	410		T19	4		T20	8
class_i[0x1]	47818	1			T1	8		T3	582		T4	14
class_i[0x2]	71366	1			T4	8		T19	7		T22	3556
class_i[0x3]	51028	1			T1	7		T8	4		T19	2692

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	69175	1			T1	6		T4	8		T19	667
alert[0x1]	65161	1			T1	7		T3	7		T8	5
alert[0x2]	62739	1			T1	2		T3	573		T8	1
alert[0x3]	64429	1			T3	2		T8	408		T4	5

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

261213

1

T1

15

T3

582

T8

414

esc_ping_fail

291

1

T4

6

T11

3

T12

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	69088	1			T1	6		T4	6		T19	667
esc_integrity_fail	alert[0x1]	65094	1			T1	7		T3	7		T8	5
esc_integrity_fail	alert[0x2]	62667	1			T1	2		T3	573		T8	1
esc_integrity_fail	alert[0x3]	64364	1			T3	2		T8	408		T4	4
esc_ping_fail	alert[0x0]	87	1			T4	2		T11	1		T12	3
esc_ping_fail	alert[0x1]	67	1			T4	1		T12	1		T77	1
esc_ping_fail	alert[0x2]	72	1			T4	2		T11	1		T12	1
esc_ping_fail	alert[0x3]	65	1			T4	1		T11	1		T12	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	91209	1			T8	410		T19	4		T20	8
esc_integrity_fail	class_i[0x1]	47744	1			T1	8		T3	582		T4	14
esc_integrity_fail	class_i[0x2]	71294	1			T4	2		T19	7		T22	3556
esc_integrity_fail	class_i[0x3]	50966	1			T1	7		T8	4		T19	2692
esc_ping_fail	class_i[0x0]	83	1			T12	1		T79	1		T226	1
esc_ping_fail	class_i[0x1]	74	1			T76	1		T79	1		T82	1
esc_ping_fail	class_i[0x2]	72	1			T4	6		T11	3		T77	3
esc_ping_fail	class_i[0x3]	62	1			T12	5		T76	1		T79	1