Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	751538390	0	0	644
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	751538390	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	751538390	751381070	0	0
tb.dut.CheckAccuCntDw	0	0	644	644	0	0
tb.dut.CheckEscCntDw	0	0	644	644	0	0
tb.dut.CheckNAlerts	0	0	644	644	0	0
tb.dut.CheckNClasses	0	0	644	644	0	0
tb.dut.CheckNEscSev	0	0	644	644	0	0
tb.dut.CrashdumpKnownO_A	0	0	751538390	751381070	0	0
tb.dut.EdnKnownO_A	0	0	751538390	751381070	0	0
tb.dut.EscPKnownO_A	0	0	751538390	751381070	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	751538390	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	751538390	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	751538390	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	751538390	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	751538390	70	0	0
tb.dut.IrqAKnownO_A	0	0	751538390	751381070	0	0
tb.dut.IrqBKnownO_A	0	0	751538390	751381070	0	0
tb.dut.IrqCKnownO_A	0	0	751538390	751381070	0	0
tb.dut.IrqDKnownO_A	0	0	751538390	751381070	0	0
tb.dut.TlAReadyKnownO_A	0	0	751538390	751381070	0	0
tb.dut.TlDValidKnownO_A	0	0	751538390	751381070	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	773625189	3917813	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	773625189	15604	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	773625189	14364	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	773625189	14100	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	773625189	14268	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	773625189	15463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	773625189	15785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	773625189	13855	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	773625189	15104	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	773625189	15448	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	773625189	14641	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	773625189	14229	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	773625189	14129	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	773625189	15866	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	773625189	15441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	773625189	14604	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	773625189	14039	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	773625189	15396	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	773625189	13853	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	773625189	14633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	773625189	14255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	773625189	15317	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	773625189	14156	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	773625189	14032	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	773625189	14302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	773625189	15441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	773625189	14323	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	773625189	14317	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	773625189	14636	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	773625189	14087	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	773625189	14419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	773625189	14509	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	773625189	14151	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	773625189	15499	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	773625189	14154	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	773625189	14440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	773625189	15243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	773625189	14500	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	773625189	14838	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	773625189	13823	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	773625189	15682	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	773625189	14649	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	773625189	13946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	773625189	14610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	773625189	13951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	773625189	15327	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	773625189	14670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	773625189	15242	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	773625189	14281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	773625189	14203	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	773625189	14305	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	773625189	15328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	773625189	14073	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	773625189	14140	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	773625189	14285	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	773625189	13919	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	773625189	14065	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	773625189	14419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	773625189	14175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	773625189	14311	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	773625189	15812	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	773625189	15460	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	773625189	14105	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	773625189	14313	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	773625189	15512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	773625189	14367	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	773625189	14314	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	773625189	14395	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	773625189	14533	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	773625189	14106	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	773625189	26365	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	773625189	14459	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	773625189	15116	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	773625189	14397	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	773625189	15514	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	773625189	14409	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	773625189	14418	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	773625189	14497	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	773625189	14201	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	751538390	4817	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	751538390	202573	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	751538390	398602470	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	751538390	240	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	751538390	846	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	751538390	43	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	751538390	406	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	751314551	265057038	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	751538390	949	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	751538390	936	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	751538390	920	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	751538390	900	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	751538390	1368	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	751538390	153341	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	751538390	1247	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	751538390	78	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	751538390	1267	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	751538390	1057	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	751538390	751381070	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	751538390	1872	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	751538390	185360	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	751538390	431333086	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	751538390	263	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	751538390	586	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	751538390	16	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	751538390	299	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	751314551	324853956	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	751538390	679	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	751538390	654	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	751538390	643	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	751538390	627	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	751538390	1129	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	751538390	131800	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	751538390	1024	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	751538390	89	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	751538390	1302	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	751538390	1092	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	751538390	751381070	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	751538390	3456	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	751538390	211533	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	751538390	402413002	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	751538390	264	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	751538390	567	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	751538390	38	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	751538390	287	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	751314551	318760710	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	751538390	678	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	751538390	667	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	751538390	652	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	751538390	630	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	751538390	888	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	751538390	100537	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	751538390	773	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	751538390	77	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	751538390	1323	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	751538390	1113	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	751538390	751381070	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	751538390	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	751538390	3393	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	751538390	208408	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	751538390	418652129	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	751538390	239	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	751538390	599	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	751538390	22	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	751538390	267	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	751314551	315242107	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	751538390	676	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	751538390	660	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	751538390	650	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	751538390	641	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	751538390	750	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	751538390	99410	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	751538390	663	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	751538390	65	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	751538390	1242	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	751538390	1032	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	644	644	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	751538390	751381070	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	773625189	146868912	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	773625189	772977655	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	773625189	772977655	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	773625189	205898917	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	773625189	772977655	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	773625189	772977655	0	0
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