Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	78	1			T8	1		T39	3		T83	1
class_index[0x1]	89	1			T57	1		T38	1		T39	1
class_index[0x2]	77	1			T1	1		T3	1		T26	1
class_index[0x3]	65	1			T25	1		T39	1		T91	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	110	1			T3	1		T25	1		T26	1
intr_timeout_cnt[1]	68	1			T57	1		T95	1		T38	1
intr_timeout_cnt[2]	19	1			T39	2		T106	1		T140	1
intr_timeout_cnt[3]	28	1			T100	1		T40	1		T62	1
intr_timeout_cnt[4]	24	1			T39	1		T91	2		T92	1
intr_timeout_cnt[5]	17	1			T60	2		T63	1		T50	1
intr_timeout_cnt[6]	16	1			T1	1		T100	1		T44	1
intr_timeout_cnt[7]	10	1			T8	1		T139	1		T100	1
intr_timeout_cnt[8]	14	1			T39	3		T270	1		T219	1
intr_timeout_cnt[9]	3	1			T114	3		-	-		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0] , class_index[0x1]]	[intr_timeout_cnt[9]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T83	1		T104	1		T285	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T105	1		T122	1		T286	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T39	1		T106	1		T250	3
class_index[0x0]	intr_timeout_cnt[3]	9	1			T40	1		T63	1		T50	2
class_index[0x0]	intr_timeout_cnt[4]	8	1			T50	1		T287	4		T288	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T60	1		T289	1		T111	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T62	1		T290	1		T291	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T8	1		T100	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	4	1			T39	2		T292	1		T293	1
class_index[0x1]	intr_timeout_cnt[0]	37	1			T38	1		T98	1		T103	2
class_index[0x1]	intr_timeout_cnt[1]	20	1			T57	1		T97	1		T91	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T289	1		T294	1		T295	1
class_index[0x1]	intr_timeout_cnt[3]	6	1			T63	1		T296	1		T297	2
class_index[0x1]	intr_timeout_cnt[4]	4	1			T111	3		T298	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	5	1			T63	1		T299	1		T300	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T100	1		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T301	1		T302	1		T303	1
class_index[0x1]	intr_timeout_cnt[8]	7	1			T39	1		T270	1		T219	1
class_index[0x2]	intr_timeout_cnt[0]	25	1			T3	1		T26	1		T96	1
class_index[0x2]	intr_timeout_cnt[1]	21	1			T95	1		T38	1		T63	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T39	1		T74	1		T304	1
class_index[0x2]	intr_timeout_cnt[3]	7	1			T140	1		T270	1		T71	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T39	1		T92	1		T294	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T60	1		T50	1		T66	1
class_index[0x2]	intr_timeout_cnt[6]	7	1			T1	1		T299	4		T275	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T50	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T111	1		T291	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T114	3		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	21	1			T25	1		T138	1		T133	1
class_index[0x3]	intr_timeout_cnt[1]	16	1			T39	1		T44	1		T140	1
class_index[0x3]	intr_timeout_cnt[2]	3	1			T140	1		T305	1		T306	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T100	1		T62	1		T250	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T91	2		T66	2		T112	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T275	1		T307	1		T308	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T44	1		T309	2		T310	1
class_index[0x3]	intr_timeout_cnt[7]	3	1			T139	1		T74	1		T311	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T306	1		-	-		-	-