Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	368731	1			T29	5		T35	1		T192	8
all_values[1]	368731	1			T29	5		T35	1		T192	8
all_values[2]	368731	1			T29	5		T35	1		T192	8
all_values[3]	368731	1			T29	5		T35	1		T192	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

735739

1

T29

16

T35

4

T192

19

auto[1]

739185

1

T29

4

T192

13

T193

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

883624

1

T29

10

T35

4

T192

24

auto[1]

591300

1

T29

10

T192

8

T193

17

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	107443	1			T29	2		T35	1		T192	4
all_values[0]	auto[0]	auto[1]	77260	1			T29	2		T192	3		T193	3
all_values[0]	auto[1]	auto[0]	107477	1			T192	1		T193	2		T212	5
all_values[0]	auto[1]	auto[1]	76551	1			T29	1		T349	1		T350	1
all_values[1]	auto[0]	auto[0]	111999	1			T29	2		T35	1		T192	5
all_values[1]	auto[0]	auto[1]	71465	1			T29	2		T192	1		T193	2
all_values[1]	auto[1]	auto[0]	113302	1			T192	1		T193	1		T212	2
all_values[1]	auto[1]	auto[1]	71965	1			T29	1		T192	1		T193	4
all_values[2]	auto[0]	auto[0]	110374	1			T29	3		T35	1		T192	2
all_values[2]	auto[0]	auto[1]	73639	1			T29	1		T193	2		T212	1
all_values[2]	auto[1]	auto[0]	111016	1			T29	1		T192	4		T193	2
all_values[2]	auto[1]	auto[1]	73702	1			T192	2		T193	3		T212	2
all_values[3]	auto[0]	auto[0]	110173	1			T29	2		T35	1		T192	4
all_values[3]	auto[0]	auto[1]	73386	1			T29	2		T193	1		T259	1
all_values[3]	auto[1]	auto[0]	111840	1			T192	3		T193	3		T212	4
all_values[3]	auto[1]	auto[1]	73332	1			T29	1		T192	1		T193	2