Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	368731	1			T29	5		T35	1		T192	8
all_pins[1]	368731	1			T29	5		T35	1		T192	8
all_pins[2]	368731	1			T29	5		T35	1		T192	8
all_pins[3]	368731	1			T29	5		T35	1		T192	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1179374	1			T29	17		T35	4		T192	28
values[0x1]	295550	1			T29	3		T192	4		T193	9
transitions[0x0=>0x1]	196566	1			T29	1		T192	4		T193	8
transitions[0x1=>0x0]	196813	1			T29	1		T192	4		T193	8

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	292180	1			T29	4		T35	1		T192	8
all_pins[0]	values[0x1]	76551	1			T29	1		T349	1		T350	1
all_pins[0]	transitions[0x0=>0x1]	75790	1			T349	1		T1	2		T2	5
all_pins[0]	transitions[0x1=>0x0]	72818	1			T192	1		T193	2		T351	2
all_pins[1]	values[0x0]	296766	1			T29	4		T35	1		T192	7
all_pins[1]	values[0x1]	71965	1			T29	1		T192	1		T193	4
all_pins[1]	transitions[0x0=>0x1]	39175	1			T192	1		T193	4		T212	2
all_pins[1]	transitions[0x1=>0x0]	43761	1			T349	1		T350	1		T1	2
all_pins[2]	values[0x0]	295029	1			T29	5		T35	1		T192	6
all_pins[2]	values[0x1]	73702	1			T192	2		T193	3		T212	2
all_pins[2]	transitions[0x0=>0x1]	41116	1			T192	2		T193	2		T259	1
all_pins[2]	transitions[0x1=>0x0]	39379	1			T29	1		T192	1		T193	3
all_pins[3]	values[0x0]	295399	1			T29	4		T35	1		T192	7
all_pins[3]	values[0x1]	73332	1			T29	1		T192	1		T193	2
all_pins[3]	transitions[0x0=>0x1]	40485	1			T29	1		T192	1		T193	2
all_pins[3]	transitions[0x1=>0x0]	40855	1			T192	2		T193	3		T212	2