Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89391	1			T6	1241		T9	2159		T18	259
accum_cnt_1000	255403	1			T5	1714		T6	1077		T9	2144
accum_cnt_100	28978	1			T5	245		T6	52		T9	109
accum_cnt_50	84617	1			T8	21		T24	27		T5	170
accum_cnt_10	196807	1			T1	15		T2	22		T3	4
accum_cnt_0	390980	1			T1	25		T2	74		T3	8

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	271574	1			T1	10		T2	24		T3	3
class_index[0x1]	271571	1			T1	10		T2	24		T3	3
class_index[0x2]	271571	1			T1	10		T2	24		T3	3
class_index[0x3]	271571	1			T1	10		T2	24		T3	3

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22569	1			T6	595		T9	492		T20	89
class_index[0x0]	accum_cnt_1000	59782	1			T6	533		T9	468		T56	5
class_index[0x0]	accum_cnt_100	8212	1			T6	24		T9	24		T56	19
class_index[0x0]	accum_cnt_50	30188	1			T24	10		T6	28		T9	20
class_index[0x0]	accum_cnt_10	53335	1			T1	5		T2	22		T8	4
class_index[0x0]	accum_cnt_0	87471	1			T1	5		T2	2		T3	3
class_index[0x1]	accum_cnt_2000	21302	1			T6	646		T9	662		T19	152
class_index[0x1]	accum_cnt_1000	59085	1			T5	788		T6	544		T9	591
class_index[0x1]	accum_cnt_100	6820	1			T5	158		T6	28		T9	30
class_index[0x1]	accum_cnt_50	16650	1			T8	5		T5	106		T6	31
class_index[0x1]	accum_cnt_10	48376	1			T1	2		T3	3		T8	12
class_index[0x1]	accum_cnt_0	110405	1			T1	8		T2	24		T8	2
class_index[0x2]	accum_cnt_2000	22320	1			T9	579		T18	259		T22	200
class_index[0x2]	accum_cnt_1000	66369	1			T9	691		T55	9		T56	8
class_index[0x2]	accum_cnt_100	6381	1			T9	33		T55	17		T56	16
class_index[0x2]	accum_cnt_50	17642	1			T8	15		T24	17		T9	29
class_index[0x2]	accum_cnt_10	49302	1			T1	2		T3	1		T24	5
class_index[0x2]	accum_cnt_0	97223	1			T1	8		T2	24		T3	2
class_index[0x3]	accum_cnt_2000	23200	1			T9	426		T19	220		T22	411
class_index[0x3]	accum_cnt_1000	70167	1			T5	926		T9	394		T18	555
class_index[0x3]	accum_cnt_100	7565	1			T5	87		T9	22		T55	19
class_index[0x3]	accum_cnt_50	20137	1			T8	1		T5	64		T9	13
class_index[0x3]	accum_cnt_10	45794	1			T1	6		T8	16		T5	21
class_index[0x3]	accum_cnt_0	95881	1			T1	4		T2	24		T3	3