Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3727	1			T20	124		T22	224		T80	11
alert[0x1]	5598	1			T4	1		T19	1448		T80	4
alert[0x2]	4739	1			T8	10		T4	1		T20	14
alert[0x3]	5492	1			T8	1		T38	3		T39	15
alert[0x4]	3713	1			T4	1		T20	20		T22	6
alert[0x5]	4859	1			T22	72		T10	1		T79	1
alert[0x6]	4389	1			T19	33		T22	8		T101	234
alert[0x7]	5641	1			T4	1		T38	15		T80	1
alert[0x8]	2363	1			T19	25		T80	18		T84	5
alert[0x9]	2969	1			T19	77		T20	16		T11	1
alert[0xa]	5301	1			T19	21		T20	4		T22	58
alert[0xb]	3291	1			T4	1		T19	343		T22	32
alert[0xc]	13810	1			T3	32		T20	336		T22	42
alert[0xd]	3760	1			T19	52		T38	41		T91	1
alert[0xe]	5863	1			T39	54		T84	1		T87	1
alert[0xf]	3416	1			T4	1		T19	143		T22	375
alert[0x10]	8309	1			T8	1		T19	298		T22	23
alert[0x11]	9067	1			T8	5		T22	171		T12	1
alert[0x12]	6256	1			T4	1		T19	19		T22	583
alert[0x13]	6494	1			T19	239		T38	426		T82	1
alert[0x14]	8699	1			T5	1		T19	242		T20	31
alert[0x15]	3545	1			T5	1		T20	25		T22	485
alert[0x16]	9337	1			T4	1		T22	255		T39	454
alert[0x17]	3692	1			T19	100		T12	1		T38	1
alert[0x18]	7309	1			T19	293		T57	1		T22	105
alert[0x19]	4077	1			T80	3		T99	286		T223	1
alert[0x1a]	2643	1			T39	7		T82	1		T221	1
alert[0x1b]	7437	1			T22	117		T39	48		T99	1325
alert[0x1c]	2987	1			T8	3		T22	21		T11	1
alert[0x1d]	3854	1			T57	5		T12	1		T101	1737
alert[0x1e]	4089	1			T22	612		T84	1		T99	128
alert[0x1f]	5731	1			T76	1		T79	1		T221	1
alert[0x20]	3019	1			T19	48		T20	121		T57	1
alert[0x21]	2107	1			T19	76		T99	531		T224	1
alert[0x22]	14331	1			T19	161		T20	288		T57	3
alert[0x23]	1873	1			T19	49		T22	134		T38	99
alert[0x24]	7869	1			T19	41		T12	2		T38	15
alert[0x25]	3960	1			T19	121		T22	679		T79	1
alert[0x26]	2714	1			T57	9		T76	1		T80	16
alert[0x27]	1797	1			T8	11		T22	2		T38	16
alert[0x28]	4071	1			T12	1		T221	1		T99	6
alert[0x29]	9687	1			T8	1		T4	1		T22	27
alert[0x2a]	3014	1			T8	1		T19	7		T38	62
alert[0x2b]	7574	1			T19	9		T12	1		T38	129
alert[0x2c]	13479	1			T11	1		T77	1		T79	1
alert[0x2d]	3656	1			T19	16		T99	446		T100	2
alert[0x2e]	12344	1			T22	401		T39	63		T82	2
alert[0x2f]	4653	1			T19	335		T22	117		T38	358
alert[0x30]	5470	1			T19	20		T38	85		T39	5
alert[0x31]	4139	1			T38	111		T101	101		T44	1
alert[0x32]	8525	1			T19	146		T22	179		T38	43
alert[0x33]	8247	1			T19	220		T57	6		T22	12
alert[0x34]	4483	1			T22	370		T12	1		T80	5
alert[0x35]	2875	1			T19	36		T12	1		T79	1
alert[0x36]	4918	1			T8	6		T38	181		T39	9
alert[0x37]	7499	1			T8	1		T19	402		T57	3
alert[0x38]	2679	1			T19	57		T57	48		T22	6
alert[0x39]	6502	1			T38	13		T79	1		T39	7
alert[0x3a]	7070	1			T4	1		T20	200		T57	4
alert[0x3b]	5041	1			T19	97		T98	6		T92	199
alert[0x3c]	2755	1			T8	7		T19	117		T12	1
alert[0x3d]	6168	1			T19	45		T22	128		T38	178
alert[0x3e]	2266	1			T19	152		T20	6		T22	12
alert[0x3f]	5292	1			T19	14		T20	60		T22	434
alert[0x40]	2901	1			T19	15		T22	49		T39	11

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	87606	1			T19	5501		T57	2		T22	6
class_i[0x1]	112297	1			T4	10		T22	6824		T11	1
class_i[0x2]	61368	1			T3	32		T8	47		T20	1245
class_i[0x3]	94164	1			T5	2		T19	16		T57	78

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

354764

1

T3

32

T8

47

T19

5517

alert_ping_fail

671

1

T4

10

T5

2

T10

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3722	1			T20	124		T22	224		T80	11
alert_integrity_fail	alert[0x1]	5592	1			T19	1448		T80	4		T100	24
alert_integrity_fail	alert[0x2]	4728	1			T8	10		T20	14		T38	5
alert_integrity_fail	alert[0x3]	5480	1			T8	1		T38	3		T39	15
alert_integrity_fail	alert[0x4]	3700	1			T20	20		T22	6		T38	48
alert_integrity_fail	alert[0x5]	4842	1			T22	72		T99	207		T100	23
alert_integrity_fail	alert[0x6]	4377	1			T19	33		T22	8		T101	234
alert_integrity_fail	alert[0x7]	5629	1			T38	15		T80	1		T39	56
alert_integrity_fail	alert[0x8]	2352	1			T19	25		T80	18		T84	5
alert_integrity_fail	alert[0x9]	2963	1			T19	77		T20	16		T63	25
alert_integrity_fail	alert[0xa]	5288	1			T19	21		T20	4		T22	58
alert_integrity_fail	alert[0xb]	3282	1			T19	343		T22	32		T38	6
alert_integrity_fail	alert[0xc]	13804	1			T3	32		T20	336		T22	42
alert_integrity_fail	alert[0xd]	3749	1			T19	52		T38	41		T91	1
alert_integrity_fail	alert[0xe]	5854	1			T39	54		T84	1		T99	120
alert_integrity_fail	alert[0xf]	3408	1			T19	143		T22	375		T38	21
alert_integrity_fail	alert[0x10]	8298	1			T8	1		T19	298		T22	23
alert_integrity_fail	alert[0x11]	9054	1			T8	5		T22	171		T101	274
alert_integrity_fail	alert[0x12]	6248	1			T19	19		T22	583		T38	2
alert_integrity_fail	alert[0x13]	6478	1			T19	239		T38	426		T99	98
alert_integrity_fail	alert[0x14]	8687	1			T19	242		T20	31		T22	216
alert_integrity_fail	alert[0x15]	3532	1			T20	25		T22	485		T38	89
alert_integrity_fail	alert[0x16]	9331	1			T22	255		T39	454		T91	1
alert_integrity_fail	alert[0x17]	3683	1			T19	100		T38	1		T80	2
alert_integrity_fail	alert[0x18]	7293	1			T19	293		T57	1		T22	105
alert_integrity_fail	alert[0x19]	4071	1			T80	3		T99	286		T101	9
alert_integrity_fail	alert[0x1a]	2635	1			T39	7		T99	167		T92	1076
alert_integrity_fail	alert[0x1b]	7428	1			T22	117		T39	48		T99	1325
alert_integrity_fail	alert[0x1c]	2974	1			T8	3		T22	21		T125	3
alert_integrity_fail	alert[0x1d]	3839	1			T57	5		T101	1737		T40	1
alert_integrity_fail	alert[0x1e]	4075	1			T22	612		T84	1		T99	128
alert_integrity_fail	alert[0x1f]	5720	1			T125	4		T60	16		T118	4
alert_integrity_fail	alert[0x20]	3009	1			T19	48		T20	121		T57	1
alert_integrity_fail	alert[0x21]	2096	1			T19	76		T99	531		T269	12
alert_integrity_fail	alert[0x22]	14314	1			T19	161		T20	288		T57	3
alert_integrity_fail	alert[0x23]	1864	1			T19	49		T22	134		T38	99
alert_integrity_fail	alert[0x24]	7855	1			T19	41		T38	15		T80	1
alert_integrity_fail	alert[0x25]	3950	1			T19	121		T22	679		T80	6
alert_integrity_fail	alert[0x26]	2704	1			T57	9		T80	16		T39	7
alert_integrity_fail	alert[0x27]	1790	1			T8	11		T22	2		T38	16
alert_integrity_fail	alert[0x28]	4054	1			T99	6		T100	49		T103	1
alert_integrity_fail	alert[0x29]	9674	1			T8	1		T22	27		T101	141
alert_integrity_fail	alert[0x2a]	2997	1			T8	1		T19	7		T38	62
alert_integrity_fail	alert[0x2b]	7565	1			T19	9		T38	129		T39	26
alert_integrity_fail	alert[0x2c]	13455	1			T39	69		T44	4		T61	2
alert_integrity_fail	alert[0x2d]	3651	1			T19	16		T99	446		T100	2
alert_integrity_fail	alert[0x2e]	12332	1			T22	401		T39	63		T98	2
alert_integrity_fail	alert[0x2f]	4645	1			T19	335		T22	117		T38	358
alert_integrity_fail	alert[0x30]	5457	1			T19	20		T38	85		T39	5
alert_integrity_fail	alert[0x31]	4134	1			T38	111		T101	101		T44	1
alert_integrity_fail	alert[0x32]	8514	1			T19	146		T22	179		T38	43
alert_integrity_fail	alert[0x33]	8240	1			T19	220		T57	6		T22	12
alert_integrity_fail	alert[0x34]	4480	1			T22	370		T80	5		T99	61
alert_integrity_fail	alert[0x35]	2867	1			T19	36		T100	13		T101	11
alert_integrity_fail	alert[0x36]	4910	1			T8	6		T38	181		T39	9
alert_integrity_fail	alert[0x37]	7486	1			T8	1		T19	402		T57	3
alert_integrity_fail	alert[0x38]	2670	1			T19	57		T57	48		T22	6
alert_integrity_fail	alert[0x39]	6496	1			T38	13		T39	7		T100	14
alert_integrity_fail	alert[0x3a]	7058	1			T20	200		T57	4		T22	53
alert_integrity_fail	alert[0x3b]	5029	1			T19	97		T98	6		T92	199
alert_integrity_fail	alert[0x3c]	2751	1			T8	7		T19	117		T38	23
alert_integrity_fail	alert[0x3d]	6158	1			T19	45		T22	128		T38	178
alert_integrity_fail	alert[0x3e]	2258	1			T19	152		T20	6		T22	12
alert_integrity_fail	alert[0x3f]	5287	1			T19	14		T20	60		T22	434
alert_integrity_fail	alert[0x40]	2898	1			T19	15		T22	49		T39	11
alert_ping_fail	alert[0x0]	5	1			T316	1		T317	1		T318	1
alert_ping_fail	alert[0x1]	6	1			T4	1		T87	1		T223	1
alert_ping_fail	alert[0x2]	11	1			T4	1		T221	1		T223	1
alert_ping_fail	alert[0x3]	12	1			T253	1		T316	1		T271	1
alert_ping_fail	alert[0x4]	13	1			T4	1		T82	2		T221	1
alert_ping_fail	alert[0x5]	17	1			T10	1		T79	1		T319	1
alert_ping_fail	alert[0x6]	12	1			T224	1		T319	1		T320	1
alert_ping_fail	alert[0x7]	12	1			T4	1		T221	1		T273	1
alert_ping_fail	alert[0x8]	11	1			T87	1		T314	1		T320	1
alert_ping_fail	alert[0x9]	6	1			T11	1		T87	1		T321	1
alert_ping_fail	alert[0xa]	13	1			T82	3		T322	1		T271	2
alert_ping_fail	alert[0xb]	9	1			T4	1		T221	1		T223	1
alert_ping_fail	alert[0xc]	6	1			T253	1		T323	1		T324	1
alert_ping_fail	alert[0xd]	11	1			T223	2		T323	1		T321	1
alert_ping_fail	alert[0xe]	9	1			T87	1		T273	2		T325	1
alert_ping_fail	alert[0xf]	8	1			T4	1		T221	1		T226	1
alert_ping_fail	alert[0x10]	11	1			T87	1		T223	1		T135	1
alert_ping_fail	alert[0x11]	13	1			T12	1		T76	1		T79	1
alert_ping_fail	alert[0x12]	8	1			T4	1		T79	1		T82	1
alert_ping_fail	alert[0x13]	16	1			T82	1		T225	1		T326	2
alert_ping_fail	alert[0x14]	12	1			T5	1		T10	1		T221	1
alert_ping_fail	alert[0x15]	13	1			T5	1		T77	1		T273	1
alert_ping_fail	alert[0x16]	6	1			T4	1		T319	1		T323	1
alert_ping_fail	alert[0x17]	9	1			T12	1		T79	2		T82	1
alert_ping_fail	alert[0x18]	16	1			T221	1		T223	1		T253	1
alert_ping_fail	alert[0x19]	6	1			T223	1		T146	1		T253	1
alert_ping_fail	alert[0x1a]	8	1			T82	1		T221	1		T223	1
alert_ping_fail	alert[0x1b]	9	1			T223	1		T146	1		T320	1
alert_ping_fail	alert[0x1c]	13	1			T11	1		T82	1		T224	2
alert_ping_fail	alert[0x1d]	15	1			T12	1		T224	1		T320	1
alert_ping_fail	alert[0x1e]	14	1			T223	1		T224	2		T135	1
alert_ping_fail	alert[0x1f]	11	1			T76	1		T79	1		T221	1
alert_ping_fail	alert[0x20]	10	1			T12	1		T76	1		T223	1
alert_ping_fail	alert[0x21]	11	1			T224	1		T319	1		T320	2
alert_ping_fail	alert[0x22]	17	1			T12	1		T79	1		T221	1
alert_ping_fail	alert[0x23]	9	1			T253	1		T316	1		T327	1
alert_ping_fail	alert[0x24]	14	1			T12	2		T77	1		T221	1
alert_ping_fail	alert[0x25]	10	1			T79	1		T226	2		T223	1
alert_ping_fail	alert[0x26]	10	1			T76	1		T87	1		T146	3
alert_ping_fail	alert[0x27]	7	1			T87	1		T324	1		T325	1
alert_ping_fail	alert[0x28]	17	1			T12	1		T221	1		T225	2
alert_ping_fail	alert[0x29]	13	1			T4	1		T82	1		T221	2
alert_ping_fail	alert[0x2a]	17	1			T79	2		T82	1		T224	1
alert_ping_fail	alert[0x2b]	9	1			T12	1		T82	2		T224	1
alert_ping_fail	alert[0x2c]	24	1			T11	1		T77	1		T79	1
alert_ping_fail	alert[0x2d]	5	1			T273	1		T320	1		T323	1
alert_ping_fail	alert[0x2e]	12	1			T82	2		T87	1		T221	1
alert_ping_fail	alert[0x2f]	8	1			T321	1		T328	1		T329	1
alert_ping_fail	alert[0x30]	13	1			T87	1		T330	1		T320	1
alert_ping_fail	alert[0x31]	5	1			T331	2		T329	1		T332	1
alert_ping_fail	alert[0x32]	11	1			T77	1		T82	1		T221	1
alert_ping_fail	alert[0x33]	7	1			T11	1		T12	1		T87	1
alert_ping_fail	alert[0x34]	3	1			T12	1		T319	1		T333	1
alert_ping_fail	alert[0x35]	8	1			T12	1		T79	1		T221	1
alert_ping_fail	alert[0x36]	8	1			T221	1		T224	1		T146	1
alert_ping_fail	alert[0x37]	13	1			T76	1		T87	1		T226	2
alert_ping_fail	alert[0x38]	9	1			T77	1		T82	1		T323	1
alert_ping_fail	alert[0x39]	6	1			T79	1		T82	1		T146	1
alert_ping_fail	alert[0x3a]	12	1			T4	1		T11	1		T221	1
alert_ping_fail	alert[0x3b]	12	1			T224	1		T135	1		T271	3
alert_ping_fail	alert[0x3c]	4	1			T12	1		T87	1		T319	1
alert_ping_fail	alert[0x3d]	10	1			T77	1		T319	1		T253	1
alert_ping_fail	alert[0x3e]	8	1			T273	1		T323	1		T261	1
alert_ping_fail	alert[0x3f]	5	1			T12	1		T77	1		T253	1
alert_ping_fail	alert[0x40]	3	1			T334	1		T335	2		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	87489	1			T19	5501		T57	2		T22	6
alert_integrity_fail	class_i[0x1]	112038	1			T22	6824		T38	2220		T39	387
alert_integrity_fail	class_i[0x2]	61226	1			T3	32		T8	47		T20	1245
alert_integrity_fail	class_i[0x3]	94011	1			T19	16		T57	78		T38	1
alert_ping_fail	class_i[0x0]	117	1			T10	2		T11	1		T77	1
alert_ping_fail	class_i[0x1]	259	1			T4	10		T11	1		T76	1
alert_ping_fail	class_i[0x2]	142	1			T11	2		T76	2		T77	3
alert_ping_fail	class_i[0x3]	153	1			T5	2		T11	1		T12	14