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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.65 99.97 100.00 100.00 99.38 99.56


Total test records in report: 849
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T771 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3061771270 Dec 20 12:40:24 PM PST 23 Dec 20 12:41:41 PM PST 23 271228112 ps
T772 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.548181479 Dec 20 12:40:05 PM PST 23 Dec 20 12:42:22 PM PST 23 624507735 ps
T773 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2975842407 Dec 20 12:40:19 PM PST 23 Dec 20 12:41:20 PM PST 23 41966816 ps
T774 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2574565955 Dec 20 12:40:27 PM PST 23 Dec 20 12:41:37 PM PST 23 2186159511 ps
T775 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2243986248 Dec 20 12:40:13 PM PST 23 Dec 20 12:41:20 PM PST 23 54304207 ps
T178 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1572196891 Dec 20 12:40:41 PM PST 23 Dec 20 12:49:28 PM PST 23 46064757241 ps
T184 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4183998834 Dec 20 12:40:14 PM PST 23 Dec 20 12:48:33 PM PST 23 11711577907 ps
T776 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.226380293 Dec 20 12:40:12 PM PST 23 Dec 20 12:43:22 PM PST 23 2229517111 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1281417881 Dec 20 12:40:14 PM PST 23 Dec 20 12:41:31 PM PST 23 721589861 ps
T778 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4093548534 Dec 20 12:40:08 PM PST 23 Dec 20 12:44:11 PM PST 23 11884965770 ps
T779 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1432337913 Dec 20 12:40:14 PM PST 23 Dec 20 12:41:16 PM PST 23 7807241 ps
T780 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4053810010 Dec 20 12:40:34 PM PST 23 Dec 20 12:41:39 PM PST 23 6718558 ps
T781 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.464233400 Dec 20 12:40:24 PM PST 23 Dec 20 12:41:39 PM PST 23 8119849 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.512867628 Dec 20 12:40:24 PM PST 23 Dec 20 12:41:25 PM PST 23 10274452 ps
T783 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4121806604 Dec 20 12:40:54 PM PST 23 Dec 20 12:42:00 PM PST 23 18537098 ps
T784 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2446699611 Dec 20 12:40:38 PM PST 23 Dec 20 12:42:22 PM PST 23 3277557787 ps
T785 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1607348319 Dec 20 12:40:20 PM PST 23 Dec 20 12:41:32 PM PST 23 320455871 ps
T786 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1634804735 Dec 20 12:40:04 PM PST 23 Dec 20 12:41:20 PM PST 23 106869794 ps
T787 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.437232800 Dec 20 12:40:08 PM PST 23 Dec 20 12:41:15 PM PST 23 103403722 ps
T788 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1997657619 Dec 20 12:39:57 PM PST 23 Dec 20 12:41:17 PM PST 23 167271923 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3154955799 Dec 20 12:40:03 PM PST 23 Dec 20 12:41:17 PM PST 23 33853024 ps
T790 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2166121402 Dec 20 12:39:54 PM PST 23 Dec 20 12:41:16 PM PST 23 12973956 ps
T791 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.237084226 Dec 20 12:40:27 PM PST 23 Dec 20 12:41:39 PM PST 23 464233105 ps
T792 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1733686619 Dec 20 12:40:25 PM PST 23 Dec 20 12:41:33 PM PST 23 487116877 ps
T793 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.4221855289 Dec 20 12:40:28 PM PST 23 Dec 20 12:41:31 PM PST 23 9469083 ps
T199 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3121535253 Dec 20 12:40:28 PM PST 23 Dec 20 12:41:32 PM PST 23 204782478 ps
T794 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2587685204 Dec 20 12:40:08 PM PST 23 Dec 20 12:42:54 PM PST 23 864443995 ps
T795 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1114814800 Dec 20 12:40:30 PM PST 23 Dec 20 12:41:39 PM PST 23 126847125 ps
T796 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3778919602 Dec 20 12:41:07 PM PST 23 Dec 20 12:42:14 PM PST 23 12330057 ps
T173 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4115184917 Dec 20 12:40:47 PM PST 23 Dec 20 12:43:50 PM PST 23 1199172639 ps
T797 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1757773481 Dec 20 12:40:37 PM PST 23 Dec 20 12:41:41 PM PST 23 8056994 ps
T798 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3059527209 Dec 20 12:40:46 PM PST 23 Dec 20 12:42:03 PM PST 23 611196511 ps
T181 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.440111273 Dec 20 12:39:50 PM PST 23 Dec 20 12:42:53 PM PST 23 3370452735 ps
T799 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.250789069 Dec 20 12:40:47 PM PST 23 Dec 20 12:41:57 PM PST 23 30771423 ps
T800 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3330546826 Dec 20 12:40:36 PM PST 23 Dec 20 12:41:40 PM PST 23 15229066 ps
T801 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3945809684 Dec 20 12:40:19 PM PST 23 Dec 20 12:41:26 PM PST 23 429675259 ps
T802 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1069462502 Dec 20 12:39:49 PM PST 23 Dec 20 12:40:56 PM PST 23 19931715 ps
T198 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3526455911 Dec 20 12:40:00 PM PST 23 Dec 20 12:41:04 PM PST 23 61314876 ps
T168 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2317030923 Dec 20 12:40:42 PM PST 23 Dec 20 12:50:13 PM PST 23 8648060577 ps
T803 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.295454186 Dec 20 12:41:02 PM PST 23 Dec 20 12:42:07 PM PST 23 11651332 ps
T183 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3342044228 Dec 20 12:40:13 PM PST 23 Dec 20 12:45:06 PM PST 23 2238115644 ps
T804 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.467066123 Dec 20 12:40:14 PM PST 23 Dec 20 12:41:23 PM PST 23 23624109 ps
T805 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4293094667 Dec 20 12:40:05 PM PST 23 Dec 20 12:41:13 PM PST 23 98940434 ps
T188 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.475974610 Dec 20 12:40:25 PM PST 23 Dec 20 12:46:35 PM PST 23 7184579066 ps
T806 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1308816430 Dec 20 12:40:32 PM PST 23 Dec 20 12:41:34 PM PST 23 16121111 ps
T807 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4138799360 Dec 20 12:40:21 PM PST 23 Dec 20 12:41:29 PM PST 23 250633120 ps
T808 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3915941527 Dec 20 12:40:14 PM PST 23 Dec 20 12:41:21 PM PST 23 69025603 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1958694379 Dec 20 12:40:20 PM PST 23 Dec 20 12:42:56 PM PST 23 3714753539 ps
T810 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2625214711 Dec 20 12:40:09 PM PST 23 Dec 20 12:41:23 PM PST 23 72657061 ps
T206 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3372696427 Dec 20 12:40:47 PM PST 23 Dec 20 12:42:55 PM PST 23 3682716131 ps
T207 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1106304408 Dec 20 12:40:30 PM PST 23 Dec 20 12:42:18 PM PST 23 784126049 ps
T811 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3015852568 Dec 20 12:40:30 PM PST 23 Dec 20 12:42:07 PM PST 23 6498736989 ps
T812 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.413856257 Dec 20 12:40:43 PM PST 23 Dec 20 12:41:55 PM PST 23 548907914 ps
T185 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1888826223 Dec 20 12:39:47 PM PST 23 Dec 20 12:50:03 PM PST 23 46058411560 ps
T813 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2556091719 Dec 20 12:40:42 PM PST 23 Dec 20 12:41:46 PM PST 23 9066128 ps
T814 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4198520934 Dec 20 12:40:10 PM PST 23 Dec 20 12:41:47 PM PST 23 773442617 ps
T815 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2353606902 Dec 20 12:41:11 PM PST 23 Dec 20 12:42:16 PM PST 23 14568093 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3122832021 Dec 20 12:40:14 PM PST 23 Dec 20 12:41:21 PM PST 23 8719126 ps
T817 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1689789410 Dec 20 12:40:44 PM PST 23 Dec 20 12:41:50 PM PST 23 19485886 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3130402429 Dec 20 12:40:07 PM PST 23 Dec 20 12:41:22 PM PST 23 213131024 ps
T819 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.30618881 Dec 20 12:40:40 PM PST 23 Dec 20 12:41:44 PM PST 23 14947771 ps
T205 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.517837520 Dec 20 12:39:58 PM PST 23 Dec 20 12:41:06 PM PST 23 121584142 ps
T820 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.589813672 Dec 20 12:40:52 PM PST 23 Dec 20 12:41:58 PM PST 23 30033038 ps
T174 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4053195605 Dec 20 12:40:35 PM PST 23 Dec 20 12:44:33 PM PST 23 2968922102 ps
T821 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2409155437 Dec 20 12:40:18 PM PST 23 Dec 20 12:41:19 PM PST 23 25722856 ps
T822 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3674637974 Dec 20 12:40:05 PM PST 23 Dec 20 12:41:15 PM PST 23 125546746 ps
T357 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.184475729 Dec 20 12:41:00 PM PST 23 Dec 20 12:51:15 PM PST 23 9148861272 ps
T823 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.346598081 Dec 20 12:40:25 PM PST 23 Dec 20 12:41:35 PM PST 23 29519581 ps
T824 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4255493109 Dec 20 12:40:30 PM PST 23 Dec 20 12:41:35 PM PST 23 52307538 ps
T825 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.300957772 Dec 20 12:40:13 PM PST 23 Dec 20 12:41:21 PM PST 23 55140530 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1436346921 Dec 20 12:40:44 PM PST 23 Dec 20 12:41:50 PM PST 23 76866299 ps
T356 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3985520654 Dec 20 12:40:34 PM PST 23 Dec 20 12:50:16 PM PST 23 42471915875 ps
T827 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4203167336 Dec 20 12:40:43 PM PST 23 Dec 20 12:41:47 PM PST 23 12111344 ps
T828 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1140515158 Dec 20 12:41:16 PM PST 23 Dec 20 12:42:28 PM PST 23 755261957 ps
T202 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1438804714 Dec 20 12:40:40 PM PST 23 Dec 20 12:42:51 PM PST 23 893640105 ps
T829 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1488975961 Dec 20 12:39:52 PM PST 23 Dec 20 12:41:06 PM PST 23 63660677 ps
T830 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3653341358 Dec 20 12:41:34 PM PST 23 Dec 20 12:42:39 PM PST 23 7627823 ps
T831 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1118733533 Dec 20 12:40:17 PM PST 23 Dec 20 12:41:18 PM PST 23 23184176 ps
T832 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2382597152 Dec 20 12:40:39 PM PST 23 Dec 20 12:41:46 PM PST 23 20689024 ps
T833 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.969342610 Dec 20 12:40:16 PM PST 23 Dec 20 12:41:35 PM PST 23 337826540 ps
T834 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1051535564 Dec 20 12:40:16 PM PST 23 Dec 20 12:41:16 PM PST 23 6924738 ps
T835 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4145679303 Dec 20 12:40:22 PM PST 23 Dec 20 12:41:46 PM PST 23 378867508 ps
T836 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3942098462 Dec 20 12:39:59 PM PST 23 Dec 20 12:41:13 PM PST 23 109357846 ps
T837 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1665252585 Dec 20 12:40:23 PM PST 23 Dec 20 12:41:26 PM PST 23 129442763 ps
T838 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4013677425 Dec 20 12:40:04 PM PST 23 Dec 20 12:41:14 PM PST 23 59681315 ps
T839 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2264087070 Dec 20 12:40:10 PM PST 23 Dec 20 12:41:17 PM PST 23 581491706 ps
T840 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2389170792 Dec 20 12:40:25 PM PST 23 Dec 20 12:41:36 PM PST 23 312304665 ps
T165 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3721222307 Dec 20 12:40:22 PM PST 23 Dec 20 12:46:31 PM PST 23 6563491889 ps
T841 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3216126798 Dec 20 12:40:05 PM PST 23 Dec 20 12:43:36 PM PST 23 4580140854 ps
T842 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3085025051 Dec 20 12:40:39 PM PST 23 Dec 20 12:41:44 PM PST 23 8371525 ps
T843 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4179667263 Dec 20 12:40:49 PM PST 23 Dec 20 12:41:56 PM PST 23 52790964 ps
T844 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.427825131 Dec 20 12:40:49 PM PST 23 Dec 20 12:41:54 PM PST 23 9409685 ps
T845 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1601930719 Dec 20 12:40:33 PM PST 23 Dec 20 12:41:41 PM PST 23 50778387 ps
T846 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.437770933 Dec 20 12:40:38 PM PST 23 Dec 20 12:41:46 PM PST 23 63434951 ps
T847 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.504777850 Dec 20 12:41:47 PM PST 23 Dec 20 12:42:50 PM PST 23 6899321 ps
T166 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3956339401 Dec 20 12:40:30 PM PST 23 Dec 20 12:46:04 PM PST 23 8260661617 ps
T848 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1726221788 Dec 20 12:40:39 PM PST 23 Dec 20 12:41:47 PM PST 23 59121627 ps
T849 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1063453311 Dec 20 12:40:29 PM PST 23 Dec 20 12:41:36 PM PST 23 7587423 ps
T182 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1813196301 Dec 20 12:40:16 PM PST 23 Dec 20 12:50:04 PM PST 23 8526584122 ps

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3107308522
Short name T16
Test name
Test status
Simulation time 32453499719 ps
CPU time 276.79 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:46:22 PM PST 23
Peak memory 268156 kb
Host smart-bfdea2ea-cb4c-43d0-8e89-2e1aa335b412
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107308522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3107308522
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2155759346
Short name T8
Test name
Test status
Simulation time 1325452370 ps
CPU time 37.78 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 12:58:12 PM PST 23
Peak memory 248064 kb
Host smart-53a25105-0c89-4f8a-89b0-e0994fe3e886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21557
59346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2155759346
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.394943646
Short name T177
Test name
Test status
Simulation time 300420684 ps
CPU time 21.61 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:42 PM PST 23
Peak memory 245216 kb
Host smart-9a4fb4bb-cc82-4da9-a031-e66787f7ca4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=394943646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.394943646
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.2029148159
Short name T38
Test name
Test status
Simulation time 67584030591 ps
CPU time 4260.96 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 02:08:52 PM PST 23
Peak memory 319096 kb
Host smart-8aedd451-cc2a-4fe6-942a-c688eaaea551
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029148159 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.2029148159
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1318963496
Short name T46
Test name
Test status
Simulation time 1370807606 ps
CPU time 12.71 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:57:15 PM PST 23
Peak memory 269100 kb
Host smart-366e4a0f-1826-4932-a12c-1199e76e36a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1318963496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1318963496
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3496524798
Short name T148
Test name
Test status
Simulation time 22434868025 ps
CPU time 359.32 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:47:45 PM PST 23
Peak memory 265420 kb
Host smart-c76191b5-f9b3-4068-9472-a2ea95565cb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3496524798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3496524798
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1750759312
Short name T9
Test name
Test status
Simulation time 52956625418 ps
CPU time 2799.2 seconds
Started Dec 20 12:56:57 PM PST 23
Finished Dec 20 01:43:49 PM PST 23
Peak memory 288204 kb
Host smart-295848fe-32fa-4013-b92f-73adc14a9336
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750759312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1750759312
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2807940568
Short name T39
Test name
Test status
Simulation time 67517883074 ps
CPU time 4305.27 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 02:09:02 PM PST 23
Peak memory 314176 kb
Host smart-ea166498-513f-45ed-ad40-7d00b09c07d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807940568 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2807940568
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1150841548
Short name T10
Test name
Test status
Simulation time 29242297640 ps
CPU time 1538.54 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 01:23:01 PM PST 23
Peak memory 273324 kb
Host smart-d84d3666-b85a-4f4b-8051-a518edfd9c78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150841548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1150841548
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2038547341
Short name T149
Test name
Test status
Simulation time 19454818941 ps
CPU time 588.22 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:50:59 PM PST 23
Peak memory 272732 kb
Host smart-f6b8e910-f779-4977-b58d-100eb1a078cc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038547341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2038547341
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2434935475
Short name T107
Test name
Test status
Simulation time 774474308 ps
CPU time 32.75 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 240288 kb
Host smart-3770b002-b133-4268-8355-de9534139be6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2434935475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2434935475
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.470944387
Short name T193
Test name
Test status
Simulation time 8369070 ps
CPU time 1.37 seconds
Started Dec 20 12:40:16 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 235680 kb
Host smart-c0fe2dbb-f136-4e91-a2c2-e7b61f6959a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=470944387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.470944387
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.912349186
Short name T27
Test name
Test status
Simulation time 14549187658 ps
CPU time 296.61 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:46:21 PM PST 23
Peak memory 266532 kb
Host smart-91782960-1643-46db-adbd-634568106e14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=912349186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.912349186
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1998858857
Short name T17
Test name
Test status
Simulation time 128432771578 ps
CPU time 3323.76 seconds
Started Dec 20 12:57:09 PM PST 23
Finished Dec 20 01:52:49 PM PST 23
Peak memory 289120 kb
Host smart-da764776-8b52-4e67-9745-6e1e08fd4e55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998858857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1998858857
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2022155442
Short name T19
Test name
Test status
Simulation time 21996164812 ps
CPU time 646 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 01:08:04 PM PST 23
Peak memory 273480 kb
Host smart-2dead5cd-0f8d-488f-9e5b-bacca0f376a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022155442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2022155442
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2734511202
Short name T175
Test name
Test status
Simulation time 149089859244 ps
CPU time 840.32 seconds
Started Dec 20 12:40:06 PM PST 23
Finished Dec 20 12:55:11 PM PST 23
Peak memory 265572 kb
Host smart-d0892482-0372-46ab-b3b8-f807fdb3c39d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734511202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2734511202
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3504148052
Short name T221
Test name
Test status
Simulation time 44695318948 ps
CPU time 495.1 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 01:06:07 PM PST 23
Peak memory 247468 kb
Host smart-77d0fc5f-1ba3-454f-8bb4-db45fde64a9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504148052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3504148052
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3534566750
Short name T160
Test name
Test status
Simulation time 17490804875 ps
CPU time 326.18 seconds
Started Dec 20 12:40:23 PM PST 23
Finished Dec 20 12:46:50 PM PST 23
Peak memory 265416 kb
Host smart-fb7e07c1-3993-4351-8fa6-dec170e49580
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3534566750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3534566750
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.481791782
Short name T50
Test name
Test status
Simulation time 37382036756 ps
CPU time 1766.51 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 01:27:00 PM PST 23
Peak memory 284324 kb
Host smart-1b045ee5-3ce9-4a91-baba-1665ee938527
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481791782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.481791782
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3918893297
Short name T322
Test name
Test status
Simulation time 88066745440 ps
CPU time 2569.28 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 01:40:32 PM PST 23
Peak memory 285416 kb
Host smart-6f2a206f-d615-42ab-abe3-95cc76db72f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918893297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3918893297
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4264916523
Short name T87
Test name
Test status
Simulation time 42108115949 ps
CPU time 401.14 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 01:03:59 PM PST 23
Peak memory 247632 kb
Host smart-847d4498-8201-4910-9808-9b93761494d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264916523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4264916523
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2340725372
Short name T151
Test name
Test status
Simulation time 47743569361 ps
CPU time 889.21 seconds
Started Dec 20 12:40:19 PM PST 23
Finished Dec 20 12:56:08 PM PST 23
Peak memory 265388 kb
Host smart-7be595f0-6cf9-446f-a66d-221783cde954
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340725372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2340725372
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3272415308
Short name T12
Test name
Test status
Simulation time 9905707771 ps
CPU time 402.29 seconds
Started Dec 20 12:58:07 PM PST 23
Finished Dec 20 01:05:06 PM PST 23
Peak memory 247712 kb
Host smart-98b1eb98-fc2b-4297-abaa-ab04f96a09a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272415308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3272415308
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2025238129
Short name T22
Test name
Test status
Simulation time 34853927857 ps
CPU time 1886.37 seconds
Started Dec 20 12:58:14 PM PST 23
Finished Dec 20 01:29:59 PM PST 23
Peak memory 273152 kb
Host smart-a043b903-0857-46a0-9cb1-5bdd8b1b02ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025238129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2025238129
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3693596149
Short name T323
Test name
Test status
Simulation time 11091894748 ps
CPU time 490.65 seconds
Started Dec 20 12:56:41 PM PST 23
Finished Dec 20 01:04:57 PM PST 23
Peak memory 247696 kb
Host smart-db8923e9-de74-4fdc-a5c7-8ef797931b5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693596149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3693596149
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1062534360
Short name T225
Test name
Test status
Simulation time 152158984835 ps
CPU time 1974.9 seconds
Started Dec 20 12:58:38 PM PST 23
Finished Dec 20 01:31:51 PM PST 23
Peak memory 272756 kb
Host smart-fcbee4a9-b6bb-4c52-a30d-1ffdf1e73184
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062534360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1062534360
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4161349074
Short name T150
Test name
Test status
Simulation time 6295008706 ps
CPU time 167.48 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:44:33 PM PST 23
Peak memory 271376 kb
Host smart-94052119-5bc6-4a7c-95ba-b8f6dad61188
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4161349074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.4161349074
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.466099083
Short name T57
Test name
Test status
Simulation time 32719276826 ps
CPU time 833.78 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 01:12:24 PM PST 23
Peak memory 267268 kb
Host smart-87529d13-7094-4df5-9b42-7de2b6ce6ad9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466099083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.466099083
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3721222307
Short name T165
Test name
Test status
Simulation time 6563491889 ps
CPU time 307.88 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:46:31 PM PST 23
Peak memory 266584 kb
Host smart-83c0a8fb-1ca1-4cbc-871f-160b4a2493eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3721222307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3721222307
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1718604157
Short name T330
Test name
Test status
Simulation time 33617982159 ps
CPU time 1907.23 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:29:25 PM PST 23
Peak memory 285704 kb
Host smart-2a8fbf46-e8e4-48a1-9394-e438278d0c8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718604157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1718604157
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2647241210
Short name T169
Test name
Test status
Simulation time 16507289811 ps
CPU time 1034.86 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:58:38 PM PST 23
Peak memory 265612 kb
Host smart-c36e8fc7-aec7-4d0c-9390-3966680fdc55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647241210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2647241210
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.510813467
Short name T44
Test name
Test status
Simulation time 252923862269 ps
CPU time 3613.92 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 01:58:06 PM PST 23
Peak memory 306304 kb
Host smart-79ee1a16-b284-4b16-855b-19df9149c0d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510813467 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.510813467
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1300553110
Short name T59
Test name
Test status
Simulation time 21255643693 ps
CPU time 1170.49 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 01:17:56 PM PST 23
Peak memory 273556 kb
Host smart-f11d99a4-236b-4ac3-be41-d325ec4107a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300553110 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1300553110
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3583879063
Short name T321
Test name
Test status
Simulation time 51791440717 ps
CPU time 565.39 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 01:06:53 PM PST 23
Peak memory 247776 kb
Host smart-a18f2c00-f11a-42e6-a58d-3252b84bfcd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583879063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3583879063
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4069933759
Short name T342
Test name
Test status
Simulation time 162290189961 ps
CPU time 1958.68 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 01:30:32 PM PST 23
Peak memory 273376 kb
Host smart-cf3c88c7-1fda-4465-a5e1-11882ab0702d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069933759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4069933759
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2423305761
Short name T83
Test name
Test status
Simulation time 282541597 ps
CPU time 24.85 seconds
Started Dec 20 12:58:09 PM PST 23
Finished Dec 20 12:58:53 PM PST 23
Peak memory 255508 kb
Host smart-7d5a4621-5aea-4190-ad55-245d4e704dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24233
05761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2423305761
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.300883724
Short name T154
Test name
Test status
Simulation time 12178101621 ps
CPU time 862.47 seconds
Started Dec 20 12:40:12 PM PST 23
Finished Dec 20 12:55:36 PM PST 23
Peak memory 273004 kb
Host smart-652fd2f3-5d64-4fea-89d7-ccb0cf2b0e1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300883724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.300883724
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.869775745
Short name T111
Test name
Test status
Simulation time 98899050945 ps
CPU time 3134.03 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:49:51 PM PST 23
Peak memory 305584 kb
Host smart-3457684e-8368-4d17-8edb-bc5028f624ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869775745 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.869775745
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.382531222
Short name T765
Test name
Test status
Simulation time 21629315 ps
CPU time 1.38 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:41:34 PM PST 23
Peak memory 235520 kb
Host smart-ed39e55c-d83a-4a75-adc4-7e179de4eafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=382531222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.382531222
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2747890604
Short name T63
Test name
Test status
Simulation time 309147346376 ps
CPU time 2361.07 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:36:57 PM PST 23
Peak memory 289484 kb
Host smart-d0cabc0d-9550-4580-a46d-47f886722240
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747890604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2747890604
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3132565861
Short name T62
Test name
Test status
Simulation time 568845110293 ps
CPU time 3298.15 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 01:52:49 PM PST 23
Peak memory 298000 kb
Host smart-a07d5ce6-74d4-4b40-9abe-ade329ec1985
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132565861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3132565861
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4053195605
Short name T174
Test name
Test status
Simulation time 2968922102 ps
CPU time 175.02 seconds
Started Dec 20 12:40:35 PM PST 23
Finished Dec 20 12:44:33 PM PST 23
Peak memory 257256 kb
Host smart-8e6153c3-cd4a-40e7-aa17-269eb9297181
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4053195605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.4053195605
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3070187824
Short name T697
Test name
Test status
Simulation time 96182386914 ps
CPU time 237.31 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 01:01:51 PM PST 23
Peak memory 247352 kb
Host smart-9a587b8a-5123-4f3c-a140-bd04f5bb0a05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070187824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3070187824
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1517785947
Short name T289
Test name
Test status
Simulation time 51804083410 ps
CPU time 255.3 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:01:52 PM PST 23
Peak memory 257016 kb
Host smart-88b3b1fd-3082-495e-b280-e2fb90c6e469
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517785947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1517785947
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.565484919
Short name T312
Test name
Test status
Simulation time 307996648641 ps
CPU time 2177.78 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:34:18 PM PST 23
Peak memory 288580 kb
Host smart-b8634b97-de25-4afd-92e5-6919abf17edc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565484919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.565484919
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3920226921
Short name T114
Test name
Test status
Simulation time 37459497746 ps
CPU time 2322.37 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 01:36:15 PM PST 23
Peak memory 283316 kb
Host smart-95e94725-d6ba-4d56-a708-8633a3801446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920226921 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3920226921
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2558976133
Short name T5
Test name
Test status
Simulation time 192815674893 ps
CPU time 2469.87 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 01:39:06 PM PST 23
Peak memory 283688 kb
Host smart-76bc23f3-c865-43de-a4f8-63192abe5940
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558976133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2558976133
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3121535253
Short name T199
Test name
Test status
Simulation time 204782478 ps
CPU time 3.95 seconds
Started Dec 20 12:40:28 PM PST 23
Finished Dec 20 12:41:32 PM PST 23
Peak memory 236540 kb
Host smart-738574cc-890e-43b8-b9dd-c8931a2d9607
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3121535253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3121535253
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4255719325
Short name T110
Test name
Test status
Simulation time 64974492712 ps
CPU time 1706.22 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 01:26:16 PM PST 23
Peak memory 289724 kb
Host smart-a7ae83a7-87c5-4d08-963e-be5c3edab013
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255719325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4255719325
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3333866439
Short name T7
Test name
Test status
Simulation time 200532353 ps
CPU time 3.88 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:57:35 PM PST 23
Peak memory 248876 kb
Host smart-51877e2e-f8d8-4393-bc99-7dd28cdfaad1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3333866439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3333866439
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2262811838
Short name T232
Test name
Test status
Simulation time 42711307 ps
CPU time 3.44 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 248884 kb
Host smart-95777c97-6811-4a94-8050-75ab1171283d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2262811838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2262811838
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1637207692
Short name T231
Test name
Test status
Simulation time 38745158 ps
CPU time 3.55 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 12:57:09 PM PST 23
Peak memory 248940 kb
Host smart-ae45bfd9-2c80-4db7-82a1-0847ebb8f58c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1637207692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1637207692
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.351657940
Short name T236
Test name
Test status
Simulation time 59256120 ps
CPU time 2.33 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:57:03 PM PST 23
Peak memory 248868 kb
Host smart-84bdb0f2-0c2b-46eb-a779-8a7d9a330f20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=351657940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.351657940
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1538467971
Short name T164
Test name
Test status
Simulation time 4626238442 ps
CPU time 316.97 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:46:43 PM PST 23
Peak memory 265352 kb
Host smart-fde16dc8-9000-4f35-840a-ea4cebce2024
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538467971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1538467971
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3792039115
Short name T260
Test name
Test status
Simulation time 8809775409 ps
CPU time 65.46 seconds
Started Dec 20 12:40:48 PM PST 23
Finished Dec 20 12:42:57 PM PST 23
Peak memory 239588 kb
Host smart-800780d3-f578-4046-966d-6a5163fa7f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3792039115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3792039115
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3271927418
Short name T259
Test name
Test status
Simulation time 12594101 ps
CPU time 1.6 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:41:13 PM PST 23
Peak memory 236480 kb
Host smart-7f4817ff-9978-4b46-8a2e-cd21c5f54492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3271927418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3271927418
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1306322388
Short name T71
Test name
Test status
Simulation time 172043906727 ps
CPU time 2679.85 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 01:41:58 PM PST 23
Peak memory 289496 kb
Host smart-ef779283-e823-4c62-ac44-91ee8447965b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306322388 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1306322388
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.232753126
Short name T299
Test name
Test status
Simulation time 5830412794 ps
CPU time 305.39 seconds
Started Dec 20 12:57:58 PM PST 23
Finished Dec 20 01:03:18 PM PST 23
Peak memory 252036 kb
Host smart-e85c3854-eb45-41df-be55-63c1ae131370
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232753126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.232753126
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.876642152
Short name T335
Test name
Test status
Simulation time 5457704485 ps
CPU time 221.64 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 01:01:31 PM PST 23
Peak memory 247712 kb
Host smart-c8fb5c1f-e908-4769-adef-d83e9d3ed336
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876642152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.876642152
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3060290724
Short name T282
Test name
Test status
Simulation time 131131491913 ps
CPU time 2015.73 seconds
Started Dec 20 12:56:47 PM PST 23
Finished Dec 20 01:30:27 PM PST 23
Peak memory 281592 kb
Host smart-ade656a3-807d-4eb3-903d-7b72b7766f3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060290724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3060290724
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.145789250
Short name T253
Test name
Test status
Simulation time 43451361851 ps
CPU time 454.29 seconds
Started Dec 20 12:58:18 PM PST 23
Finished Dec 20 01:06:10 PM PST 23
Peak memory 247368 kb
Host smart-7353621e-c36b-4958-b41b-94ef6b35eb71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145789250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.145789250
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3339983740
Short name T306
Test name
Test status
Simulation time 213255734448 ps
CPU time 1917.45 seconds
Started Dec 20 12:58:35 PM PST 23
Finished Dec 20 01:30:50 PM PST 23
Peak memory 289744 kb
Host smart-adbb68a0-23c4-46f1-8041-1de44c7c60d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339983740 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3339983740
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1189400776
Short name T267
Test name
Test status
Simulation time 159571388329 ps
CPU time 3844.37 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 02:01:31 PM PST 23
Peak memory 330768 kb
Host smart-a3a67cc0-4230-4706-af84-9f4355c1eb80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189400776 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1189400776
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.665156925
Short name T155
Test name
Test status
Simulation time 4757513253 ps
CPU time 307.51 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:46:05 PM PST 23
Peak memory 265416 kb
Host smart-f38d772c-fff9-4333-b2c2-65dd08717e0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=665156925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.665156925
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3985520654
Short name T356
Test name
Test status
Simulation time 42471915875 ps
CPU time 518.47 seconds
Started Dec 20 12:40:34 PM PST 23
Finished Dec 20 12:50:16 PM PST 23
Peak memory 265512 kb
Host smart-31ae8bfa-6196-45c1-80eb-5b68325c5a8a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985520654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3985520654
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1927976201
Short name T492
Test name
Test status
Simulation time 159104953137 ps
CPU time 6923.71 seconds
Started Dec 20 12:56:36 PM PST 23
Finished Dec 20 02:52:06 PM PST 23
Peak memory 371184 kb
Host smart-7fd29fad-95af-4baa-97c5-02ff7c5d5bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927976201 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1927976201
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2258676708
Short name T302
Test name
Test status
Simulation time 999836217 ps
CPU time 17.39 seconds
Started Dec 20 12:57:08 PM PST 23
Finished Dec 20 12:57:41 PM PST 23
Peak memory 252796 kb
Host smart-2b6b248b-b711-4cbd-a576-a4934d662414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
76708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2258676708
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.235357204
Short name T311
Test name
Test status
Simulation time 364300073742 ps
CPU time 5759.63 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 02:33:30 PM PST 23
Peak memory 338676 kb
Host smart-c8a0f085-2bd2-4972-9fe9-39767f590a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235357204 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.235357204
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.684493666
Short name T308
Test name
Test status
Simulation time 4692364068 ps
CPU time 42.74 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:58:38 PM PST 23
Peak memory 248760 kb
Host smart-3fdbf1f3-64d4-4a71-a3f1-a814fa7942a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68449
3666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.684493666
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1298243807
Short name T262
Test name
Test status
Simulation time 20529439938 ps
CPU time 1246.89 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 01:17:51 PM PST 23
Peak memory 272092 kb
Host smart-83586b48-959e-4f5c-a3f2-a7482dee4a25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298243807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1298243807
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3641135748
Short name T92
Test name
Test status
Simulation time 26595445865 ps
CPU time 1203.15 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 01:17:55 PM PST 23
Peak memory 285560 kb
Host smart-67fc9c8b-90d4-43a0-8fbc-8d67e6e7be8d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641135748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3641135748
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4229085952
Short name T284
Test name
Test status
Simulation time 308579609829 ps
CPU time 3747.65 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 01:59:48 PM PST 23
Peak memory 338876 kb
Host smart-402f25a7-2f32-4228-92e8-5774ef54e81f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229085952 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4229085952
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1803005339
Short name T40
Test name
Test status
Simulation time 30492910536 ps
CPU time 582.89 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 01:06:39 PM PST 23
Peak memory 273528 kb
Host smart-c35028c0-5f36-4f78-bc29-384650751b04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803005339 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1803005339
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.705306495
Short name T158
Test name
Test status
Simulation time 14545018086 ps
CPU time 282.66 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:45:51 PM PST 23
Peak memory 265396 kb
Host smart-a7863c37-4f01-49c3-bd8b-82e72480d37a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=705306495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.705306495
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2834478876
Short name T197
Test name
Test status
Simulation time 4552727482 ps
CPU time 80.05 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:42:59 PM PST 23
Peak memory 245996 kb
Host smart-9d76052f-05bd-4c85-998a-9972a5729801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2834478876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2834478876
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3940033338
Short name T203
Test name
Test status
Simulation time 978134528 ps
CPU time 39.63 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:41:43 PM PST 23
Peak memory 240448 kb
Host smart-a6d4f6fb-3837-46fa-8e9b-aaf028862f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3940033338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3940033338
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.247068855
Short name T201
Test name
Test status
Simulation time 360543622 ps
CPU time 35.85 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 236696 kb
Host smart-a90aee8c-c488-4a97-b52c-4e3497fb1591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=247068855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.247068855
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3526455911
Short name T198
Test name
Test status
Simulation time 61314876 ps
CPU time 2.07 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:41:04 PM PST 23
Peak memory 236876 kb
Host smart-6e915c0e-7d5a-4d3b-9c5a-3197a84e4afe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3526455911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3526455911
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3342044228
Short name T183
Test name
Test status
Simulation time 2238115644 ps
CPU time 231.85 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 12:45:06 PM PST 23
Peak memory 265516 kb
Host smart-a36096b5-f204-41ea-b041-30771aa9b744
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3342044228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3342044228
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2270837516
Short name T204
Test name
Test status
Simulation time 361839022 ps
CPU time 41.28 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:42:27 PM PST 23
Peak memory 236460 kb
Host smart-3bd36e18-7baf-44ec-abc1-49b7e6345c89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2270837516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2270837516
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2130958958
Short name T208
Test name
Test status
Simulation time 449236819 ps
CPU time 28.01 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 12:41:42 PM PST 23
Peak memory 245824 kb
Host smart-87e714d6-2992-4368-8205-ee856bf22366
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2130958958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2130958958
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3229561382
Short name T200
Test name
Test status
Simulation time 455289602 ps
CPU time 30.39 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:42:10 PM PST 23
Peak memory 248040 kb
Host smart-060afac3-6873-4406-afc5-fef5cc40f50c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3229561382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3229561382
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3372696427
Short name T206
Test name
Test status
Simulation time 3682716131 ps
CPU time 64.76 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 240460 kb
Host smart-e8ed3ffd-3cea-42f7-ac9e-23b740588e24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3372696427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3372696427
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3934433298
Short name T162
Test name
Test status
Simulation time 1088294650 ps
CPU time 107.96 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:43:21 PM PST 23
Peak memory 257176 kb
Host smart-607b156b-71b4-4441-9cea-7bdd4049d9f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3934433298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3934433298
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2308622108
Short name T209
Test name
Test status
Simulation time 128293508 ps
CPU time 2.65 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 236516 kb
Host smart-c8a6b677-f80b-4418-b15f-656613183a58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2308622108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2308622108
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3224062328
Short name T37
Test name
Test status
Simulation time 83919946169 ps
CPU time 1600.38 seconds
Started Dec 20 12:57:40 PM PST 23
Finished Dec 20 01:24:42 PM PST 23
Peak memory 272516 kb
Host smart-004691bd-0ca9-4160-9972-81f2783677a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224062328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3224062328
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1066044979
Short name T754
Test name
Test status
Simulation time 1732258881 ps
CPU time 104.49 seconds
Started Dec 20 12:40:11 PM PST 23
Finished Dec 20 12:42:55 PM PST 23
Peak memory 236644 kb
Host smart-67bb83b4-12c3-4f1a-9925-aaf5ebc5222c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1066044979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1066044979
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2587685204
Short name T794
Test name
Test status
Simulation time 864443995 ps
CPU time 104.6 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 240452 kb
Host smart-f7e947e7-a955-499a-8e53-56c5dc3f9af4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2587685204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2587685204
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.722018267
Short name T358
Test name
Test status
Simulation time 82090559 ps
CPU time 5.5 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:45 PM PST 23
Peak memory 240392 kb
Host smart-5ce9ba4f-ae3d-4c22-8d70-75de5d72e368
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=722018267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.722018267
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3154955799
Short name T789
Test name
Test status
Simulation time 33853024 ps
CPU time 3.74 seconds
Started Dec 20 12:40:03 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 240416 kb
Host smart-2564e17b-5f14-4224-8152-245698e139bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154955799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3154955799
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4039573805
Short name T179
Test name
Test status
Simulation time 237516187 ps
CPU time 8.56 seconds
Started Dec 20 12:40:09 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 236356 kb
Host smart-70168df1-4411-4dde-8a1c-fb747d2873c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4039573805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4039573805
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1069462502
Short name T802
Test name
Test status
Simulation time 19931715 ps
CPU time 1.9 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:40:56 PM PST 23
Peak memory 235624 kb
Host smart-dbbda044-fa5c-4deb-891f-a34e826fee2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1069462502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1069462502
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.969342610
Short name T833
Test name
Test status
Simulation time 337826540 ps
CPU time 18.96 seconds
Started Dec 20 12:40:16 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 243692 kb
Host smart-5633c07f-2745-4016-a5dd-d3eea5b90b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=969342610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.969342610
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3942098462
Short name T836
Test name
Test status
Simulation time 109357846 ps
CPU time 11.92 seconds
Started Dec 20 12:39:59 PM PST 23
Finished Dec 20 12:41:13 PM PST 23
Peak memory 253644 kb
Host smart-84ca3397-25bf-43af-94e5-7c33cb63281b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3942098462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3942098462
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3216126798
Short name T841
Test name
Test status
Simulation time 4580140854 ps
CPU time 150.41 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:43:36 PM PST 23
Peak memory 238660 kb
Host smart-3058f4d8-fb06-440a-a661-2bda1cf1789d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3216126798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3216126798
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1685454464
Short name T31
Test name
Test status
Simulation time 823031353 ps
CPU time 85.85 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:43:06 PM PST 23
Peak memory 235884 kb
Host smart-6aa34aea-8991-4067-9468-f19909eafa83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1685454464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1685454464
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1436346921
Short name T826
Test name
Test status
Simulation time 76866299 ps
CPU time 3.64 seconds
Started Dec 20 12:40:44 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 240388 kb
Host smart-0d1bb1e6-e862-4237-a409-5eadbb64f5bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1436346921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1436346921
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2952266438
Short name T752
Test name
Test status
Simulation time 149758576 ps
CPU time 6.53 seconds
Started Dec 20 12:40:06 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 251924 kb
Host smart-6adc2b91-4fcd-41a6-8677-e77956f9ebeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952266438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2952266438
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1391903323
Short name T758
Test name
Test status
Simulation time 61196368 ps
CPU time 4.71 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:41:13 PM PST 23
Peak memory 240300 kb
Host smart-a838a7fd-58fe-4844-b6ed-1e26b85e6c4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1391903323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1391903323
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1757773481
Short name T797
Test name
Test status
Simulation time 8056994 ps
CPU time 1.23 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 234016 kb
Host smart-9359156a-b2eb-4b73-8c74-0eb183c68247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1757773481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1757773481
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2828292640
Short name T216
Test name
Test status
Simulation time 1505805161 ps
CPU time 21.11 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:41:31 PM PST 23
Peak memory 240492 kb
Host smart-55b43ab7-836d-4657-ac4a-7c9e5ad0e54f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2828292640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2828292640
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4183998834
Short name T184
Test name
Test status
Simulation time 11711577907 ps
CPU time 438.21 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:48:33 PM PST 23
Peak memory 265408 kb
Host smart-99fa81b6-1bcb-4a82-aeae-a9a1a355c3e7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183998834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4183998834
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1733686619
Short name T792
Test name
Test status
Simulation time 487116877 ps
CPU time 9.13 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:41:33 PM PST 23
Peak memory 248028 kb
Host smart-a86d1119-b1ed-4dcf-8afd-7cace09f462a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1733686619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1733686619
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1438804714
Short name T202
Test name
Test status
Simulation time 893640105 ps
CPU time 68.25 seconds
Started Dec 20 12:40:40 PM PST 23
Finished Dec 20 12:42:51 PM PST 23
Peak memory 236580 kb
Host smart-edba3b95-a4b6-4f37-b01f-1e2d9bf6aca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1438804714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1438804714
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.346598081
Short name T823
Test name
Test status
Simulation time 29519581 ps
CPU time 5.82 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 256584 kb
Host smart-a171c601-4796-4d28-a336-2b6370210b82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346598081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.346598081
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.285572825
Short name T741
Test name
Test status
Simulation time 172488616 ps
CPU time 4.79 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:41:49 PM PST 23
Peak memory 236432 kb
Host smart-c3da188d-c2b5-47f3-b716-9bc48f881b73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=285572825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.285572825
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3653514319
Short name T746
Test name
Test status
Simulation time 12378792 ps
CPU time 1.6 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:41:10 PM PST 23
Peak memory 235676 kb
Host smart-c61e183e-4f0d-40b6-9c08-b4f4c16325a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3653514319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3653514319
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4019109058
Short name T191
Test name
Test status
Simulation time 167670829 ps
CPU time 22.29 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 244764 kb
Host smart-d510ff7c-9165-4d2c-972b-787b203a501a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4019109058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4019109058
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2100647823
Short name T753
Test name
Test status
Simulation time 1242826661 ps
CPU time 9.14 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 251796 kb
Host smart-e80bed65-9c92-4d91-975d-34111fb6f260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2100647823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2100647823
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.190126412
Short name T748
Test name
Test status
Simulation time 38371364 ps
CPU time 6.84 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:21 PM PST 23
Peak memory 251868 kb
Host smart-266feca0-6050-4302-be62-616435fb2616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190126412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.190126412
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4255493109
Short name T824
Test name
Test status
Simulation time 52307538 ps
CPU time 4.51 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 236532 kb
Host smart-fc02dcfe-47a1-4729-b85b-4cbf972908fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4255493109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4255493109
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3922105717
Short name T349
Test name
Test status
Simulation time 19133157 ps
CPU time 1.31 seconds
Started Dec 20 12:40:38 PM PST 23
Finished Dec 20 12:41:43 PM PST 23
Peak memory 236020 kb
Host smart-8c2a16e1-85ad-4abf-80ec-50a5866b8f79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3922105717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3922105717
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3182624279
Short name T213
Test name
Test status
Simulation time 419529198 ps
CPU time 20.09 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:42:00 PM PST 23
Peak memory 248024 kb
Host smart-c715cdd6-b989-438b-966e-5062a02b4f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3182624279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3182624279
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1814870752
Short name T161
Test name
Test status
Simulation time 9377507112 ps
CPU time 153.17 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:44:18 PM PST 23
Peak memory 266872 kb
Host smart-5c6f558c-0c37-42c8-8434-cd2ff345f2a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1814870752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1814870752
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2256998598
Short name T159
Test name
Test status
Simulation time 20515910470 ps
CPU time 575.25 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:50:56 PM PST 23
Peak memory 273464 kb
Host smart-9f41c829-f24b-49a7-addd-03296bdad7cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256998598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2256998598
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1281417881
Short name T777
Test name
Test status
Simulation time 721589861 ps
CPU time 11.58 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:31 PM PST 23
Peak memory 248672 kb
Host smart-bbb9ceb5-1fac-4e53-8dd8-7d3b325f3d20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1281417881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1281417881
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1388976859
Short name T187
Test name
Test status
Simulation time 204365640 ps
CPU time 2.28 seconds
Started Dec 20 12:40:40 PM PST 23
Finished Dec 20 12:41:45 PM PST 23
Peak memory 236000 kb
Host smart-4084a164-56cd-4027-9d30-b7117f747bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1388976859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1388976859
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2970207939
Short name T760
Test name
Test status
Simulation time 238220964 ps
CPU time 7 seconds
Started Dec 20 12:40:21 PM PST 23
Finished Dec 20 12:41:28 PM PST 23
Peak memory 251784 kb
Host smart-12e305aa-7642-4b53-8a98-7259b6db878c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970207939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2970207939
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.437770933
Short name T846
Test name
Test status
Simulation time 63434951 ps
CPU time 5.53 seconds
Started Dec 20 12:40:38 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 236388 kb
Host smart-85966783-0cca-4daa-834f-463a31ae16da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=437770933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.437770933
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3122832021
Short name T816
Test name
Test status
Simulation time 8719126 ps
CPU time 1.4 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:21 PM PST 23
Peak memory 234596 kb
Host smart-d5efdba7-bc2a-4113-b08a-60045ac07dc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3122832021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3122832021
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1122892570
Short name T30
Test name
Test status
Simulation time 327779822 ps
CPU time 20.42 seconds
Started Dec 20 12:40:38 PM PST 23
Finished Dec 20 12:42:01 PM PST 23
Peak memory 243848 kb
Host smart-1fe76ab4-1194-489e-942c-d7ee7c7cbb28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1122892570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1122892570
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4238183573
Short name T157
Test name
Test status
Simulation time 10359789240 ps
CPU time 300.57 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:46:28 PM PST 23
Peak memory 265508 kb
Host smart-15bfa4b2-3e8e-4611-817e-cf891a226083
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4238183573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4238183573
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3684237618
Short name T766
Test name
Test status
Simulation time 77868756 ps
CPU time 5 seconds
Started Dec 20 12:40:12 PM PST 23
Finished Dec 20 12:41:23 PM PST 23
Peak memory 248700 kb
Host smart-cd7bc7a3-a35d-4259-8819-cfb0d70a4b36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3684237618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3684237618
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2410077089
Short name T211
Test name
Test status
Simulation time 54544950 ps
CPU time 2.5 seconds
Started Dec 20 12:40:28 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 236856 kb
Host smart-5c5f8114-c604-4f6f-90f8-5ccb1ec473d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2410077089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2410077089
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3915941527
Short name T808
Test name
Test status
Simulation time 69025603 ps
CPU time 6.02 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:21 PM PST 23
Peak memory 251748 kb
Host smart-32adfa35-72eb-4521-9321-cd040ca3f384
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915941527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3915941527
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1601930719
Short name T845
Test name
Test status
Simulation time 50778387 ps
CPU time 4.41 seconds
Started Dec 20 12:40:33 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 238676 kb
Host smart-a07c8cb9-41e0-49e0-8f66-b511efbc8b8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1601930719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1601930719
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3379261700
Short name T190
Test name
Test status
Simulation time 273912641 ps
CPU time 19.25 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 244700 kb
Host smart-8ed688ba-e8df-4c19-aa6d-ec22d668e755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3379261700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3379261700
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4066098007
Short name T171
Test name
Test status
Simulation time 4572266739 ps
CPU time 272.43 seconds
Started Dec 20 12:40:17 PM PST 23
Finished Dec 20 12:45:59 PM PST 23
Peak memory 271196 kb
Host smart-c6d21223-ea20-49e1-974f-a27182276a19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4066098007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4066098007
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.561364800
Short name T195
Test name
Test status
Simulation time 693514396 ps
CPU time 9.18 seconds
Started Dec 20 12:40:11 PM PST 23
Finished Dec 20 12:41:21 PM PST 23
Peak memory 248564 kb
Host smart-b2f62b13-5148-4614-983d-31c82c163bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=561364800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.561364800
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2133475951
Short name T215
Test name
Test status
Simulation time 62960398 ps
CPU time 2.72 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 236532 kb
Host smart-310de7b1-6893-47e9-b9af-2a6513bdd667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2133475951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2133475951
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2264087070
Short name T839
Test name
Test status
Simulation time 581491706 ps
CPU time 5.96 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 250820 kb
Host smart-0c932b6c-be74-4a35-8a04-b0fb35dbd3f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264087070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2264087070
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1114814800
Short name T795
Test name
Test status
Simulation time 126847125 ps
CPU time 9.36 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 236536 kb
Host smart-7e8f5525-68ee-484e-be14-6cfd0a42b9e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1114814800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1114814800
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.464233400
Short name T781
Test name
Test status
Simulation time 8119849 ps
CPU time 1.28 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 236404 kb
Host smart-742c425a-60ac-4439-8277-698daad690f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=464233400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.464233400
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1607348319
Short name T785
Test name
Test status
Simulation time 320455871 ps
CPU time 11.12 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:41:32 PM PST 23
Peak memory 244688 kb
Host smart-85800f01-9371-4878-a80e-0c986e8895eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1607348319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1607348319
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2317030923
Short name T168
Test name
Test status
Simulation time 8648060577 ps
CPU time 507.3 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:50:13 PM PST 23
Peak memory 265508 kb
Host smart-7590817e-70d1-4b38-9ad3-c5d1fc6533ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317030923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2317030923
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.413856257
Short name T812
Test name
Test status
Simulation time 548907914 ps
CPU time 9.66 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 248684 kb
Host smart-a0ce1578-c21a-41b0-a19d-c3bf796bbf68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=413856257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.413856257
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.467066123
Short name T804
Test name
Test status
Simulation time 23624109 ps
CPU time 2.45 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:23 PM PST 23
Peak memory 236576 kb
Host smart-379d412c-9c4f-42b3-8f7d-e5846e1d989d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=467066123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.467066123
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.206609872
Short name T194
Test name
Test status
Simulation time 74627638 ps
CPU time 3.93 seconds
Started Dec 20 12:40:55 PM PST 23
Finished Dec 20 12:42:03 PM PST 23
Peak memory 256796 kb
Host smart-4a34b49c-a7b4-4f20-a1cf-514bf40064a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206609872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.206609872
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2461722549
Short name T744
Test name
Test status
Simulation time 373560114 ps
CPU time 5.12 seconds
Started Dec 20 12:40:29 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 240352 kb
Host smart-7de2c727-77b7-4ce5-9409-f825e2b473a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2461722549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2461722549
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1063453311
Short name T849
Test name
Test status
Simulation time 7587423 ps
CPU time 1.35 seconds
Started Dec 20 12:40:29 PM PST 23
Finished Dec 20 12:41:36 PM PST 23
Peak memory 235720 kb
Host smart-877fdf2e-d2f1-446c-8c5f-2a98f72c3ec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1063453311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1063453311
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2446699611
Short name T784
Test name
Test status
Simulation time 3277557787 ps
CPU time 40.96 seconds
Started Dec 20 12:40:38 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 248704 kb
Host smart-385c0be0-508d-435c-aec5-3df47e7694d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2446699611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2446699611
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.475974610
Short name T188
Test name
Test status
Simulation time 7184579066 ps
CPU time 311.01 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:46:35 PM PST 23
Peak memory 269212 kb
Host smart-cb9b3e02-9404-4592-947b-dde2fef298c2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475974610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.475974610
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2460334993
Short name T147
Test name
Test status
Simulation time 90761963 ps
CPU time 10.21 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:42:15 PM PST 23
Peak memory 247480 kb
Host smart-47d1215e-6be3-4cda-b6e2-47fedda6aac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2460334993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2460334993
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1726221788
Short name T848
Test name
Test status
Simulation time 59121627 ps
CPU time 5.99 seconds
Started Dec 20 12:40:39 PM PST 23
Finished Dec 20 12:41:47 PM PST 23
Peak memory 243524 kb
Host smart-a599c947-58e4-4cd1-b45f-3a91c28399b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726221788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1726221788
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1689789410
Short name T817
Test name
Test status
Simulation time 19485886 ps
CPU time 3.28 seconds
Started Dec 20 12:40:44 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 239588 kb
Host smart-d7955fe0-4cde-4d86-943f-d81bdce4c9c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1689789410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1689789410
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2152912617
Short name T761
Test name
Test status
Simulation time 7314540 ps
CPU time 1.26 seconds
Started Dec 20 12:40:17 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 236480 kb
Host smart-cd7dc872-3dd9-462d-a324-a364aad1407a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2152912617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2152912617
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3674620756
Short name T218
Test name
Test status
Simulation time 764847871 ps
CPU time 39.73 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 248680 kb
Host smart-89a1d261-1a21-404d-afab-137d59b0d53e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3674620756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3674620756
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4079276347
Short name T167
Test name
Test status
Simulation time 2173805620 ps
CPU time 303.67 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:46:24 PM PST 23
Peak memory 265408 kb
Host smart-80f99c4e-79a1-47f6-a49d-f26731421c5a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079276347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4079276347
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2847094186
Short name T768
Test name
Test status
Simulation time 689859021 ps
CPU time 12.66 seconds
Started Dec 20 12:40:39 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 248320 kb
Host smart-5eea21c6-f194-4f90-acfa-2d25d23c95a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2847094186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2847094186
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.552403510
Short name T34
Test name
Test status
Simulation time 26739536 ps
CPU time 3.9 seconds
Started Dec 20 12:40:31 PM PST 23
Finished Dec 20 12:41:48 PM PST 23
Peak memory 255704 kb
Host smart-c3eaa19c-fe71-4289-872b-0fd38f97e694
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552403510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.552403510
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.961470200
Short name T757
Test name
Test status
Simulation time 122275836 ps
CPU time 5.06 seconds
Started Dec 20 12:40:16 PM PST 23
Finished Dec 20 12:41:21 PM PST 23
Peak memory 236536 kb
Host smart-9fe4243f-850c-4f2d-b650-f95721733670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=961470200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.961470200
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2464216645
Short name T192
Test name
Test status
Simulation time 11313451 ps
CPU time 1.62 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 235680 kb
Host smart-12f013b6-3dac-42df-9b65-8b2b4c2e0dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2464216645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2464216645
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.876336596
Short name T152
Test name
Test status
Simulation time 1202930979 ps
CPU time 17.6 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:41:50 PM PST 23
Peak memory 243720 kb
Host smart-92713117-bd34-4090-9507-06fa634bc50d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=876336596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.876336596
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.582239904
Short name T770
Test name
Test status
Simulation time 122323314 ps
CPU time 8.24 seconds
Started Dec 20 12:40:55 PM PST 23
Finished Dec 20 12:42:08 PM PST 23
Peak memory 248768 kb
Host smart-52490660-2ce1-40be-9384-a4cd72c7afd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=582239904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.582239904
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1461068299
Short name T189
Test name
Test status
Simulation time 7752757940 ps
CPU time 79.19 seconds
Started Dec 20 12:40:59 PM PST 23
Finished Dec 20 12:43:23 PM PST 23
Peak memory 246172 kb
Host smart-97cf912f-4441-4bf5-a131-bb32a4119049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1461068299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1461068299
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2951836274
Short name T186
Test name
Test status
Simulation time 276432645 ps
CPU time 6.99 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 252192 kb
Host smart-c682ec78-a355-4598-8db7-1c336593f082
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951836274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2951836274
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3261128378
Short name T755
Test name
Test status
Simulation time 166519240 ps
CPU time 4.22 seconds
Started Dec 20 12:40:49 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 238632 kb
Host smart-c9bacfa2-5957-455e-b491-15eb490e9927
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3261128378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3261128378
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3778919602
Short name T796
Test name
Test status
Simulation time 12330057 ps
CPU time 1.17 seconds
Started Dec 20 12:41:07 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 236548 kb
Host smart-6b2ebc09-f112-468c-ad1e-19b4f92021f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3778919602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3778919602
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.473238442
Short name T214
Test name
Test status
Simulation time 1997943924 ps
CPU time 18.36 seconds
Started Dec 20 12:41:04 PM PST 23
Finished Dec 20 12:42:25 PM PST 23
Peak memory 243892 kb
Host smart-41656232-01a7-4294-9118-8846eb09c51e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=473238442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.473238442
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.8899085
Short name T170
Test name
Test status
Simulation time 1860189606 ps
CPU time 144.25 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:43:55 PM PST 23
Peak memory 265472 kb
Host smart-11f1d8f2-cc27-4dc0-b972-d7300f4d4c98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=8899085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.8899085
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.184475729
Short name T357
Test name
Test status
Simulation time 9148861272 ps
CPU time 550.64 seconds
Started Dec 20 12:41:00 PM PST 23
Finished Dec 20 12:51:15 PM PST 23
Peak memory 267544 kb
Host smart-4ddd8984-b8a5-43f8-840e-3da68c4e119c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184475729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.184475729
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1140515158
Short name T828
Test name
Test status
Simulation time 755261957 ps
CPU time 8.05 seconds
Started Dec 20 12:41:16 PM PST 23
Finished Dec 20 12:42:28 PM PST 23
Peak memory 252916 kb
Host smart-a569398a-3970-4483-8198-65c26bb78718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1140515158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1140515158
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.250789069
Short name T799
Test name
Test status
Simulation time 30771423 ps
CPU time 5.8 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:57 PM PST 23
Peak memory 253088 kb
Host smart-ab6347ec-b455-4378-abcf-8d0b5b5d951c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250789069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.250789069
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1665252585
Short name T837
Test name
Test status
Simulation time 129442763 ps
CPU time 4.75 seconds
Started Dec 20 12:40:23 PM PST 23
Finished Dec 20 12:41:26 PM PST 23
Peak memory 235620 kb
Host smart-6710a45c-3a09-4239-b42a-ab3fc95ecefa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1665252585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1665252585
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2353606902
Short name T815
Test name
Test status
Simulation time 14568093 ps
CPU time 1.5 seconds
Started Dec 20 12:41:11 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 236560 kb
Host smart-1d8cf113-94ed-470f-bb28-3a72e930b1ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2353606902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2353606902
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3524022223
Short name T767
Test name
Test status
Simulation time 87826220 ps
CPU time 10.86 seconds
Started Dec 20 12:40:46 PM PST 23
Finished Dec 20 12:42:00 PM PST 23
Peak memory 244700 kb
Host smart-6962acb8-a821-4b71-b4d4-fe2a3b2adf73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3524022223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3524022223
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4115184917
Short name T173
Test name
Test status
Simulation time 1199172639 ps
CPU time 118.31 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 257128 kb
Host smart-d8da892c-bc7c-4ca1-a65e-7ddd088b2021
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115184917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4115184917
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3059527209
Short name T798
Test name
Test status
Simulation time 611196511 ps
CPU time 13.48 seconds
Started Dec 20 12:40:46 PM PST 23
Finished Dec 20 12:42:03 PM PST 23
Peak memory 248632 kb
Host smart-daaf33ba-d6a5-4976-9e11-15fb90ff1c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3059527209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3059527209
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.288026669
Short name T764
Test name
Test status
Simulation time 1652973471 ps
CPU time 111.33 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:43:15 PM PST 23
Peak memory 236556 kb
Host smart-29770842-d44e-4ff6-ac57-ca3aa291e19a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=288026669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.288026669
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1958694379
Short name T809
Test name
Test status
Simulation time 3714753539 ps
CPU time 97.35 seconds
Started Dec 20 12:40:20 PM PST 23
Finished Dec 20 12:42:56 PM PST 23
Peak memory 236380 kb
Host smart-a55f0eba-0b6a-4f2e-8dbd-b0608e402658
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1958694379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1958694379
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3292183677
Short name T359
Test name
Test status
Simulation time 66823933 ps
CPU time 5.12 seconds
Started Dec 20 12:39:55 PM PST 23
Finished Dec 20 12:41:08 PM PST 23
Peak memory 240344 kb
Host smart-6be3d343-8f37-4bd8-a8d4-bbd4e7c627bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3292183677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3292183677
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.817253936
Short name T258
Test name
Test status
Simulation time 47670901 ps
CPU time 3.12 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 240516 kb
Host smart-cb13469b-cf54-469b-b867-c1b50295cc8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817253936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.817253936
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3674637974
Short name T822
Test name
Test status
Simulation time 125546746 ps
CPU time 8.03 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:41:15 PM PST 23
Peak memory 240300 kb
Host smart-fb5c7556-a05a-454b-add9-5865a729461d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3674637974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3674637974
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3536281699
Short name T217
Test name
Test status
Simulation time 1276272454 ps
CPU time 38.6 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 244704 kb
Host smart-a0904fb6-d8fb-45ee-a010-4d6d182a5c70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3536281699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3536281699
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3956339401
Short name T166
Test name
Test status
Simulation time 8260661617 ps
CPU time 269.54 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:46:04 PM PST 23
Peak memory 265464 kb
Host smart-17009f50-dbd4-45a1-871c-77d56269d98a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3956339401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3956339401
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1888826223
Short name T185
Test name
Test status
Simulation time 46058411560 ps
CPU time 543.62 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:50:03 PM PST 23
Peak memory 269052 kb
Host smart-cfc3f14a-78c8-4b28-a45e-70024b8cd84a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888826223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1888826223
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.300957772
Short name T825
Test name
Test status
Simulation time 55140530 ps
CPU time 7.14 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 12:41:21 PM PST 23
Peak memory 248144 kb
Host smart-9c5aa070-53e2-4b0e-87f8-c5d158f36125
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=300957772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.300957772
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.225910445
Short name T751
Test name
Test status
Simulation time 15119260 ps
CPU time 1.25 seconds
Started Dec 20 12:40:12 PM PST 23
Finished Dec 20 12:41:15 PM PST 23
Peak memory 236404 kb
Host smart-d9ab39fc-4d09-4b98-b820-55b813c04ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=225910445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.225910445
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.588076485
Short name T745
Test name
Test status
Simulation time 15360795 ps
CPU time 1.31 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 235604 kb
Host smart-3bf4dbf9-92d8-4c43-8d40-6aa0429ed0c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=588076485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.588076485
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3928866826
Short name T212
Test name
Test status
Simulation time 10507595 ps
CPU time 1.21 seconds
Started Dec 20 12:40:11 PM PST 23
Finished Dec 20 12:41:12 PM PST 23
Peak memory 236480 kb
Host smart-dbb818bd-8c6c-4e0e-9c68-9419ae9476a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3928866826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3928866826
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1133536385
Short name T763
Test name
Test status
Simulation time 35888093 ps
CPU time 1.4 seconds
Started Dec 20 12:40:15 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 236392 kb
Host smart-9fa3b131-8557-4998-9f06-ac4325b683ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1133536385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1133536385
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3653341358
Short name T830
Test name
Test status
Simulation time 7627823 ps
CPU time 1.19 seconds
Started Dec 20 12:41:34 PM PST 23
Finished Dec 20 12:42:39 PM PST 23
Peak memory 235940 kb
Host smart-b708b7c2-fea1-4a16-b274-1f9afa822021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3653341358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3653341358
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1051535564
Short name T834
Test name
Test status
Simulation time 6924738 ps
CPU time 1.25 seconds
Started Dec 20 12:40:16 PM PST 23
Finished Dec 20 12:41:16 PM PST 23
Peak memory 234584 kb
Host smart-1272fdda-be67-4bfd-8c72-18066bfb55f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1051535564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1051535564
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.589813672
Short name T820
Test name
Test status
Simulation time 30033038 ps
CPU time 2.12 seconds
Started Dec 20 12:40:52 PM PST 23
Finished Dec 20 12:41:58 PM PST 23
Peak memory 234744 kb
Host smart-7bf8bfcf-8591-4cd1-92e4-69c57f3e482c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=589813672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.589813672
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.30618881
Short name T819
Test name
Test status
Simulation time 14947771 ps
CPU time 1.44 seconds
Started Dec 20 12:40:40 PM PST 23
Finished Dec 20 12:41:44 PM PST 23
Peak memory 235656 kb
Host smart-f293dee3-4908-45a7-9076-533b8151e185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=30618881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.30618881
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4002433376
Short name T762
Test name
Test status
Simulation time 7962357 ps
CPU time 1.31 seconds
Started Dec 20 12:40:47 PM PST 23
Finished Dec 20 12:41:52 PM PST 23
Peak memory 236408 kb
Host smart-398f6b06-a6c5-42d0-b433-ef8c7fd6bee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4002433376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4002433376
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.548181479
Short name T772
Test name
Test status
Simulation time 624507735 ps
CPU time 72.69 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:42:22 PM PST 23
Peak memory 240352 kb
Host smart-1c820a6d-96f2-4303-97c2-c217ffb7eff2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=548181479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.548181479
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.561970802
Short name T28
Test name
Test status
Simulation time 13603975219 ps
CPU time 99.97 seconds
Started Dec 20 12:40:31 PM PST 23
Finished Dec 20 12:43:13 PM PST 23
Peak memory 236448 kb
Host smart-d8b58ab4-f69e-434b-8bea-0be1c82f26bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=561970802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.561970802
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3945809684
Short name T801
Test name
Test status
Simulation time 429675259 ps
CPU time 7.68 seconds
Started Dec 20 12:40:19 PM PST 23
Finished Dec 20 12:41:26 PM PST 23
Peak memory 240412 kb
Host smart-b6a5734e-e37d-44f8-8317-ec4cf65041a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3945809684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3945809684
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4293094667
Short name T805
Test name
Test status
Simulation time 98940434 ps
CPU time 3.45 seconds
Started Dec 20 12:40:05 PM PST 23
Finished Dec 20 12:41:13 PM PST 23
Peak memory 236592 kb
Host smart-515393cb-7e5b-41ce-975f-74f0e056590f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293094667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4293094667
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2347359923
Short name T769
Test name
Test status
Simulation time 32867254 ps
CPU time 4.76 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:45 PM PST 23
Peak memory 235968 kb
Host smart-2941a7dc-f539-4561-8185-3785c201b083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2347359923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2347359923
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.344909214
Short name T355
Test name
Test status
Simulation time 10375273 ps
CPU time 1.18 seconds
Started Dec 20 12:40:37 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 235848 kb
Host smart-97e6f44d-033e-48a4-b496-5c1a29c31c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=344909214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.344909214
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.4198520934
Short name T814
Test name
Test status
Simulation time 773442617 ps
CPU time 35.48 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:41:47 PM PST 23
Peak memory 243812 kb
Host smart-27f76647-c4e3-4063-a789-b8385b9bfacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4198520934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.4198520934
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.440111273
Short name T181
Test name
Test status
Simulation time 3370452735 ps
CPU time 111.67 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:42:53 PM PST 23
Peak memory 265296 kb
Host smart-f9598da2-01c7-4487-ab1f-107d6cab7369
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=440111273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.440111273
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2020169396
Short name T180
Test name
Test status
Simulation time 22043879294 ps
CPU time 255.45 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 12:45:23 PM PST 23
Peak memory 268136 kb
Host smart-59618efa-d208-44b9-b637-e73eea93d35a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020169396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2020169396
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3130402429
Short name T818
Test name
Test status
Simulation time 213131024 ps
CPU time 12.74 seconds
Started Dec 20 12:40:07 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 253008 kb
Host smart-0f3b7b63-d8e3-413d-9866-d5a02f4e20d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3130402429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3130402429
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.410372955
Short name T352
Test name
Test status
Simulation time 7426510 ps
CPU time 1.44 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 236552 kb
Host smart-6e31717b-8ed7-46db-b1ec-de29c638a7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=410372955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.410372955
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.504777850
Short name T847
Test name
Test status
Simulation time 6899321 ps
CPU time 1.37 seconds
Started Dec 20 12:41:47 PM PST 23
Finished Dec 20 12:42:50 PM PST 23
Peak memory 236100 kb
Host smart-4b730f96-69d0-4e66-951d-11aa4f418ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=504777850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.504777850
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3708429631
Short name T742
Test name
Test status
Simulation time 14121377 ps
CPU time 1.34 seconds
Started Dec 20 12:40:31 PM PST 23
Finished Dec 20 12:41:36 PM PST 23
Peak memory 236452 kb
Host smart-c977fef1-857b-459f-ae0a-35c335ae5f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3708429631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3708429631
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2392815349
Short name T354
Test name
Test status
Simulation time 8349580 ps
CPU time 1.31 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:41:35 PM PST 23
Peak memory 236620 kb
Host smart-01059351-1a4c-4e5b-81a5-1137f03df1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2392815349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2392815349
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2975842407
Short name T773
Test name
Test status
Simulation time 41966816 ps
CPU time 1.35 seconds
Started Dec 20 12:40:19 PM PST 23
Finished Dec 20 12:41:20 PM PST 23
Peak memory 235408 kb
Host smart-755a357d-1d0d-48d3-a59d-b20ea1cd93e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2975842407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2975842407
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3085025051
Short name T842
Test name
Test status
Simulation time 8371525 ps
CPU time 1.44 seconds
Started Dec 20 12:40:39 PM PST 23
Finished Dec 20 12:41:44 PM PST 23
Peak memory 234764 kb
Host smart-682c9094-f316-47db-9f6d-9ba4b76b7fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3085025051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3085025051
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1308816430
Short name T806
Test name
Test status
Simulation time 16121111 ps
CPU time 1.24 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:41:34 PM PST 23
Peak memory 234652 kb
Host smart-b8b75b3d-143f-4013-b373-1f01c432725e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1308816430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1308816430
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3512881999
Short name T350
Test name
Test status
Simulation time 24218848 ps
CPU time 1.18 seconds
Started Dec 20 12:40:19 PM PST 23
Finished Dec 20 12:41:20 PM PST 23
Peak memory 236356 kb
Host smart-de87ac81-93d0-4a24-9023-54f76827e7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3512881999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3512881999
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3330546826
Short name T800
Test name
Test status
Simulation time 15229066 ps
CPU time 1.56 seconds
Started Dec 20 12:40:36 PM PST 23
Finished Dec 20 12:41:40 PM PST 23
Peak memory 235568 kb
Host smart-91e68432-373e-4029-bc49-5acf4a1a3dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3330546826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3330546826
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2409155437
Short name T821
Test name
Test status
Simulation time 25722856 ps
CPU time 1.42 seconds
Started Dec 20 12:40:18 PM PST 23
Finished Dec 20 12:41:19 PM PST 23
Peak memory 236576 kb
Host smart-e04b834c-b8be-4223-8edb-b2130a0c69ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2409155437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2409155437
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.226380293
Short name T776
Test name
Test status
Simulation time 2229517111 ps
CPU time 127.37 seconds
Started Dec 20 12:40:12 PM PST 23
Finished Dec 20 12:43:22 PM PST 23
Peak memory 236372 kb
Host smart-6e559600-e7ee-45c4-9efb-fb7090c48d76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=226380293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.226380293
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4093548534
Short name T778
Test name
Test status
Simulation time 11884965770 ps
CPU time 180.82 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:44:11 PM PST 23
Peak memory 236660 kb
Host smart-0ef400cd-db6b-4da6-87b5-5d4cd7a087ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4093548534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4093548534
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1634804735
Short name T786
Test name
Test status
Simulation time 106869794 ps
CPU time 8.28 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 12:41:20 PM PST 23
Peak memory 240464 kb
Host smart-098ea143-20e7-4ba6-a316-3d55b19132a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1634804735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1634804735
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2391562713
Short name T743
Test name
Test status
Simulation time 136774566 ps
CPU time 4.1 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:19 PM PST 23
Peak memory 240360 kb
Host smart-27c5ee8d-51e1-43f9-9c83-9d8e51f959b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391562713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2391562713
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1488975961
Short name T829
Test name
Test status
Simulation time 63660677 ps
CPU time 5.01 seconds
Started Dec 20 12:39:52 PM PST 23
Finished Dec 20 12:41:06 PM PST 23
Peak memory 236544 kb
Host smart-9d4aa690-6a57-4c91-ac28-2ca17ad82c58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1488975961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1488975961
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2166121402
Short name T790
Test name
Test status
Simulation time 12973956 ps
CPU time 1.41 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:41:16 PM PST 23
Peak memory 235692 kb
Host smart-6fd41430-534f-4c1e-a9fa-831ca78947b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2166121402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2166121402
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3061771270
Short name T771
Test name
Test status
Simulation time 271228112 ps
CPU time 17.38 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 240444 kb
Host smart-3e76976c-18b6-449e-9e66-9a021212cd21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3061771270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3061771270
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.71086314
Short name T163
Test name
Test status
Simulation time 11137828924 ps
CPU time 103.87 seconds
Started Dec 20 12:40:09 PM PST 23
Finished Dec 20 12:42:54 PM PST 23
Peak memory 265516 kb
Host smart-434c9c06-1780-42ce-8045-bcf4be82aade
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=71086314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors
.71086314
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3596015145
Short name T153
Test name
Test status
Simulation time 2540594495 ps
CPU time 296.96 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 12:46:08 PM PST 23
Peak memory 265216 kb
Host smart-6855ea00-a043-4282-92f8-5b29274147ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596015145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3596015145
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2389170792
Short name T840
Test name
Test status
Simulation time 312304665 ps
CPU time 10.05 seconds
Started Dec 20 12:40:25 PM PST 23
Finished Dec 20 12:41:36 PM PST 23
Peak memory 248768 kb
Host smart-6e04f9e7-7898-4ecb-810d-9d12fbd806f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389170792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2389170792
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2120327799
Short name T351
Test name
Test status
Simulation time 9378117 ps
CPU time 1.47 seconds
Started Dec 20 12:40:49 PM PST 23
Finished Dec 20 12:41:54 PM PST 23
Peak memory 236552 kb
Host smart-e8e43a43-8e67-4da3-9e50-f7f23eef4d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2120327799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2120327799
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.427825131
Short name T844
Test name
Test status
Simulation time 9409685 ps
CPU time 1.5 seconds
Started Dec 20 12:40:49 PM PST 23
Finished Dec 20 12:41:54 PM PST 23
Peak memory 235544 kb
Host smart-b4383226-826b-4d92-b55e-9bb07ea3dd2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=427825131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.427825131
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1118733533
Short name T831
Test name
Test status
Simulation time 23184176 ps
CPU time 1.3 seconds
Started Dec 20 12:40:17 PM PST 23
Finished Dec 20 12:41:18 PM PST 23
Peak memory 234536 kb
Host smart-f549e198-a34f-4889-9dcd-88d58cf13ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118733533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1118733533
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.295454186
Short name T803
Test name
Test status
Simulation time 11651332 ps
CPU time 1.66 seconds
Started Dec 20 12:41:02 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 235684 kb
Host smart-9c58d9c1-3885-4ed4-95d5-bf4136b26ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=295454186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.295454186
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2556091719
Short name T813
Test name
Test status
Simulation time 9066128 ps
CPU time 1.42 seconds
Started Dec 20 12:40:42 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 234668 kb
Host smart-00abc065-2375-471d-993d-8ed03795d701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2556091719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2556091719
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.747389107
Short name T749
Test name
Test status
Simulation time 20604723 ps
CPU time 1.38 seconds
Started Dec 20 12:40:51 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 236556 kb
Host smart-2d3935fe-3a10-4f61-b4f1-21fe274a7592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=747389107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.747389107
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4121806604
Short name T783
Test name
Test status
Simulation time 18537098 ps
CPU time 1.33 seconds
Started Dec 20 12:40:54 PM PST 23
Finished Dec 20 12:42:00 PM PST 23
Peak memory 235688 kb
Host smart-10a78beb-900a-4307-a2ad-d55ddd5b3d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4121806604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4121806604
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.729165005
Short name T29
Test name
Test status
Simulation time 71816411 ps
CPU time 3.81 seconds
Started Dec 20 12:40:28 PM PST 23
Finished Dec 20 12:41:30 PM PST 23
Peak memory 236568 kb
Host smart-3a50ac74-e470-4a12-ae9b-e698708b6894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=729165005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.729165005
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4203167336
Short name T827
Test name
Test status
Simulation time 12111344 ps
CPU time 1.39 seconds
Started Dec 20 12:40:43 PM PST 23
Finished Dec 20 12:41:47 PM PST 23
Peak memory 236616 kb
Host smart-b9c4b93a-1d26-4cea-a3f0-4d3b525e1869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4203167336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4203167336
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.652343155
Short name T353
Test name
Test status
Simulation time 12790284 ps
CPU time 1.5 seconds
Started Dec 20 12:40:39 PM PST 23
Finished Dec 20 12:41:44 PM PST 23
Peak memory 236528 kb
Host smart-44b9f2f7-43fe-4dec-a0f8-35348d10851b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=652343155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.652343155
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3581352025
Short name T196
Test name
Test status
Simulation time 32945572 ps
CPU time 5.87 seconds
Started Dec 20 12:40:21 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 244172 kb
Host smart-3763913b-278f-4630-a6ea-c9662dbbc357
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581352025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3581352025
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.407733115
Short name T750
Test name
Test status
Simulation time 94618682 ps
CPU time 6.9 seconds
Started Dec 20 12:40:00 PM PST 23
Finished Dec 20 12:41:21 PM PST 23
Peak memory 240340 kb
Host smart-8a3fef04-7bf0-48e5-bcf4-8bc52c450d02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=407733115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.407733115
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4053810010
Short name T780
Test name
Test status
Simulation time 6718558 ps
CPU time 1.34 seconds
Started Dec 20 12:40:34 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 235672 kb
Host smart-47edb231-671d-453e-9015-af2f20e1cca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4053810010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4053810010
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1997657619
Short name T788
Test name
Test status
Simulation time 167271923 ps
CPU time 11.43 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 239728 kb
Host smart-80ec0519-b3a2-4955-a398-d688642ed3bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1997657619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1997657619
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2524289240
Short name T172
Test name
Test status
Simulation time 12859243564 ps
CPU time 310.07 seconds
Started Dec 20 12:40:38 PM PST 23
Finished Dec 20 12:46:51 PM PST 23
Peak memory 265328 kb
Host smart-b3b8ba36-18ea-4172-ba70-9346a9a20bb0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524289240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2524289240
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.437232800
Short name T787
Test name
Test status
Simulation time 103403722 ps
CPU time 7.21 seconds
Started Dec 20 12:40:08 PM PST 23
Finished Dec 20 12:41:15 PM PST 23
Peak memory 239936 kb
Host smart-625e994b-fc7c-42fd-9f76-9ba33831365b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=437232800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.437232800
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.517837520
Short name T205
Test name
Test status
Simulation time 121584142 ps
CPU time 6.08 seconds
Started Dec 20 12:39:58 PM PST 23
Finished Dec 20 12:41:06 PM PST 23
Peak memory 236724 kb
Host smart-140b9834-72b6-4774-81a1-d83a35bf5f80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=517837520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.517837520
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2625214711
Short name T810
Test name
Test status
Simulation time 72657061 ps
CPU time 6.47 seconds
Started Dec 20 12:40:09 PM PST 23
Finished Dec 20 12:41:23 PM PST 23
Peak memory 251080 kb
Host smart-da78d341-2eb4-4958-848f-3eccf2aa3f7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625214711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2625214711
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3259060058
Short name T33
Test name
Test status
Simulation time 51290019 ps
CPU time 4.67 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 12:41:19 PM PST 23
Peak memory 238732 kb
Host smart-ba29f079-7731-4c32-b71d-e7b8cfa27d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3259060058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3259060058
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.512867628
Short name T782
Test name
Test status
Simulation time 10274452 ps
CPU time 1.29 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 236400 kb
Host smart-35df9292-e4ac-4623-9a26-873a7f5cae22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=512867628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.512867628
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1304458767
Short name T176
Test name
Test status
Simulation time 1298132477 ps
CPU time 21.71 seconds
Started Dec 20 12:40:17 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 244692 kb
Host smart-49703c6a-db69-482a-a47e-3ea0c56d1eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1304458767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1304458767
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4013677425
Short name T838
Test name
Test status
Simulation time 59681315 ps
CPU time 7.71 seconds
Started Dec 20 12:40:04 PM PST 23
Finished Dec 20 12:41:14 PM PST 23
Peak memory 253168 kb
Host smart-7ac5ba46-47fb-480f-97f6-2e6c78bac16a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4013677425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4013677425
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2243986248
Short name T775
Test name
Test status
Simulation time 54304207 ps
CPU time 5.57 seconds
Started Dec 20 12:40:13 PM PST 23
Finished Dec 20 12:41:20 PM PST 23
Peak memory 250584 kb
Host smart-0e8b1d96-1db9-4dd5-9344-da94bd034673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243986248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2243986248
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4138799360
Short name T807
Test name
Test status
Simulation time 250633120 ps
CPU time 8.66 seconds
Started Dec 20 12:40:21 PM PST 23
Finished Dec 20 12:41:29 PM PST 23
Peak memory 236504 kb
Host smart-6f22c815-011a-4b4a-8ca9-c9c1e4242f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4138799360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4138799360
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1432337913
Short name T779
Test name
Test status
Simulation time 7807241 ps
CPU time 1.29 seconds
Started Dec 20 12:40:14 PM PST 23
Finished Dec 20 12:41:16 PM PST 23
Peak memory 236552 kb
Host smart-8a552f5e-89b6-498a-bdcb-389c4ca45d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1432337913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1432337913
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3015852568
Short name T811
Test name
Test status
Simulation time 6498736989 ps
CPU time 37.53 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:42:07 PM PST 23
Peak memory 243644 kb
Host smart-b25c8225-4759-467c-b9e8-cf9442fd9ba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3015852568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3015852568
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1572196891
Short name T178
Test name
Test status
Simulation time 46064757241 ps
CPU time 464.94 seconds
Started Dec 20 12:40:41 PM PST 23
Finished Dec 20 12:49:28 PM PST 23
Peak memory 265420 kb
Host smart-74b07a4c-5cd3-4d25-bb8f-1a62da826dc4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572196891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1572196891
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4145679303
Short name T835
Test name
Test status
Simulation time 378867508 ps
CPU time 23.98 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 252620 kb
Host smart-c15ad0ea-16ea-4bf5-9450-7c1ada1d8395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145679303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4145679303
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1106304408
Short name T207
Test name
Test status
Simulation time 784126049 ps
CPU time 47.79 seconds
Started Dec 20 12:40:30 PM PST 23
Finished Dec 20 12:42:18 PM PST 23
Peak memory 245080 kb
Host smart-db1ba37d-903e-4b8b-a15a-08bb19019116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1106304408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1106304408
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1581804852
Short name T210
Test name
Test status
Simulation time 37279660 ps
CPU time 3.85 seconds
Started Dec 20 12:40:24 PM PST 23
Finished Dec 20 12:41:40 PM PST 23
Peak memory 240296 kb
Host smart-65185b3b-d675-47b8-87ba-1207f6049330
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581804852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1581804852
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.237084226
Short name T791
Test name
Test status
Simulation time 464233105 ps
CPU time 8.88 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 236524 kb
Host smart-631e91e9-1a4b-4f85-8ea6-1bc21f36e386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=237084226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.237084226
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.4221855289
Short name T793
Test name
Test status
Simulation time 9469083 ps
CPU time 1.33 seconds
Started Dec 20 12:40:28 PM PST 23
Finished Dec 20 12:41:31 PM PST 23
Peak memory 236480 kb
Host smart-666007e4-c730-4c35-8061-c23ffe55a17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4221855289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.4221855289
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2835920742
Short name T756
Test name
Test status
Simulation time 98287367 ps
CPU time 12.39 seconds
Started Dec 20 12:40:32 PM PST 23
Finished Dec 20 12:41:45 PM PST 23
Peak memory 246900 kb
Host smart-59b5e27b-5373-4556-9ba4-5b811cf9adb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2835920742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2835920742
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2058045376
Short name T32
Test name
Test status
Simulation time 4608381315 ps
CPU time 158.43 seconds
Started Dec 20 12:40:31 PM PST 23
Finished Dec 20 12:44:13 PM PST 23
Peak memory 257284 kb
Host smart-9c059f13-5d43-4445-900d-eb2444ddb902
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2058045376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2058045376
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1813196301
Short name T182
Test name
Test status
Simulation time 8526584122 ps
CPU time 528.44 seconds
Started Dec 20 12:40:16 PM PST 23
Finished Dec 20 12:50:04 PM PST 23
Peak memory 272836 kb
Host smart-ac612290-1f2b-4562-824a-69d3cf35f73b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813196301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1813196301
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.582307493
Short name T35
Test name
Test status
Simulation time 73972585 ps
CPU time 10.12 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:42:04 PM PST 23
Peak memory 248400 kb
Host smart-04fea05c-1504-4fd4-b34b-7afd6598e733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=582307493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.582307493
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.4179667263
Short name T843
Test name
Test status
Simulation time 52790964 ps
CPU time 3.32 seconds
Started Dec 20 12:40:49 PM PST 23
Finished Dec 20 12:41:56 PM PST 23
Peak memory 239420 kb
Host smart-6d46ffef-2356-4910-99bb-316fa10c3aa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179667263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.4179667263
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2382597152
Short name T832
Test name
Test status
Simulation time 20689024 ps
CPU time 3.09 seconds
Started Dec 20 12:40:39 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 238600 kb
Host smart-bff21f3f-e45d-46df-a9cd-33f79f6d76a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2382597152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2382597152
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4270722088
Short name T747
Test name
Test status
Simulation time 9838434 ps
CPU time 1.47 seconds
Started Dec 20 12:40:50 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 236620 kb
Host smart-d485c456-b093-45f6-ab4c-2f1725762829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4270722088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4270722088
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.641542708
Short name T759
Test name
Test status
Simulation time 845229997 ps
CPU time 20.04 seconds
Started Dec 20 12:40:29 PM PST 23
Finished Dec 20 12:41:55 PM PST 23
Peak memory 248620 kb
Host smart-9873664f-460d-433b-b4e3-9d565862f486
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=641542708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.641542708
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1510747443
Short name T156
Test name
Test status
Simulation time 2999047473 ps
CPU time 85.67 seconds
Started Dec 20 12:40:22 PM PST 23
Finished Dec 20 12:42:47 PM PST 23
Peak memory 257224 kb
Host smart-ddb0cbfc-ae63-4b4f-9b00-3ae36e84e10e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1510747443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1510747443
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2574565955
Short name T774
Test name
Test status
Simulation time 2186159511 ps
CPU time 7.66 seconds
Started Dec 20 12:40:27 PM PST 23
Finished Dec 20 12:41:37 PM PST 23
Peak memory 248848 kb
Host smart-c4c4684c-07d1-4b36-9277-3d541c8d80a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2574565955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2574565955
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3168778159
Short name T65
Test name
Test status
Simulation time 20278866882 ps
CPU time 1234.01 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 01:17:33 PM PST 23
Peak memory 273268 kb
Host smart-115413b2-fe08-49d5-a2a2-b73715ac6942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168778159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3168778159
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3486896854
Short name T409
Test name
Test status
Simulation time 2015825517 ps
CPU time 21.9 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:58:06 PM PST 23
Peak memory 240572 kb
Host smart-ade40db1-14c8-4751-97a3-60a9443d9ad3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3486896854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3486896854
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3509148659
Short name T733
Test name
Test status
Simulation time 13031849494 ps
CPU time 129.97 seconds
Started Dec 20 12:56:57 PM PST 23
Finished Dec 20 12:59:18 PM PST 23
Peak memory 250768 kb
Host smart-1f2cc5f8-2423-4555-85d5-b3e6fbc2e587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
48659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3509148659
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3148669854
Short name T397
Test name
Test status
Simulation time 232474407 ps
CPU time 4.17 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:57:07 PM PST 23
Peak memory 238684 kb
Host smart-39897ae8-f455-4171-8de0-8b734decea36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31486
69854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3148669854
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2750106974
Short name T683
Test name
Test status
Simulation time 69540967069 ps
CPU time 1076.55 seconds
Started Dec 20 12:56:57 PM PST 23
Finished Dec 20 01:15:06 PM PST 23
Peak memory 265040 kb
Host smart-c2f8a2f1-3036-4fc5-8b4f-63441089a99b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750106974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2750106974
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.200108313
Short name T53
Test name
Test status
Simulation time 38032064844 ps
CPU time 2107.8 seconds
Started Dec 20 12:56:57 PM PST 23
Finished Dec 20 01:32:18 PM PST 23
Peak memory 272556 kb
Host smart-b6d1b915-3a8a-4273-ab47-02f71545c49d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200108313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.200108313
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4126272043
Short name T82
Test name
Test status
Simulation time 13869446893 ps
CPU time 600.66 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 01:07:00 PM PST 23
Peak memory 246408 kb
Host smart-b41ded09-a323-4395-ac51-f8b6ee171680
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126272043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4126272043
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.564911980
Short name T639
Test name
Test status
Simulation time 1687300461 ps
CPU time 44.94 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 12:57:55 PM PST 23
Peak memory 248792 kb
Host smart-4fd1e10a-42e5-4b14-9026-c715305ca23a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56491
1980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.564911980
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.569864759
Short name T525
Test name
Test status
Simulation time 771109475 ps
CPU time 43.52 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:57:47 PM PST 23
Peak memory 255724 kb
Host smart-081805ef-8f90-472c-8f89-04224ef48ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56986
4759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.569864759
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1804053881
Short name T441
Test name
Test status
Simulation time 477077471 ps
CPU time 30.27 seconds
Started Dec 20 12:56:49 PM PST 23
Finished Dec 20 12:57:26 PM PST 23
Peak memory 256452 kb
Host smart-20e6b5af-5898-4d2f-a9ba-3c0d006c1387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18040
53881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1804053881
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.273911813
Short name T680
Test name
Test status
Simulation time 1002495997 ps
CPU time 16.71 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 12:57:27 PM PST 23
Peak memory 248772 kb
Host smart-d278fdcd-f1bd-4359-8a26-aa715af25a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27391
1813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.273911813
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2317483942
Short name T559
Test name
Test status
Simulation time 5594081228 ps
CPU time 310.51 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 01:02:16 PM PST 23
Peak memory 256992 kb
Host smart-88aca4bf-db3c-4907-bd1c-b0c13d999155
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317483942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2317483942
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2161593526
Short name T433
Test name
Test status
Simulation time 88183757632 ps
CPU time 1100.74 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 01:15:24 PM PST 23
Peak memory 265096 kb
Host smart-c88f89f5-0515-4ff1-899e-406f29f9e25e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161593526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2161593526
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3443491712
Short name T562
Test name
Test status
Simulation time 322886485 ps
CPU time 10.07 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 12:57:45 PM PST 23
Peak memory 240508 kb
Host smart-aeb4cd31-e4ff-456b-8094-2291e8d58610
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3443491712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3443491712
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.717554988
Short name T55
Test name
Test status
Simulation time 2683316841 ps
CPU time 140.39 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:59:48 PM PST 23
Peak memory 249652 kb
Host smart-ec688e2d-1b70-4748-938e-4dd16d8b1063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71755
4988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.717554988
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3776525501
Short name T25
Test name
Test status
Simulation time 1582178529 ps
CPU time 21.32 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 12:57:29 PM PST 23
Peak memory 247792 kb
Host smart-c269feff-3991-41b4-a20e-5bcfee83a74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37765
25501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3776525501
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1620874984
Short name T592
Test name
Test status
Simulation time 19108138360 ps
CPU time 1127.31 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 01:16:07 PM PST 23
Peak memory 265276 kb
Host smart-60b4d8c1-de62-4d42-be72-4e92ee0a9c95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620874984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1620874984
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1672055419
Short name T320
Test name
Test status
Simulation time 45128359572 ps
CPU time 459.6 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 01:05:00 PM PST 23
Peak memory 247792 kb
Host smart-79763372-490a-421f-9163-11204a99f59a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672055419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1672055419
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3484066449
Short name T643
Test name
Test status
Simulation time 2154065816 ps
CPU time 31.19 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 248772 kb
Host smart-b83f6e55-1004-49ca-9f65-4567f399a6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34840
66449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3484066449
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3631315694
Short name T655
Test name
Test status
Simulation time 299640673 ps
CPU time 26.97 seconds
Started Dec 20 12:56:57 PM PST 23
Finished Dec 20 12:57:36 PM PST 23
Peak memory 255332 kb
Host smart-9de45c1d-b51a-4822-96f2-4772f76ef34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36313
15694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3631315694
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3516548820
Short name T15
Test name
Test status
Simulation time 841994384 ps
CPU time 37.56 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:57:08 PM PST 23
Peak memory 277696 kb
Host smart-0579505e-6bb4-4a2f-a253-a252a03a1b48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3516548820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3516548820
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4142471481
Short name T138
Test name
Test status
Simulation time 1483216740 ps
CPU time 29.3 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 248640 kb
Host smart-14e1e536-c4b3-483a-9d36-14375644ce07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41424
71481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4142471481
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1135885014
Short name T268
Test name
Test status
Simulation time 180040137 ps
CPU time 20.22 seconds
Started Dec 20 12:57:06 PM PST 23
Finished Dec 20 12:57:43 PM PST 23
Peak memory 248808 kb
Host smart-c46ea911-4776-45ea-b8f3-fdb70aa5e67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11358
85014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1135885014
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3277823432
Short name T601
Test name
Test status
Simulation time 4360936874 ps
CPU time 230.79 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 01:01:03 PM PST 23
Peak memory 256988 kb
Host smart-65b1c15c-af43-4380-b5c6-89e43508f521
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277823432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3277823432
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.466825632
Short name T574
Test name
Test status
Simulation time 55966058632 ps
CPU time 1320.5 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 01:19:42 PM PST 23
Peak memory 286748 kb
Host smart-ecee5325-f579-4a50-bdd3-23de813f2ca6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466825632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.466825632
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3929890304
Short name T451
Test name
Test status
Simulation time 855238813 ps
CPU time 20.37 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 12:58:04 PM PST 23
Peak memory 240556 kb
Host smart-1e93e433-51ea-494f-832e-3af742870d8f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3929890304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3929890304
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2320927323
Short name T54
Test name
Test status
Simulation time 1123559380 ps
CPU time 58.56 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 255316 kb
Host smart-8613d95b-d2bb-454a-9e30-69f728c44a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23209
27323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2320927323
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.407217887
Short name T695
Test name
Test status
Simulation time 1219599656 ps
CPU time 69.4 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:58:55 PM PST 23
Peak memory 254248 kb
Host smart-089da2f5-52e7-4c8d-8623-a1abce5e4300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721
7887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.407217887
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.667141280
Short name T556
Test name
Test status
Simulation time 23917897703 ps
CPU time 1151.58 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:16:49 PM PST 23
Peak memory 284316 kb
Host smart-80fcc32f-2f36-4a57-a1ec-d66a7169b10e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667141280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.667141280
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2420514566
Short name T693
Test name
Test status
Simulation time 17115240484 ps
CPU time 1025.79 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 01:14:37 PM PST 23
Peak memory 264872 kb
Host smart-ad7790f4-dd58-464a-9f6a-c283a722c085
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420514566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2420514566
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2582217148
Short name T325
Test name
Test status
Simulation time 23049963650 ps
CPU time 231.53 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 01:01:23 PM PST 23
Peak memory 248792 kb
Host smart-9ca5dc7c-a20c-4069-a88e-b4aea9d969bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582217148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2582217148
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3012147580
Short name T498
Test name
Test status
Simulation time 630763781 ps
CPU time 21.13 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 255504 kb
Host smart-e254fb57-2d7d-4ed3-9ad7-bac9aef5b572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30121
47580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3012147580
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3055326061
Short name T386
Test name
Test status
Simulation time 400383476 ps
CPU time 32.77 seconds
Started Dec 20 12:57:45 PM PST 23
Finished Dec 20 12:58:38 PM PST 23
Peak memory 248336 kb
Host smart-62d88a28-09d7-4a4a-b17c-1bda8600397f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30553
26061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3055326061
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2022509256
Short name T288
Test name
Test status
Simulation time 1040616812 ps
CPU time 21.93 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:58 PM PST 23
Peak memory 246800 kb
Host smart-2f4f5695-b1e9-425a-a9cf-302788b0bed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20225
09256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2022509256
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.685529703
Short name T565
Test name
Test status
Simulation time 766687574 ps
CPU time 11.3 seconds
Started Dec 20 12:57:20 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 248552 kb
Host smart-aac5206c-ce23-439d-b159-8262f0076374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68552
9703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.685529703
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.192928524
Short name T475
Test name
Test status
Simulation time 62464125285 ps
CPU time 1341.73 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:19:58 PM PST 23
Peak memory 288844 kb
Host smart-0e4cde29-3734-41fa-b9da-4c78833d396e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192928524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.192928524
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3036630100
Short name T629
Test name
Test status
Simulation time 9825315270 ps
CPU time 695.58 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 01:08:56 PM PST 23
Peak memory 265192 kb
Host smart-c2ca767f-55cb-4585-ab7d-011a0a1c193e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036630100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3036630100
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3679796648
Short name T612
Test name
Test status
Simulation time 158485985 ps
CPU time 9.15 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:58:01 PM PST 23
Peak memory 240492 kb
Host smart-7084dc9a-3840-4b82-914d-2771e3f3a9ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3679796648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3679796648
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1102758568
Short name T387
Test name
Test status
Simulation time 384428692 ps
CPU time 21.13 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:57:52 PM PST 23
Peak memory 248168 kb
Host smart-a62f6857-b748-4e12-a3f7-0470363c9bca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027
58568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1102758568
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1143204388
Short name T687
Test name
Test status
Simulation time 694750267 ps
CPU time 15.13 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:43 PM PST 23
Peak memory 255404 kb
Host smart-93ce6cb4-2b28-4a31-9f71-1777246dd430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11432
04388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1143204388
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.4150473221
Short name T142
Test name
Test status
Simulation time 24755171150 ps
CPU time 1093.29 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 01:15:37 PM PST 23
Peak memory 284476 kb
Host smart-9c1fb7d3-4e55-4bb7-a98d-59c0a7b7b7d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150473221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.4150473221
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.765501855
Short name T18
Test name
Test status
Simulation time 8939467791 ps
CPU time 760.65 seconds
Started Dec 20 12:57:20 PM PST 23
Finished Dec 20 01:10:18 PM PST 23
Peak memory 265352 kb
Host smart-8f26636b-1a8f-49f1-8096-93d3937ed87a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765501855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.765501855
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1590369689
Short name T712
Test name
Test status
Simulation time 13540748472 ps
CPU time 556.51 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 01:06:48 PM PST 23
Peak memory 247684 kb
Host smart-7c9d9179-a67f-43f4-8c17-f3f65c5e1926
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590369689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1590369689
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1593282117
Short name T478
Test name
Test status
Simulation time 752915689 ps
CPU time 12.43 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:30 PM PST 23
Peak memory 248636 kb
Host smart-a8f0411c-5fb3-4037-9902-f4772201bf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15932
82117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1593282117
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2130933884
Short name T295
Test name
Test status
Simulation time 854131441 ps
CPU time 51.45 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:58:23 PM PST 23
Peak memory 255384 kb
Host smart-9d5531b6-6d7e-4fae-813f-ed5f1bdcd199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
33884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2130933884
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3701684401
Short name T481
Test name
Test status
Simulation time 373262559 ps
CPU time 24.57 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:52 PM PST 23
Peak memory 254856 kb
Host smart-bd038fbc-8124-443f-9bca-54543d1a7792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37016
84401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3701684401
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3483441164
Short name T672
Test name
Test status
Simulation time 118137866 ps
CPU time 7.9 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 12:57:42 PM PST 23
Peak memory 240452 kb
Host smart-a99b53fc-98b9-4d9d-8725-98730a4db216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34834
41164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3483441164
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.4283876303
Short name T242
Test name
Test status
Simulation time 31130527 ps
CPU time 2.35 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 248856 kb
Host smart-6829e0bf-0873-4ffd-9846-6aabab9b0c5a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4283876303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.4283876303
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1089507412
Short name T405
Test name
Test status
Simulation time 33834401576 ps
CPU time 1806.64 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 01:27:53 PM PST 23
Peak memory 283652 kb
Host smart-1ec2e53c-40db-4bee-a62a-86d87708914e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089507412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1089507412
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2170242565
Short name T690
Test name
Test status
Simulation time 406475132 ps
CPU time 6.49 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:34 PM PST 23
Peak memory 240376 kb
Host smart-35d710da-2a9d-4018-b608-54eff0668d6b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2170242565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2170242565
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3661177976
Short name T417
Test name
Test status
Simulation time 3129419255 ps
CPU time 49.69 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:58:17 PM PST 23
Peak memory 255912 kb
Host smart-25f29955-b83c-4f35-b604-df655689a7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36611
77976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3661177976
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.971983913
Short name T285
Test name
Test status
Simulation time 343658008 ps
CPU time 32.81 seconds
Started Dec 20 12:57:09 PM PST 23
Finished Dec 20 12:57:57 PM PST 23
Peak memory 254428 kb
Host smart-a91f54c1-d846-4b02-bc95-37da28e87153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97198
3913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.971983913
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2240022356
Short name T41
Test name
Test status
Simulation time 47930069705 ps
CPU time 1173.73 seconds
Started Dec 20 12:57:08 PM PST 23
Finished Dec 20 01:16:58 PM PST 23
Peak memory 288288 kb
Host smart-b1ece2d7-b0b3-4c79-8d0e-9abd171fbddd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240022356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2240022356
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1221224917
Short name T652
Test name
Test status
Simulation time 256620844 ps
CPU time 7.23 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 12:57:35 PM PST 23
Peak memory 253324 kb
Host smart-e010b8af-f1b6-4f93-9683-859764f31969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12212
24917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1221224917
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2824840557
Short name T701
Test name
Test status
Simulation time 186745514 ps
CPU time 3.51 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 12:57:55 PM PST 23
Peak memory 238652 kb
Host smart-2ba21764-faee-46f7-b933-df348d3231ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28248
40557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2824840557
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1932275380
Short name T406
Test name
Test status
Simulation time 1017339417 ps
CPU time 30.58 seconds
Started Dec 20 12:57:09 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 248660 kb
Host smart-33907986-336f-4f43-b7cb-f34e653be2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19322
75380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1932275380
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3812014710
Short name T587
Test name
Test status
Simulation time 136839979023 ps
CPU time 2072.53 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:32:16 PM PST 23
Peak memory 289572 kb
Host smart-7f5e12cc-c0f7-4750-aff6-24c38f5c211c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812014710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3812014710
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.32173824
Short name T229
Test name
Test status
Simulation time 51837481 ps
CPU time 2.44 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:57:55 PM PST 23
Peak memory 248764 kb
Host smart-1f7e9800-32cc-4c65-bc1d-c5fa42e457ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=32173824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.32173824
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2466807839
Short name T692
Test name
Test status
Simulation time 95895243730 ps
CPU time 1303.6 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 01:19:23 PM PST 23
Peak memory 271172 kb
Host smart-b820189d-e2d2-406e-8f3b-998d56b73985
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466807839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2466807839
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3008896003
Short name T653
Test name
Test status
Simulation time 3558667109 ps
CPU time 76.98 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 12:59:15 PM PST 23
Peak memory 248776 kb
Host smart-91007cab-e01f-4db1-9469-c2911bd85742
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3008896003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3008896003
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.4174499478
Short name T434
Test name
Test status
Simulation time 8723196837 ps
CPU time 115.45 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:59:41 PM PST 23
Peak memory 256520 kb
Host smart-12df8e54-e1b0-46f0-ba14-eaab061768f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
99478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4174499478
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.898723348
Short name T133
Test name
Test status
Simulation time 1043741090 ps
CPU time 51.53 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 12:58:20 PM PST 23
Peak memory 248304 kb
Host smart-018aa689-0b7f-4454-8fbc-218169cf641d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89872
3348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.898723348
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2991582392
Short name T739
Test name
Test status
Simulation time 20150006552 ps
CPU time 1242.16 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:18:18 PM PST 23
Peak memory 273356 kb
Host smart-1e904155-fa5e-4047-ba09-27610f23bb2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991582392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2991582392
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1610969146
Short name T272
Test name
Test status
Simulation time 102685702800 ps
CPU time 1885.89 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 01:29:06 PM PST 23
Peak memory 289264 kb
Host smart-b4a2ca92-1214-4101-bc2c-08897ffc2edd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610969146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1610969146
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3009312298
Short name T514
Test name
Test status
Simulation time 2623883719 ps
CPU time 105.63 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 12:59:26 PM PST 23
Peak memory 246320 kb
Host smart-9be8408b-c8b9-4f97-b2a4-e1f6fd39b5ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009312298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3009312298
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3485158592
Short name T543
Test name
Test status
Simulation time 218707702 ps
CPU time 22.63 seconds
Started Dec 20 12:57:20 PM PST 23
Finished Dec 20 12:58:00 PM PST 23
Peak memory 248732 kb
Host smart-d3c29c22-5bbe-4479-8a0b-419d52757613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34851
58592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3485158592
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2322811318
Short name T528
Test name
Test status
Simulation time 1292962802 ps
CPU time 70.55 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:58:57 PM PST 23
Peak memory 254504 kb
Host smart-0ccc1740-c4df-45bb-ab89-65c15ad2f166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
11318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2322811318
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3015413836
Short name T513
Test name
Test status
Simulation time 842866368 ps
CPU time 46.15 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 12:58:42 PM PST 23
Peak memory 247488 kb
Host smart-a704532a-123f-4882-b64b-10f021323a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30154
13836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3015413836
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2772453678
Short name T649
Test name
Test status
Simulation time 832859419 ps
CPU time 22.54 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 248820 kb
Host smart-b4ba6bae-49ad-40c9-86ea-0019fbe8a646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27724
53678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2772453678
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.598394479
Short name T507
Test name
Test status
Simulation time 181392514749 ps
CPU time 1010.01 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 01:14:43 PM PST 23
Peak memory 285332 kb
Host smart-a2feb7fc-59a1-4192-ac53-59da6fa2bef0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598394479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.598394479
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2350724924
Short name T688
Test name
Test status
Simulation time 232920347366 ps
CPU time 1423.14 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 01:21:18 PM PST 23
Peak memory 281464 kb
Host smart-734f0d50-7e00-4976-8086-3b961c8b4adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350724924 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2350724924
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2804328694
Short name T238
Test name
Test status
Simulation time 145031234 ps
CPU time 2.83 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:40 PM PST 23
Peak memory 249012 kb
Host smart-d9bdfb5c-c2c3-4809-95ca-524c0b6fa3d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2804328694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2804328694
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.788588677
Short name T99
Test name
Test status
Simulation time 11355257314 ps
CPU time 1121.66 seconds
Started Dec 20 12:57:20 PM PST 23
Finished Dec 20 01:16:20 PM PST 23
Peak memory 285448 kb
Host smart-13a1a6d7-de3a-47e9-a1a7-7791ade5af21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788588677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.788588677
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1369977529
Short name T620
Test name
Test status
Simulation time 268959791 ps
CPU time 12.96 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 12:57:19 PM PST 23
Peak memory 240568 kb
Host smart-0660e433-28ed-45fd-b830-a99f43c520cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1369977529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1369977529
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.494080762
Short name T511
Test name
Test status
Simulation time 6056649170 ps
CPU time 90.44 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 12:59:04 PM PST 23
Peak memory 248776 kb
Host smart-81092998-0c0e-46eb-a7ec-d419731bcc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49408
0762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.494080762
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1999110388
Short name T97
Test name
Test status
Simulation time 999539135 ps
CPU time 32.39 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 12:58:15 PM PST 23
Peak memory 248040 kb
Host smart-20f87f6e-276d-4f8a-9f07-184c2e777263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19991
10388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1999110388
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3730081963
Short name T732
Test name
Test status
Simulation time 113560898361 ps
CPU time 1358.48 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 01:20:12 PM PST 23
Peak memory 273424 kb
Host smart-3e86aead-cb11-4422-9420-60fe171e7d54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730081963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3730081963
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.390178215
Short name T700
Test name
Test status
Simulation time 354128038065 ps
CPU time 1742.73 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 01:26:14 PM PST 23
Peak memory 272272 kb
Host smart-08dd93d4-2981-4371-aa72-b872458701b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390178215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.390178215
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1581375290
Short name T464
Test name
Test status
Simulation time 559029590 ps
CPU time 29.04 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:58:07 PM PST 23
Peak memory 248712 kb
Host smart-1221a105-f9a5-458f-8101-7fbb9fd5afe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15813
75290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1581375290
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3254615307
Short name T551
Test name
Test status
Simulation time 509669453 ps
CPU time 26.37 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 12:58:02 PM PST 23
Peak memory 246836 kb
Host smart-96986180-1e9c-402c-be09-a85578bdd845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32546
15307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3254615307
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.811886695
Short name T630
Test name
Test status
Simulation time 4577400314 ps
CPU time 47.59 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:58:40 PM PST 23
Peak memory 255288 kb
Host smart-5abaa85f-07c9-4dd4-b1cc-885def1bed93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81188
6695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.811886695
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3915590063
Short name T465
Test name
Test status
Simulation time 2999158092 ps
CPU time 34.33 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 12:58:14 PM PST 23
Peak memory 248528 kb
Host smart-688e8b7b-b2a6-4432-a432-0a741a53e8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39155
90063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3915590063
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.851768810
Short name T532
Test name
Test status
Simulation time 6833631695 ps
CPU time 427.5 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:04:44 PM PST 23
Peak memory 254200 kb
Host smart-6871a5a4-8046-4635-8f33-a00e7d3a10c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851768810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.851768810
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1285085074
Short name T228
Test name
Test status
Simulation time 135289613 ps
CPU time 2.97 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:57:34 PM PST 23
Peak memory 249048 kb
Host smart-27f16bce-b280-4778-85c0-1c5678a9e740
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1285085074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1285085074
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1647936911
Short name T529
Test name
Test status
Simulation time 15581203469 ps
CPU time 1419.59 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 01:21:13 PM PST 23
Peak memory 289196 kb
Host smart-39da0abf-2f53-42f0-9a7f-f7105ec2218c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647936911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1647936911
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.959325844
Short name T684
Test name
Test status
Simulation time 533182260 ps
CPU time 7.86 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 12:57:41 PM PST 23
Peak memory 240372 kb
Host smart-d7916a76-adf4-4ed8-b118-b8f038954b7f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=959325844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.959325844
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3671243726
Short name T411
Test name
Test status
Simulation time 35582805284 ps
CPU time 230.88 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 01:01:36 PM PST 23
Peak memory 256120 kb
Host smart-75951ecc-dba1-4ff9-95b3-8e82e3c82107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36712
43726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3671243726
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.611379218
Short name T391
Test name
Test status
Simulation time 303058794 ps
CPU time 5.27 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 12:57:27 PM PST 23
Peak memory 239624 kb
Host smart-d8dac065-0a14-41fd-9667-663f14d89996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61137
9218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.611379218
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3131049420
Short name T326
Test name
Test status
Simulation time 117754695511 ps
CPU time 2253.85 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 01:34:57 PM PST 23
Peak memory 289504 kb
Host smart-5b333d69-e333-467c-85ca-595cabe2527d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131049420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3131049420
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2164208374
Short name T731
Test name
Test status
Simulation time 496934603358 ps
CPU time 2240.82 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:35:05 PM PST 23
Peak memory 288884 kb
Host smart-c7c873c4-d83f-4ccb-afef-207ae3fff900
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164208374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2164208374
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3121687200
Short name T724
Test name
Test status
Simulation time 16154076106 ps
CPU time 326.35 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 01:03:12 PM PST 23
Peak memory 247216 kb
Host smart-b6567b18-1d17-445f-b475-b741958d3dfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121687200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3121687200
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2517212506
Short name T539
Test name
Test status
Simulation time 1570955476 ps
CPU time 27.42 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:57:59 PM PST 23
Peak memory 255664 kb
Host smart-0579dbd1-b2b6-4d62-bd28-001831680e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25172
12506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2517212506
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.524771886
Short name T370
Test name
Test status
Simulation time 155314045 ps
CPU time 5.5 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 12:57:04 PM PST 23
Peak memory 252268 kb
Host smart-e98987f1-e6a9-4922-be56-2d4db727c758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52477
1886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.524771886
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3084440832
Short name T278
Test name
Test status
Simulation time 365135591 ps
CPU time 20.46 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 12:57:43 PM PST 23
Peak memory 248784 kb
Host smart-b6b6b5a8-8a96-41f5-8c37-19d4d41e09b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30844
40832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3084440832
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1856947039
Short name T85
Test name
Test status
Simulation time 405789900 ps
CPU time 5.72 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 240392 kb
Host smart-11218f8b-ae45-4317-93ed-808cd30a8d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18569
47039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1856947039
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.278215610
Short name T300
Test name
Test status
Simulation time 44626295256 ps
CPU time 2455.6 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 01:38:30 PM PST 23
Peak memory 289224 kb
Host smart-ff59c646-afd5-4bec-b4f5-7b3ae391a17d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278215610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.278215610
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2543353810
Short name T304
Test name
Test status
Simulation time 14387426732 ps
CPU time 626.52 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 01:08:25 PM PST 23
Peak memory 270744 kb
Host smart-404201b4-55ef-47b8-81c2-c4490cc70dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543353810 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2543353810
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1501797720
Short name T230
Test name
Test status
Simulation time 38276823 ps
CPU time 3.19 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 248872 kb
Host smart-a6fdcd4e-8861-4dda-978d-165c5a2e157b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1501797720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1501797720
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1695374800
Short name T462
Test name
Test status
Simulation time 34235826207 ps
CPU time 1812.94 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 01:27:47 PM PST 23
Peak memory 273020 kb
Host smart-66de8d80-4e25-4f08-9053-0489887ed3e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695374800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1695374800
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.4195278692
Short name T254
Test name
Test status
Simulation time 728237953 ps
CPU time 10.48 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 12:57:58 PM PST 23
Peak memory 248684 kb
Host smart-036203ed-5d06-4608-b6bf-ba8ccea9bfde
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4195278692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4195278692
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3831414926
Short name T648
Test name
Test status
Simulation time 2973966590 ps
CPU time 19.98 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:47 PM PST 23
Peak memory 255912 kb
Host smart-94dbacf1-42d3-4fb5-a628-5e1d097f8ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38314
14926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3831414926
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1128155203
Short name T719
Test name
Test status
Simulation time 377756960 ps
CPU time 7.55 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 12:57:33 PM PST 23
Peak memory 252460 kb
Host smart-fc200208-2993-4507-bb58-b714de5fbea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11281
55203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1128155203
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2523712164
Short name T313
Test name
Test status
Simulation time 17631712014 ps
CPU time 1188.59 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 01:17:31 PM PST 23
Peak memory 281568 kb
Host smart-c7322828-929b-4ca5-88ba-3870a7d7e807
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523712164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2523712164
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3829325143
Short name T530
Test name
Test status
Simulation time 34369896956 ps
CPU time 1432 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 01:21:19 PM PST 23
Peak memory 289444 kb
Host smart-fd35c87f-68b3-4ce9-a939-984515cece8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829325143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3829325143
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2877014525
Short name T146
Test name
Test status
Simulation time 17505185234 ps
CPU time 385.39 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:04:08 PM PST 23
Peak memory 247700 kb
Host smart-818223f5-bc58-4207-abb7-8e6bdd94d44f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877014525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2877014525
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1520834216
Short name T249
Test name
Test status
Simulation time 949146287 ps
CPU time 29.5 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 255492 kb
Host smart-42429f36-f2fe-46db-bf69-97f95fe6162a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15208
34216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1520834216
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1619909266
Short name T64
Test name
Test status
Simulation time 2996616274 ps
CPU time 41.12 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:58:21 PM PST 23
Peak memory 254444 kb
Host smart-448010b0-cd2b-40f9-811b-39240ca37a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16199
09266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1619909266
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4238008940
Short name T550
Test name
Test status
Simulation time 123905091 ps
CPU time 12.42 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 12:57:38 PM PST 23
Peak memory 248668 kb
Host smart-733090a4-8f72-44eb-8004-9f1428d6f0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
08940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4238008940
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.803317433
Short name T583
Test name
Test status
Simulation time 48144987093 ps
CPU time 1920.74 seconds
Started Dec 20 12:57:09 PM PST 23
Finished Dec 20 01:29:26 PM PST 23
Peak memory 289808 kb
Host smart-61f6cf34-495c-4033-a765-48638e5cafdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803317433 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.803317433
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4033721128
Short name T244
Test name
Test status
Simulation time 139991868 ps
CPU time 3.17 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:40 PM PST 23
Peak memory 248812 kb
Host smart-5f02a765-45a6-48d3-8032-f15f20ab9d21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4033721128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4033721128
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1874718234
Short name T472
Test name
Test status
Simulation time 38618224890 ps
CPU time 2060.87 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 01:32:07 PM PST 23
Peak memory 283068 kb
Host smart-031e5730-ac64-45db-aa85-7cd95ef92f5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874718234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1874718234
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3467427437
Short name T396
Test name
Test status
Simulation time 3397976413 ps
CPU time 201.21 seconds
Started Dec 20 12:56:59 PM PST 23
Finished Dec 20 01:00:34 PM PST 23
Peak memory 256232 kb
Host smart-7d86e20f-471b-4092-a394-934214022e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674
27437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3467427437
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2283277875
Short name T685
Test name
Test status
Simulation time 1792761021 ps
CPU time 52.6 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:58:23 PM PST 23
Peak memory 255208 kb
Host smart-3f385eab-1c8a-47af-b833-fd447b1e69ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22832
77875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2283277875
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2467057422
Short name T675
Test name
Test status
Simulation time 5796740767 ps
CPU time 503.71 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 01:06:18 PM PST 23
Peak memory 265152 kb
Host smart-9c9d958b-3f84-4fd4-8033-b24b6b6197b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467057422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2467057422
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2749880020
Short name T425
Test name
Test status
Simulation time 97778681144 ps
CPU time 1589.97 seconds
Started Dec 20 12:57:03 PM PST 23
Finished Dec 20 01:23:49 PM PST 23
Peak memory 273360 kb
Host smart-631a1b58-57a5-45af-baf8-c6fe600a873e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749880020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2749880020
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2469161858
Short name T319
Test name
Test status
Simulation time 49993495938 ps
CPU time 504.3 seconds
Started Dec 20 12:57:03 PM PST 23
Finished Dec 20 01:05:43 PM PST 23
Peak memory 247324 kb
Host smart-07a188a6-0c29-472b-b964-dd11d65da73f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469161858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2469161858
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.748165432
Short name T419
Test name
Test status
Simulation time 579667272 ps
CPU time 29.35 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 12:58:17 PM PST 23
Peak memory 248576 kb
Host smart-c4ccf80b-826f-4e3c-9d0c-9b3d6361158f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74816
5432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.748165432
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2320076533
Short name T461
Test name
Test status
Simulation time 605010191 ps
CPU time 10.66 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 247024 kb
Host smart-e53a4a70-4d93-44b3-9385-8357d45f4851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23200
76533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2320076533
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1191219413
Short name T84
Test name
Test status
Simulation time 3011527707 ps
CPU time 41.86 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:58:14 PM PST 23
Peak memory 255884 kb
Host smart-ec70d153-3c9a-498a-aa63-170edff02235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11912
19413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1191219413
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.657381271
Short name T402
Test name
Test status
Simulation time 277432422 ps
CPU time 8.11 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 250008 kb
Host smart-c4ad5a4f-7932-4cf2-b1e8-eb602408696a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65738
1271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.657381271
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.244646356
Short name T61
Test name
Test status
Simulation time 29628921959 ps
CPU time 1505.79 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 01:22:24 PM PST 23
Peak memory 289604 kb
Host smart-c6c11893-f3a7-45e0-8065-6da0780de6d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244646356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.244646356
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.210377208
Short name T294
Test name
Test status
Simulation time 15325337190 ps
CPU time 1290.08 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:19:06 PM PST 23
Peak memory 289328 kb
Host smart-981d32f7-43a8-4b8c-baa8-6c1a259e6b48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210377208 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.210377208
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3077757176
Short name T234
Test name
Test status
Simulation time 48475224 ps
CPU time 2.99 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 12:57:38 PM PST 23
Peak memory 249000 kb
Host smart-15c803b4-c223-4ad8-885b-1508ab9890b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3077757176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3077757176
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3224416478
Short name T457
Test name
Test status
Simulation time 946310514 ps
CPU time 21.77 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:58:02 PM PST 23
Peak memory 240524 kb
Host smart-d0aaf1cb-0461-4748-821a-54297bc581e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3224416478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3224416478
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.76449580
Short name T626
Test name
Test status
Simulation time 7343388825 ps
CPU time 150.5 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:00:06 PM PST 23
Peak memory 256192 kb
Host smart-3d7356a7-b516-4b9f-ae02-fa2204472dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76449
580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.76449580
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.10718610
Short name T586
Test name
Test status
Simulation time 1409442674 ps
CPU time 39.92 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 12:58:14 PM PST 23
Peak memory 248128 kb
Host smart-b7847a84-a860-4c9f-bef3-ab55c86d8dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10718
610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.10718610
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1015263372
Short name T340
Test name
Test status
Simulation time 106658824423 ps
CPU time 1564.9 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 01:23:38 PM PST 23
Peak memory 273380 kb
Host smart-f6629e0a-604b-4c17-bd16-a4425a152c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015263372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1015263372
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.834911854
Short name T439
Test name
Test status
Simulation time 29217584286 ps
CPU time 1740.05 seconds
Started Dec 20 12:57:03 PM PST 23
Finished Dec 20 01:26:19 PM PST 23
Peak memory 272396 kb
Host smart-c95cd1ff-0d21-4190-9037-c8cea7913dc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834911854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.834911854
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.4123265881
Short name T334
Test name
Test status
Simulation time 6663411625 ps
CPU time 211.5 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:01:26 PM PST 23
Peak memory 246636 kb
Host smart-d63687ad-fc95-4b5b-8679-26a2b5c8b279
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123265881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.4123265881
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2438773170
Short name T674
Test name
Test status
Simulation time 690648991 ps
CPU time 34.99 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:58:06 PM PST 23
Peak memory 248576 kb
Host smart-6d2a53b2-b813-4a3a-9ad0-963adacf6708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24387
73170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2438773170
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2214742183
Short name T378
Test name
Test status
Simulation time 94712977 ps
CPU time 5.03 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:57:57 PM PST 23
Peak memory 251232 kb
Host smart-20d156aa-25b0-45ca-837e-bff3253ac278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22147
42183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2214742183
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.89297054
Short name T281
Test name
Test status
Simulation time 466715589 ps
CPU time 13.27 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 12:57:46 PM PST 23
Peak memory 247808 kb
Host smart-f9b68cf9-c75e-4cd0-bbfc-79e691f96f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89297
054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.89297054
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3514266143
Short name T94
Test name
Test status
Simulation time 634731500 ps
CPU time 13.28 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 12:57:55 PM PST 23
Peak memory 248624 kb
Host smart-6ef13a9b-19f3-4a14-a00e-7813723d6086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35142
66143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3514266143
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1114538634
Short name T738
Test name
Test status
Simulation time 97461271536 ps
CPU time 2635.03 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 01:41:34 PM PST 23
Peak memory 289528 kb
Host smart-515e7b02-d551-464e-8738-86b04d7bc4f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114538634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1114538634
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1349069527
Short name T471
Test name
Test status
Simulation time 38571895194 ps
CPU time 2144.63 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 01:33:18 PM PST 23
Peak memory 285332 kb
Host smart-2d199e78-0ce7-4603-b9df-db272df4f2c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349069527 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1349069527
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1895199071
Short name T241
Test name
Test status
Simulation time 53780831 ps
CPU time 3.84 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:57:58 PM PST 23
Peak memory 248928 kb
Host smart-7b500dca-c8de-475c-ba69-9f36da2406ac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1895199071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1895199071
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1441983848
Short name T591
Test name
Test status
Simulation time 38354522600 ps
CPU time 991.59 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 01:14:17 PM PST 23
Peak memory 288728 kb
Host smart-be8cb8b4-93ad-4ca8-804e-071cb925d4c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441983848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1441983848
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2472225283
Short name T377
Test name
Test status
Simulation time 115431625 ps
CPU time 6.9 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:58:00 PM PST 23
Peak memory 240560 kb
Host smart-760cbfe8-2ff5-4f04-b985-f3994889b88c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2472225283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2472225283
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2601902775
Short name T499
Test name
Test status
Simulation time 2889947901 ps
CPU time 164.15 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 01:00:15 PM PST 23
Peak memory 256164 kb
Host smart-8664db4e-dd83-4d21-8de4-dc580fb7b237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26019
02775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2601902775
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.795541014
Short name T450
Test name
Test status
Simulation time 936443811 ps
CPU time 53.39 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:58:33 PM PST 23
Peak memory 256428 kb
Host smart-449e77c3-c08e-4655-902e-9e6d5abce4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79554
1014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.795541014
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3862793063
Short name T344
Test name
Test status
Simulation time 46489929757 ps
CPU time 1964.91 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:30:28 PM PST 23
Peak memory 286188 kb
Host smart-0bbd8028-6db3-4dd9-9d1c-5ae052784fac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862793063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3862793063
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1735870047
Short name T624
Test name
Test status
Simulation time 25805716147 ps
CPU time 1312.25 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 01:19:50 PM PST 23
Peak memory 265148 kb
Host smart-77e56104-ca7b-4bd4-9831-758598376314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735870047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1735870047
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.40884680
Short name T448
Test name
Test status
Simulation time 884948285 ps
CPU time 26.28 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:58:20 PM PST 23
Peak memory 248776 kb
Host smart-588aba2d-a2da-4713-bc69-08cbb4645064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40884
680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.40884680
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3832639662
Short name T677
Test name
Test status
Simulation time 3710548485 ps
CPU time 57.79 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:58:51 PM PST 23
Peak memory 247720 kb
Host smart-1612ccf9-cade-4926-818a-dd7baeab5cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38326
39662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3832639662
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3489406496
Short name T98
Test name
Test status
Simulation time 1743386875 ps
CPU time 26.24 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:58:11 PM PST 23
Peak memory 255780 kb
Host smart-42a743cc-0f79-4ce7-b5bd-6794c4c7ceb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34894
06496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3489406496
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.35328758
Short name T584
Test name
Test status
Simulation time 1227049036 ps
CPU time 30.59 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 12:58:18 PM PST 23
Peak memory 248592 kb
Host smart-26e0814f-4bdb-4d56-91c0-b010d2ca5151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35328
758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.35328758
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3281312269
Short name T522
Test name
Test status
Simulation time 1957833950 ps
CPU time 33.65 seconds
Started Dec 20 12:57:40 PM PST 23
Finished Dec 20 12:58:35 PM PST 23
Peak memory 249700 kb
Host smart-64b7888d-25c7-45b0-8312-cbd11a353b8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281312269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3281312269
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1198492575
Short name T619
Test name
Test status
Simulation time 190460491156 ps
CPU time 8232.66 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 03:15:08 PM PST 23
Peak memory 394688 kb
Host smart-ff06583d-e538-44a4-a4dd-ad5b1ec8acf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198492575 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1198492575
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.704549027
Short name T233
Test name
Test status
Simulation time 59237453 ps
CPU time 2.57 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:00 PM PST 23
Peak memory 248824 kb
Host smart-c860de8d-9146-4df1-9273-40f2a8bc8560
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=704549027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.704549027
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2756203012
Short name T375
Test name
Test status
Simulation time 13470217546 ps
CPU time 1311.11 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 01:18:54 PM PST 23
Peak memory 288808 kb
Host smart-685b98ba-c6cb-43c2-94e6-d33055886736
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756203012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2756203012
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2453179239
Short name T366
Test name
Test status
Simulation time 5110333813 ps
CPU time 49.48 seconds
Started Dec 20 12:56:24 PM PST 23
Finished Dec 20 12:57:20 PM PST 23
Peak memory 240528 kb
Host smart-101aac42-f937-4043-833a-eb07810f32d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2453179239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2453179239
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.142046392
Short name T503
Test name
Test status
Simulation time 7217086586 ps
CPU time 153.41 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 12:59:54 PM PST 23
Peak memory 256124 kb
Host smart-1afda898-a8f0-4e1e-bfac-6c41d9792979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14204
6392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.142046392
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1427018210
Short name T671
Test name
Test status
Simulation time 1667598125 ps
CPU time 25.21 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:21 PM PST 23
Peak memory 255112 kb
Host smart-8c7b78be-92ca-4141-adb9-6ad8a773ff88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14270
18210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1427018210
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4047318706
Short name T567
Test name
Test status
Simulation time 34173676079 ps
CPU time 1347 seconds
Started Dec 20 12:56:47 PM PST 23
Finished Dec 20 01:19:19 PM PST 23
Peak memory 289336 kb
Host smart-53cff658-e33c-453b-9260-f352d14dd1da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047318706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4047318706
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3072032685
Short name T480
Test name
Test status
Simulation time 15112482592 ps
CPU time 325.99 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 01:02:16 PM PST 23
Peak memory 255644 kb
Host smart-01784082-5648-4169-8cd2-0feedffe9c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072032685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3072032685
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1680250082
Short name T585
Test name
Test status
Simulation time 618340682 ps
CPU time 13.45 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 12:56:50 PM PST 23
Peak memory 248668 kb
Host smart-fd585c57-2f02-491c-a6e2-49279b017f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16802
50082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1680250082
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1768330150
Short name T593
Test name
Test status
Simulation time 45675360 ps
CPU time 5.85 seconds
Started Dec 20 12:56:37 PM PST 23
Finished Dec 20 12:56:48 PM PST 23
Peak memory 238916 kb
Host smart-2a4683a2-bac4-4244-8c13-e7426f0c1ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17683
30150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1768330150
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.4262274638
Short name T13
Test name
Test status
Simulation time 174629312 ps
CPU time 10.7 seconds
Started Dec 20 12:57:03 PM PST 23
Finished Dec 20 12:57:29 PM PST 23
Peak memory 269048 kb
Host smart-a41b4a98-1b1a-47d8-ae5f-dc3995477c1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4262274638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.4262274638
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3254414553
Short name T389
Test name
Test status
Simulation time 366819724 ps
CPU time 20.34 seconds
Started Dec 20 12:56:37 PM PST 23
Finished Dec 20 12:57:03 PM PST 23
Peak memory 254884 kb
Host smart-b492ac9c-4473-42de-82ce-1fd4ab0dd287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32544
14553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3254414553
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.270650873
Short name T582
Test name
Test status
Simulation time 843576568 ps
CPU time 46.36 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 12:57:51 PM PST 23
Peak memory 248648 kb
Host smart-743f59ca-1936-4f34-977c-330c06b3b39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27065
0873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.270650873
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1457222217
Short name T512
Test name
Test status
Simulation time 78380213243 ps
CPU time 1772.64 seconds
Started Dec 20 12:56:31 PM PST 23
Finished Dec 20 01:26:10 PM PST 23
Peak memory 289692 kb
Host smart-9e59e32b-1b0a-43cf-ab2a-a73cdfed4683
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457222217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1457222217
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2343305384
Short name T495
Test name
Test status
Simulation time 359217428802 ps
CPU time 8209.89 seconds
Started Dec 20 12:56:42 PM PST 23
Finished Dec 20 03:13:38 PM PST 23
Peak memory 394652 kb
Host smart-aacbb0f0-1642-403f-9c90-6e6d5e58cde4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343305384 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2343305384
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.80907394
Short name T613
Test name
Test status
Simulation time 64148146711 ps
CPU time 1907.98 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 01:29:33 PM PST 23
Peak memory 273368 kb
Host smart-722bef4f-a7b8-4f04-b992-ef7dc3fc6c92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80907394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.80907394
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2756602948
Short name T500
Test name
Test status
Simulation time 2579271502 ps
CPU time 145.75 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:00:20 PM PST 23
Peak memory 248368 kb
Host smart-fe3ead34-9c41-4be2-9da5-740b411a15d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27566
02948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2756602948
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2439969066
Short name T95
Test name
Test status
Simulation time 220103148 ps
CPU time 12.94 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 254388 kb
Host smart-686f0256-ac7e-4e99-8cf3-c088b53e1f8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24399
69066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2439969066
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1840762852
Short name T339
Test name
Test status
Simulation time 23423238054 ps
CPU time 1583.84 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 01:24:04 PM PST 23
Peak memory 288780 kb
Host smart-a09454f1-eccd-43b9-90a6-b5ade667f3ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840762852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1840762852
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3270726113
Short name T663
Test name
Test status
Simulation time 20345745531 ps
CPU time 870.15 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 01:12:21 PM PST 23
Peak memory 272192 kb
Host smart-b8914c42-4ff6-4669-8cb7-3ccbdbb5b171
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270726113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3270726113
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2810972193
Short name T449
Test name
Test status
Simulation time 54400125006 ps
CPU time 501.11 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 01:05:54 PM PST 23
Peak memory 248608 kb
Host smart-49fa4b42-b10d-462d-8116-75e739a3b29a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810972193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2810972193
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3502139329
Short name T89
Test name
Test status
Simulation time 752357266 ps
CPU time 22.66 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 12:57:58 PM PST 23
Peak memory 248764 kb
Host smart-705383f3-e808-4a5d-ae01-e02022e78c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35021
39329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3502139329
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.26487135
Short name T614
Test name
Test status
Simulation time 651302380 ps
CPU time 38.08 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:58:23 PM PST 23
Peak memory 255156 kb
Host smart-51497e27-4b8f-463d-b465-5efdd9b00c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26487
135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.26487135
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1257272235
Short name T714
Test name
Test status
Simulation time 816569329 ps
CPU time 27.77 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 247048 kb
Host smart-6ebdfff2-eaf3-4d83-8098-2861e0e0323d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12572
72235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1257272235
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1044823119
Short name T534
Test name
Test status
Simulation time 220847113 ps
CPU time 17.58 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 12:57:58 PM PST 23
Peak memory 248652 kb
Host smart-e07a319d-0412-4dff-980b-c560934f2f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10448
23119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1044823119
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3029951506
Short name T287
Test name
Test status
Simulation time 114009894307 ps
CPU time 2985.04 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 01:47:43 PM PST 23
Peak memory 289712 kb
Host smart-059d34a2-018f-462b-a07d-2a728a7bc458
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029951506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3029951506
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2619492095
Short name T293
Test name
Test status
Simulation time 66877442503 ps
CPU time 3753.74 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 01:59:59 PM PST 23
Peak memory 306092 kb
Host smart-fe6bb960-5124-4169-a19b-52d25f76d4e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619492095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2619492095
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1135130725
Short name T408
Test name
Test status
Simulation time 140805326507 ps
CPU time 1902.21 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:29:19 PM PST 23
Peak memory 281644 kb
Host smart-73379f2a-e5c0-4c04-95e0-0e686e00d3d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135130725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1135130725
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2167755833
Short name T428
Test name
Test status
Simulation time 32713399 ps
CPU time 2.96 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:57:55 PM PST 23
Peak memory 238620 kb
Host smart-d7d8a867-2ca0-48af-b17f-f298b29e5d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21677
55833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2167755833
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3767897425
Short name T662
Test name
Test status
Simulation time 4295876536 ps
CPU time 43.82 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 12:58:35 PM PST 23
Peak memory 255384 kb
Host smart-a216d6a3-36b4-441d-bf59-f743632f8adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
97425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3767897425
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.4285156835
Short name T590
Test name
Test status
Simulation time 70983593068 ps
CPU time 2204.31 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 01:34:31 PM PST 23
Peak memory 289032 kb
Host smart-a9f96729-dedf-40d3-9d2f-8f5ec3ff036a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285156835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.4285156835
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1518733618
Short name T474
Test name
Test status
Simulation time 86035706930 ps
CPU time 921.25 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 01:13:15 PM PST 23
Peak memory 281308 kb
Host smart-583371c0-d136-41a9-ae59-07dc9dbf9730
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518733618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1518733618
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3905377666
Short name T317
Test name
Test status
Simulation time 10713409816 ps
CPU time 214.96 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 01:01:21 PM PST 23
Peak memory 247580 kb
Host smart-b971d338-b397-43f2-a978-344d50e882c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905377666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3905377666
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4116824107
Short name T361
Test name
Test status
Simulation time 891078489 ps
CPU time 26.48 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:54 PM PST 23
Peak memory 248560 kb
Host smart-cb8070d0-5cc5-4720-b912-73f37de15d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41168
24107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4116824107
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3599600302
Short name T255
Test name
Test status
Simulation time 3380425545 ps
CPU time 56.29 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 12:58:40 PM PST 23
Peak memory 255948 kb
Host smart-c0cc1863-f89e-4ee9-b6a8-33f2c18a0d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35996
00302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3599600302
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.4201370610
Short name T517
Test name
Test status
Simulation time 968643308 ps
CPU time 17.42 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:54 PM PST 23
Peak memory 254984 kb
Host smart-17fd46ac-f349-49c4-ae4f-6277e8631745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42013
70610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.4201370610
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.951142978
Short name T636
Test name
Test status
Simulation time 66894558 ps
CPU time 6.63 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 12:57:43 PM PST 23
Peak memory 253588 kb
Host smart-aa238205-c130-4953-b24f-8e1a21c9d720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95114
2978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.951142978
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4280417673
Short name T678
Test name
Test status
Simulation time 259002146045 ps
CPU time 3483.69 seconds
Started Dec 20 12:57:39 PM PST 23
Finished Dec 20 01:56:05 PM PST 23
Peak memory 281724 kb
Host smart-192343e9-a9d6-4351-9811-217905ac2e79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280417673 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4280417673
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1554153979
Short name T122
Test name
Test status
Simulation time 230016650147 ps
CPU time 3232.34 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 01:51:41 PM PST 23
Peak memory 288748 kb
Host smart-96b44631-620b-4242-88ea-17afa952e015
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554153979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1554153979
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2461637431
Short name T631
Test name
Test status
Simulation time 4090102767 ps
CPU time 102.5 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:59:22 PM PST 23
Peak memory 248748 kb
Host smart-76dc7d24-bb24-45e7-8150-0e8591451d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24616
37431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2461637431
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3854615137
Short name T737
Test name
Test status
Simulation time 241011534 ps
CPU time 10.1 seconds
Started Dec 20 12:57:38 PM PST 23
Finished Dec 20 12:58:11 PM PST 23
Peak memory 254228 kb
Host smart-80130b63-36c6-4fc2-ab31-0a4280d9cfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38546
15137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3854615137
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2727918589
Short name T252
Test name
Test status
Simulation time 72508355904 ps
CPU time 1049.61 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 01:15:19 PM PST 23
Peak memory 265204 kb
Host smart-eb2ded1b-356d-4a63-acf5-eba9f9ad95ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727918589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2727918589
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1954221041
Short name T115
Test name
Test status
Simulation time 30564245610 ps
CPU time 615.74 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:08:05 PM PST 23
Peak memory 273052 kb
Host smart-21013d19-5e77-4a4a-99d1-509abb97e882
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954221041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1954221041
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.865010366
Short name T468
Test name
Test status
Simulation time 44786481520 ps
CPU time 481.61 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:05:56 PM PST 23
Peak memory 246672 kb
Host smart-c50f0f13-7dce-4dcb-8f6a-590228ed3e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865010366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.865010366
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4224972454
Short name T578
Test name
Test status
Simulation time 406291371 ps
CPU time 21.08 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:58:12 PM PST 23
Peak memory 248576 kb
Host smart-915fd8fa-286a-4a08-b25f-17b66133da88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42249
72454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4224972454
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2736421473
Short name T26
Test name
Test status
Simulation time 578993129 ps
CPU time 35.31 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 248692 kb
Host smart-047c6b26-afe9-4a7f-9bb6-75a2b7d58590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27364
21473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2736421473
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1709882772
Short name T394
Test name
Test status
Simulation time 354389208 ps
CPU time 20.07 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:58:12 PM PST 23
Peak memory 254936 kb
Host smart-1945906b-f588-4c11-ae40-d2089cd583b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17098
82772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1709882772
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4264525586
Short name T491
Test name
Test status
Simulation time 1255203533 ps
CPU time 32.09 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:58:11 PM PST 23
Peak memory 248676 kb
Host smart-2476d797-fbf3-4e90-a04e-34c9764e3b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
25586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4264525586
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3118201882
Short name T379
Test name
Test status
Simulation time 89850918249 ps
CPU time 1536.83 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 01:23:24 PM PST 23
Peak memory 288960 kb
Host smart-9da11018-29e4-4609-a618-db81775282fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118201882 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3118201882
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1754857630
Short name T610
Test name
Test status
Simulation time 14172885635 ps
CPU time 1040.66 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 01:15:16 PM PST 23
Peak memory 284800 kb
Host smart-025c0e4c-8d01-4800-8aa5-3e5caa73172d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754857630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1754857630
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1425402374
Short name T52
Test name
Test status
Simulation time 10615343124 ps
CPU time 87.22 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 12:59:07 PM PST 23
Peak memory 256432 kb
Host smart-6b9e731d-a895-4895-b776-a015d2070257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14254
02374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1425402374
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1885017885
Short name T666
Test name
Test status
Simulation time 926985823 ps
CPU time 54.8 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:58:49 PM PST 23
Peak memory 255688 kb
Host smart-297ca975-5966-4fe3-8406-e455d7699cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18850
17885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1885017885
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3879425333
Short name T136
Test name
Test status
Simulation time 50184856886 ps
CPU time 1036.61 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:15:11 PM PST 23
Peak memory 269364 kb
Host smart-9aa32d1a-9be3-4b6a-bf11-d84bf968c706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879425333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3879425333
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2716286326
Short name T390
Test name
Test status
Simulation time 71927832650 ps
CPU time 1431.36 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:21:29 PM PST 23
Peak memory 288792 kb
Host smart-ae227bd1-3201-411a-b315-b71d195fdb31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716286326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2716286326
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3990286079
Short name T224
Test name
Test status
Simulation time 12686653743 ps
CPU time 512.88 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 01:06:26 PM PST 23
Peak memory 246356 kb
Host smart-c106a2d4-a5a1-4638-9f89-8b741407b417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990286079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3990286079
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2665921508
Short name T670
Test name
Test status
Simulation time 1576008482 ps
CPU time 22 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 12:58:04 PM PST 23
Peak memory 255084 kb
Host smart-ad59b20a-fdf2-4df1-8236-b343e2b182c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
21508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2665921508
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2773181695
Short name T709
Test name
Test status
Simulation time 398702877 ps
CPU time 10.47 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 12:58:02 PM PST 23
Peak memory 252608 kb
Host smart-0a04c9de-8e33-4c41-ad79-1dc7256d2ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27731
81695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2773181695
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.907888734
Short name T707
Test name
Test status
Simulation time 214989605 ps
CPU time 22.75 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 12:58:22 PM PST 23
Peak memory 248660 kb
Host smart-7d6a3cc8-4ea3-475a-b8ee-8aa63adf2179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90788
8734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.907888734
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1785441854
Short name T137
Test name
Test status
Simulation time 635973864 ps
CPU time 41.4 seconds
Started Dec 20 12:57:56 PM PST 23
Finished Dec 20 12:58:52 PM PST 23
Peak memory 248640 kb
Host smart-d935ae77-70f2-4bf6-8ef8-8bffcca6816a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
41854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1785441854
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2442735674
Short name T489
Test name
Test status
Simulation time 440130062141 ps
CPU time 2474.27 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 01:39:02 PM PST 23
Peak memory 305828 kb
Host smart-7401bc52-ca39-41c9-aacc-da494b8798d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442735674 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2442735674
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2356967641
Short name T266
Test name
Test status
Simulation time 245018337232 ps
CPU time 1534.93 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 01:23:02 PM PST 23
Peak memory 272912 kb
Host smart-99cf1557-7e42-432f-b382-3767fa371e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356967641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2356967641
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.60347366
Short name T516
Test name
Test status
Simulation time 2312738788 ps
CPU time 91.98 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 12:59:16 PM PST 23
Peak memory 256360 kb
Host smart-fb9ad90c-2418-4ee7-8d2a-b21808cd5e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60347
366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.60347366
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.4264199180
Short name T536
Test name
Test status
Simulation time 64351464 ps
CPU time 4.85 seconds
Started Dec 20 12:57:35 PM PST 23
Finished Dec 20 12:58:01 PM PST 23
Peak memory 238936 kb
Host smart-6df298e9-f3aa-4a3e-ac2c-c6243e0f277c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42641
99180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.4264199180
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4015833537
Short name T682
Test name
Test status
Simulation time 7169374813 ps
CPU time 622.04 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 01:08:03 PM PST 23
Peak memory 265028 kb
Host smart-c0982972-9e00-465a-b909-47126549db18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015833537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4015833537
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2460119743
Short name T318
Test name
Test status
Simulation time 4008083089 ps
CPU time 161 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 01:00:14 PM PST 23
Peak memory 247400 kb
Host smart-7542adb0-34c8-497e-bd13-db3298338d1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460119743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2460119743
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.315075114
Short name T404
Test name
Test status
Simulation time 534624627 ps
CPU time 23.28 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 12:57:47 PM PST 23
Peak memory 248752 kb
Host smart-57d92832-52b8-4eee-8c0e-ac63f1bba640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31507
5114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.315075114
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3514241803
Short name T518
Test name
Test status
Simulation time 527905452 ps
CPU time 35.64 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:58:29 PM PST 23
Peak memory 246732 kb
Host smart-4d71ed3d-438c-4712-b03b-2dce31b8d14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35142
41803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3514241803
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2407992583
Short name T292
Test name
Test status
Simulation time 274236156 ps
CPU time 27.33 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:58:17 PM PST 23
Peak memory 248616 kb
Host smart-7f4df197-35e8-4025-a1b0-7cebc2fe6c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24079
92583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2407992583
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3443001407
Short name T549
Test name
Test status
Simulation time 759206364 ps
CPU time 42.59 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 12:58:27 PM PST 23
Peak memory 248756 kb
Host smart-aad87dd8-f15d-44e6-9424-21d35e24c9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34430
01407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3443001407
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.442800048
Short name T606
Test name
Test status
Simulation time 96623854035 ps
CPU time 2041.45 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 01:31:42 PM PST 23
Peak memory 305804 kb
Host smart-1fb3341e-0f78-4f30-a5e9-39b982feaf62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442800048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.442800048
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3458704671
Short name T676
Test name
Test status
Simulation time 183209828368 ps
CPU time 715.18 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:09:39 PM PST 23
Peak memory 272744 kb
Host smart-7b91b9c9-94ba-4b52-a435-bd6270722318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458704671 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3458704671
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.742288123
Short name T627
Test name
Test status
Simulation time 49941239277 ps
CPU time 2857.65 seconds
Started Dec 20 12:57:40 PM PST 23
Finished Dec 20 01:45:40 PM PST 23
Peak memory 289580 kb
Host smart-bc8fd712-5b9d-4e8d-8747-14e91af6a92b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742288123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.742288123
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1035511706
Short name T673
Test name
Test status
Simulation time 9330371997 ps
CPU time 73.82 seconds
Started Dec 20 12:57:40 PM PST 23
Finished Dec 20 12:59:16 PM PST 23
Peak memory 256116 kb
Host smart-f4ca3e03-4f9f-43de-8331-bb4ca5c9e72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10355
11706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1035511706
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.135392121
Short name T696
Test name
Test status
Simulation time 406879783 ps
CPU time 21.45 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:58:15 PM PST 23
Peak memory 248132 kb
Host smart-d918785a-3d91-4fa1-8b39-e7d51336cbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
2121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.135392121
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.879919594
Short name T496
Test name
Test status
Simulation time 182391668230 ps
CPU time 2454.57 seconds
Started Dec 20 12:57:39 PM PST 23
Finished Dec 20 01:38:56 PM PST 23
Peak memory 289200 kb
Host smart-acdc4798-2545-45bf-9b34-e897b69a8017
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879919594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.879919594
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3194205397
Short name T257
Test name
Test status
Simulation time 61559163959 ps
CPU time 1044.93 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 01:14:56 PM PST 23
Peak memory 264856 kb
Host smart-d6424d95-6623-4643-ab5e-3cf19bb816dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194205397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3194205397
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.13063683
Short name T11
Test name
Test status
Simulation time 12050972674 ps
CPU time 118.07 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:59:45 PM PST 23
Peak memory 247380 kb
Host smart-78a62d03-1fd2-4760-b785-7140b20354c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13063683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.13063683
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.271075763
Short name T407
Test name
Test status
Simulation time 247993514 ps
CPU time 11.03 seconds
Started Dec 20 12:57:20 PM PST 23
Finished Dec 20 12:57:50 PM PST 23
Peak memory 248660 kb
Host smart-f21ccce3-50fc-4849-aaec-c47366d388ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27107
5763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.271075763
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.523730056
Short name T479
Test name
Test status
Simulation time 2907721336 ps
CPU time 49.28 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 12:58:47 PM PST 23
Peak memory 255052 kb
Host smart-4cce1038-5166-44c7-a6fe-166100f0e1fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52373
0056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.523730056
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.141540377
Short name T440
Test name
Test status
Simulation time 234968020 ps
CPU time 8.47 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 248648 kb
Host smart-1b5b2525-7e7a-4966-9b61-0250ed6bd18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
0377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.141540377
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3089701875
Short name T460
Test name
Test status
Simulation time 487731116 ps
CPU time 9.31 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 253384 kb
Host smart-d14ff7fb-2587-4107-95a0-fa8225bb9002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30897
01875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3089701875
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.365692968
Short name T88
Test name
Test status
Simulation time 1129814024 ps
CPU time 103.2 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 12:59:27 PM PST 23
Peak memory 256928 kb
Host smart-f513d498-410f-4c22-aa84-dffccc878629
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365692968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.365692968
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1680746643
Short name T279
Test name
Test status
Simulation time 36528938092 ps
CPU time 2035.68 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 01:31:44 PM PST 23
Peak memory 289000 kb
Host smart-546abe19-1db2-4246-9e95-54cd3e2adefa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680746643 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1680746643
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2501895013
Short name T269
Test name
Test status
Simulation time 46633303199 ps
CPU time 975.44 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 01:14:09 PM PST 23
Peak memory 288792 kb
Host smart-6b47e8d0-df1f-4a03-8bfb-e47780cd4a3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501895013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2501895013
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3786947385
Short name T588
Test name
Test status
Simulation time 1174631086 ps
CPU time 78.44 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:59:03 PM PST 23
Peak memory 256476 kb
Host smart-17fcce9a-0509-42b0-aac8-afc5eca5f8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37869
47385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3786947385
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.549245047
Short name T505
Test name
Test status
Simulation time 295459375 ps
CPU time 25.21 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 12:58:20 PM PST 23
Peak memory 247868 kb
Host smart-8eee9063-dfac-4048-9ea5-c3e09148e454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54924
5047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.549245047
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1796900371
Short name T444
Test name
Test status
Simulation time 10295781770 ps
CPU time 764.42 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 01:10:42 PM PST 23
Peak memory 272400 kb
Host smart-4f19461c-5db0-42be-a246-201f14e87d2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796900371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1796900371
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3602769724
Short name T327
Test name
Test status
Simulation time 11076579047 ps
CPU time 225.15 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:01:40 PM PST 23
Peak memory 247480 kb
Host smart-80ecd164-7b38-40df-8c6d-8eebb660ca63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602769724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3602769724
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3791342537
Short name T141
Test name
Test status
Simulation time 219221360 ps
CPU time 19.42 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 12:58:17 PM PST 23
Peak memory 248744 kb
Host smart-9199c01a-37b1-4a2c-9275-83d5c1e3d0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37913
42537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3791342537
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.264031403
Short name T628
Test name
Test status
Simulation time 1689488582 ps
CPU time 53.03 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:58:43 PM PST 23
Peak memory 255772 kb
Host smart-868cc908-1bb4-4808-9ac4-f0434bec0506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26403
1403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.264031403
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.299515305
Short name T80
Test name
Test status
Simulation time 716669204 ps
CPU time 44.2 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 12:58:43 PM PST 23
Peak memory 256196 kb
Host smart-27919654-0695-4c9a-ad6c-1113f232cfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29951
5305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.299515305
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2590914336
Short name T399
Test name
Test status
Simulation time 716802966 ps
CPU time 17.13 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:55 PM PST 23
Peak memory 248800 kb
Host smart-fa7d4c93-0135-4a04-8371-650cea826aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25909
14336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2590914336
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3547409033
Short name T108
Test name
Test status
Simulation time 439421297526 ps
CPU time 1667.24 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 01:25:27 PM PST 23
Peak memory 289948 kb
Host smart-954c3f79-7aea-489b-bfaa-f95d59ad2cd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547409033 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3547409033
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3713563238
Short name T470
Test name
Test status
Simulation time 9326128202 ps
CPU time 735.6 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:09:52 PM PST 23
Peak memory 273204 kb
Host smart-e778524d-d6fd-4194-80d4-ec7f13ea3939
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713563238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3713563238
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3989218075
Short name T420
Test name
Test status
Simulation time 1380501090 ps
CPU time 72.09 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 12:58:48 PM PST 23
Peak memory 248240 kb
Host smart-651816d4-8aba-4865-bb51-d6ad0d842e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
18075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3989218075
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2156507300
Short name T679
Test name
Test status
Simulation time 861564557 ps
CPU time 47.25 seconds
Started Dec 20 12:56:58 PM PST 23
Finished Dec 20 12:57:58 PM PST 23
Peak memory 255276 kb
Host smart-b05c45ee-e118-4c3d-a700-f8c11aa6218e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21565
07300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2156507300
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2999386772
Short name T571
Test name
Test status
Simulation time 44787452439 ps
CPU time 993.08 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 01:14:15 PM PST 23
Peak memory 273256 kb
Host smart-c7c6bcb4-5e28-4380-903d-3f31859257dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999386772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2999386772
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3799012781
Short name T117
Test name
Test status
Simulation time 61803874973 ps
CPU time 1678.63 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 01:25:45 PM PST 23
Peak memory 282476 kb
Host smart-9b711e94-c262-43f6-9f07-ae19ec85c7a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799012781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3799012781
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3509838693
Short name T273
Test name
Test status
Simulation time 12810291854 ps
CPU time 370.43 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:03:46 PM PST 23
Peak memory 247692 kb
Host smart-7b705dcb-bee3-4de6-adda-68b91ba1c099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509838693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3509838693
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1490821690
Short name T436
Test name
Test status
Simulation time 342063687 ps
CPU time 20.48 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:57:52 PM PST 23
Peak memory 255312 kb
Host smart-080b771b-ba30-403d-8632-e2cb44e54d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14908
21690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1490821690
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1405551094
Short name T430
Test name
Test status
Simulation time 332418441 ps
CPU time 30.3 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:58:15 PM PST 23
Peak memory 256248 kb
Host smart-25a47d8f-dcf3-40fc-ab60-7dda687ae1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14055
51094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1405551094
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2598511440
Short name T598
Test name
Test status
Simulation time 83058338 ps
CPU time 4.36 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:57:55 PM PST 23
Peak memory 240576 kb
Host smart-509f517e-c83c-4519-8310-3428b957cc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25985
11440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2598511440
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1996375361
Short name T545
Test name
Test status
Simulation time 3383454881 ps
CPU time 30.69 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 248696 kb
Host smart-50517b18-3cb1-4c64-a512-403a465f4273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963
75361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1996375361
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.828876778
Short name T106
Test name
Test status
Simulation time 14486499173 ps
CPU time 89.7 seconds
Started Dec 20 12:57:08 PM PST 23
Finished Dec 20 12:58:53 PM PST 23
Peak memory 257072 kb
Host smart-a27039c2-9715-4445-871b-68b97d4a4ca3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828876778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.828876778
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3326324433
Short name T303
Test name
Test status
Simulation time 12802717984 ps
CPU time 760.56 seconds
Started Dec 20 12:57:22 PM PST 23
Finished Dec 20 01:10:21 PM PST 23
Peak memory 269724 kb
Host smart-4fe831d6-a27d-483f-b1a6-8c70bd5f1116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326324433 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3326324433
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3863997315
Short name T246
Test name
Test status
Simulation time 222563646946 ps
CPU time 2494.95 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 01:39:21 PM PST 23
Peak memory 289772 kb
Host smart-ca721362-66e7-4a12-b919-9070777af4fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863997315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3863997315
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3076465040
Short name T48
Test name
Test status
Simulation time 4627896454 ps
CPU time 96.35 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:59:16 PM PST 23
Peak memory 249720 kb
Host smart-9cd8f9e1-8aa7-41e1-b57a-62d2b9037a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30764
65040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3076465040
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1958102489
Short name T424
Test name
Test status
Simulation time 260738686 ps
CPU time 14.4 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:57:42 PM PST 23
Peak memory 253688 kb
Host smart-0cb2a0a2-e30c-47f2-b649-29d175bb08a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19581
02489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1958102489
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1979080096
Short name T337
Test name
Test status
Simulation time 89239491167 ps
CPU time 1655.19 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 01:25:21 PM PST 23
Peak memory 272124 kb
Host smart-d1477bf1-72f9-4ca8-a098-6ba247fa5b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979080096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1979080096
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3393527161
Short name T635
Test name
Test status
Simulation time 19900616959 ps
CPU time 1238 seconds
Started Dec 20 12:57:06 PM PST 23
Finished Dec 20 01:18:01 PM PST 23
Peak memory 272168 kb
Host smart-7eb581b0-a84c-4ed1-b239-3c086a194cb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393527161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3393527161
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.795787841
Short name T557
Test name
Test status
Simulation time 55440308 ps
CPU time 3.75 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 240380 kb
Host smart-6318497c-51fc-4ae3-9b2d-84a5c3ed62b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79578
7841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.795787841
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.958136777
Short name T597
Test name
Test status
Simulation time 318092778 ps
CPU time 29.05 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 255612 kb
Host smart-a6f0f5a3-3301-4a17-b90b-7c049017f1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95813
6777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.958136777
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4036781233
Short name T270
Test name
Test status
Simulation time 445840335 ps
CPU time 12.92 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 12:57:38 PM PST 23
Peak memory 248740 kb
Host smart-6752d9d4-8bce-4499-8bcd-e6e823f6e254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40367
81233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4036781233
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1098008432
Short name T723
Test name
Test status
Simulation time 1858235002 ps
CPU time 54.12 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 12:58:27 PM PST 23
Peak memory 248776 kb
Host smart-2337629e-2504-49ad-a5a8-d980d13c3fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10980
08432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1098008432
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3949741427
Short name T435
Test name
Test status
Simulation time 97987291931 ps
CPU time 1145.34 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 01:16:47 PM PST 23
Peak memory 264784 kb
Host smart-478f93c5-9ea7-4875-a400-5898c08aa0e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949741427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3949741427
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3437085679
Short name T651
Test name
Test status
Simulation time 410368106 ps
CPU time 37.55 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 12:58:33 PM PST 23
Peak memory 256028 kb
Host smart-767488a8-44ef-4847-abf1-04e647d127af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34370
85679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3437085679
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.170927137
Short name T369
Test name
Test status
Simulation time 4147661309 ps
CPU time 20.87 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 12:57:56 PM PST 23
Peak memory 254668 kb
Host smart-f259eb5a-62e5-4622-98d1-1f2f6e46bca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
7137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.170927137
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1273670163
Short name T314
Test name
Test status
Simulation time 203291857363 ps
CPU time 2484.52 seconds
Started Dec 20 12:57:03 PM PST 23
Finished Dec 20 01:38:44 PM PST 23
Peak memory 281684 kb
Host smart-68058af5-3b68-43e8-8c21-b052aa4fc45c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273670163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1273670163
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.136370048
Short name T555
Test name
Test status
Simulation time 36258578832 ps
CPU time 1996.56 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 01:31:06 PM PST 23
Peak memory 285432 kb
Host smart-2d7699af-687c-4fb5-87f7-abbcbeb8aed5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136370048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.136370048
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3099884198
Short name T332
Test name
Test status
Simulation time 63635716733 ps
CPU time 517.74 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 01:06:06 PM PST 23
Peak memory 247880 kb
Host smart-086e81bd-b49d-41b7-addd-7d0c2afd97c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099884198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3099884198
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.36264818
Short name T90
Test name
Test status
Simulation time 2254132882 ps
CPU time 33.93 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:58:05 PM PST 23
Peak memory 248908 kb
Host smart-012a59af-c6f2-4be6-9a99-e972c4c4d9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36264
818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.36264818
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2342351724
Short name T24
Test name
Test status
Simulation time 3740203174 ps
CPU time 50.98 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:58:18 PM PST 23
Peak memory 254696 kb
Host smart-fbba421d-178d-42fc-8fef-c30ff0e125df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23423
51724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2342351724
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1997041710
Short name T291
Test name
Test status
Simulation time 1636892874 ps
CPU time 49.73 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 12:58:26 PM PST 23
Peak memory 247260 kb
Host smart-11cf5a93-4fb1-4ce3-bba8-66e3ad28d3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19970
41710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1997041710
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2038928229
Short name T431
Test name
Test status
Simulation time 1176492009 ps
CPU time 22.99 seconds
Started Dec 20 12:57:08 PM PST 23
Finished Dec 20 12:57:47 PM PST 23
Peak memory 255580 kb
Host smart-e9ab8b63-4234-472f-ab3c-5aec3602246e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20389
28229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2038928229
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2101418806
Short name T548
Test name
Test status
Simulation time 36619176602 ps
CPU time 2119.1 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 01:32:56 PM PST 23
Peak memory 289364 kb
Host smart-8bd2eb15-5549-46cf-aa44-71de5789394e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101418806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2101418806
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3654261588
Short name T309
Test name
Test status
Simulation time 318342645160 ps
CPU time 4690.56 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 02:15:42 PM PST 23
Peak memory 322140 kb
Host smart-a78301a6-e418-4212-9e4a-ab9d74630b7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654261588 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3654261588
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4090496787
Short name T239
Test name
Test status
Simulation time 56471000 ps
CPU time 2.72 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:57:06 PM PST 23
Peak memory 248944 kb
Host smart-bcad418d-3d79-4983-bae4-30b01d707000
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4090496787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4090496787
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2963687322
Short name T251
Test name
Test status
Simulation time 38277658930 ps
CPU time 2016.85 seconds
Started Dec 20 12:56:59 PM PST 23
Finished Dec 20 01:30:50 PM PST 23
Peak memory 272592 kb
Host smart-b3b8a16f-59e2-4292-ab81-c0b55dfb1e78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963687322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2963687322
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1517306274
Short name T484
Test name
Test status
Simulation time 928337589 ps
CPU time 12.22 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:57:43 PM PST 23
Peak memory 240548 kb
Host smart-0b29fba1-abc1-4f61-afed-86bb6a12aae6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1517306274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1517306274
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3182825363
Short name T538
Test name
Test status
Simulation time 2293365216 ps
CPU time 147.86 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:59:28 PM PST 23
Peak memory 256288 kb
Host smart-4fbc64af-f485-4a5f-8b7a-75bbf7d4b5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31828
25363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3182825363
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1048122859
Short name T403
Test name
Test status
Simulation time 362309362 ps
CPU time 16.18 seconds
Started Dec 20 12:56:42 PM PST 23
Finished Dec 20 12:57:03 PM PST 23
Peak memory 248176 kb
Host smart-408ecdd6-2ad2-43a0-bc03-d95d4f31bb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10481
22859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1048122859
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3753380118
Short name T328
Test name
Test status
Simulation time 41841249111 ps
CPU time 1593.59 seconds
Started Dec 20 12:56:43 PM PST 23
Finished Dec 20 01:23:22 PM PST 23
Peak memory 288660 kb
Host smart-1df13afd-a6bd-412f-8215-5b8160f1fa30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753380118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3753380118
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1383178419
Short name T604
Test name
Test status
Simulation time 34318384070 ps
CPU time 1831.07 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 01:27:37 PM PST 23
Peak memory 281616 kb
Host smart-e2f336ef-1bf8-4d2d-8606-c5cec13c2fcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383178419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1383178419
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2635284899
Short name T535
Test name
Test status
Simulation time 206586430 ps
CPU time 20.94 seconds
Started Dec 20 12:56:36 PM PST 23
Finished Dec 20 12:57:02 PM PST 23
Peak memory 248708 kb
Host smart-90a9d046-190e-413d-b6e1-f1dd300c5ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26352
84899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2635284899
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.304516523
Short name T113
Test name
Test status
Simulation time 699669786 ps
CPU time 12.49 seconds
Started Dec 20 12:56:36 PM PST 23
Finished Dec 20 12:56:54 PM PST 23
Peak memory 255140 kb
Host smart-ff830e37-33fa-473d-a112-195ccc069e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
6523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.304516523
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1899749137
Short name T14
Test name
Test status
Simulation time 2630167849 ps
CPU time 21.07 seconds
Started Dec 20 12:56:47 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 269844 kb
Host smart-e893d68b-969a-47a7-be5c-22a74250535b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1899749137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1899749137
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2111976087
Short name T577
Test name
Test status
Simulation time 221172493 ps
CPU time 22.67 seconds
Started Dec 20 12:56:43 PM PST 23
Finished Dec 20 12:57:10 PM PST 23
Peak memory 247764 kb
Host smart-66a12f42-2843-41da-b52f-134ec0669142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21119
76087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2111976087
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.102768125
Short name T363
Test name
Test status
Simulation time 211860636 ps
CPU time 9.69 seconds
Started Dec 20 12:56:32 PM PST 23
Finished Dec 20 12:56:47 PM PST 23
Peak memory 248752 kb
Host smart-12504865-11f9-4c24-91ab-bae1dab70508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10276
8125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.102768125
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.4185476224
Short name T74
Test name
Test status
Simulation time 138176217963 ps
CPU time 4312.64 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 02:09:16 PM PST 23
Peak memory 305704 kb
Host smart-9037aa03-ee49-42df-9757-c6955381579b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185476224 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.4185476224
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3916603542
Short name T78
Test name
Test status
Simulation time 68846248844 ps
CPU time 838.69 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:11:36 PM PST 23
Peak memory 268224 kb
Host smart-0fbbac70-b8b7-427e-9b63-94f25e17440a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916603542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3916603542
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.855840858
Short name T558
Test name
Test status
Simulation time 7001616713 ps
CPU time 139.94 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 01:00:02 PM PST 23
Peak memory 256120 kb
Host smart-b641d353-c621-479d-babd-7ccb9c4ff0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85584
0858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.855840858
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1001400877
Short name T256
Test name
Test status
Simulation time 986162101 ps
CPU time 30.29 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 12:58:19 PM PST 23
Peak memory 248884 kb
Host smart-a5884520-d763-4d32-9b2f-42af88f78073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10014
00877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1001400877
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3426680425
Short name T463
Test name
Test status
Simulation time 69606524772 ps
CPU time 2010.49 seconds
Started Dec 20 12:57:20 PM PST 23
Finished Dec 20 01:31:09 PM PST 23
Peak memory 286952 kb
Host smart-52d05155-c337-419b-8940-d15957618058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426680425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3426680425
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3343964009
Short name T533
Test name
Test status
Simulation time 149450177167 ps
CPU time 1160.72 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 01:16:49 PM PST 23
Peak memory 265060 kb
Host smart-9fa5c213-03e7-43c5-9ee9-4cb52047a289
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343964009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3343964009
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.834957714
Short name T331
Test name
Test status
Simulation time 41136483609 ps
CPU time 419.4 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:04:36 PM PST 23
Peak memory 246660 kb
Host smart-d8e19e68-d040-4ad5-a58f-fb5f53bf7ac7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834957714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.834957714
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2578376243
Short name T469
Test name
Test status
Simulation time 551277714 ps
CPU time 14.51 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:58:00 PM PST 23
Peak memory 248816 kb
Host smart-21dd2469-f18e-4041-8983-b6e274f6fb6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25783
76243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2578376243
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3533895905
Short name T121
Test name
Test status
Simulation time 60955776 ps
CPU time 7.04 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 12:57:41 PM PST 23
Peak memory 248704 kb
Host smart-5a606c4d-2fb3-46a6-ae3f-82de5e2ed00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35338
95905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3533895905
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2858710221
Short name T421
Test name
Test status
Simulation time 128533796 ps
CPU time 8.31 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:45 PM PST 23
Peak memory 250024 kb
Host smart-f75016c7-fd4f-411d-8860-82a26812eff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28587
10221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2858710221
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3857354163
Short name T467
Test name
Test status
Simulation time 3465168562 ps
CPU time 43.58 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 12:58:05 PM PST 23
Peak memory 248712 kb
Host smart-afb11247-e728-4919-9383-042876dbfe7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38573
54163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3857354163
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1829170669
Short name T371
Test name
Test status
Simulation time 4500569739 ps
CPU time 175.08 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 01:00:35 PM PST 23
Peak memory 256856 kb
Host smart-bce58917-be99-45a8-856b-e4a6d573720f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829170669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1829170669
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.983387444
Short name T510
Test name
Test status
Simulation time 35081758323 ps
CPU time 1956.09 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 01:30:35 PM PST 23
Peak memory 306048 kb
Host smart-a053113b-8286-4252-aec2-58736413c0b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983387444 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.983387444
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2671366629
Short name T393
Test name
Test status
Simulation time 395843927224 ps
CPU time 1591.62 seconds
Started Dec 20 12:57:42 PM PST 23
Finished Dec 20 01:24:35 PM PST 23
Peak memory 273428 kb
Host smart-2e6a2369-ba51-44d4-a730-f675bd78cb7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671366629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2671366629
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3059167357
Short name T527
Test name
Test status
Simulation time 2905506648 ps
CPU time 144.63 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:00:07 PM PST 23
Peak memory 256092 kb
Host smart-4276ddbc-b2b9-403a-a5af-af8688a3ad6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30591
67357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3059167357
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1027879559
Short name T702
Test name
Test status
Simulation time 508728890 ps
CPU time 28.48 seconds
Started Dec 20 12:57:35 PM PST 23
Finished Dec 20 12:58:25 PM PST 23
Peak memory 255228 kb
Host smart-97458013-a29f-4096-868c-8e4a0097b373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10278
79559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1027879559
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.713488067
Short name T346
Test name
Test status
Simulation time 40017557846 ps
CPU time 1196.81 seconds
Started Dec 20 12:57:39 PM PST 23
Finished Dec 20 01:17:58 PM PST 23
Peak memory 265084 kb
Host smart-b23ff59f-69a7-47fd-87e2-d9473dfcb04a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713488067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.713488067
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2518501758
Short name T563
Test name
Test status
Simulation time 12001774990 ps
CPU time 946.06 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 01:13:34 PM PST 23
Peak memory 272216 kb
Host smart-e4e3d583-ab19-4af6-9d34-6e6464fd5227
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518501758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2518501758
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3080397962
Short name T76
Test name
Test status
Simulation time 10863096398 ps
CPU time 100.85 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:59:34 PM PST 23
Peak memory 247688 kb
Host smart-13e66155-58c7-4aec-945c-a86541e6009a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080397962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3080397962
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.613774885
Short name T659
Test name
Test status
Simulation time 1952929651 ps
CPU time 28.58 seconds
Started Dec 20 12:57:49 PM PST 23
Finished Dec 20 12:58:35 PM PST 23
Peak memory 248756 kb
Host smart-8221644c-35a0-42fb-928c-53c61ed66644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61377
4885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.613774885
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1174196868
Short name T132
Test name
Test status
Simulation time 1689753911 ps
CPU time 28.77 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:58:19 PM PST 23
Peak memory 254636 kb
Host smart-b8363119-0982-4abc-9278-47fd11cf4231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11741
96868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1174196868
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1821201855
Short name T66
Test name
Test status
Simulation time 170954402 ps
CPU time 17.83 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 247044 kb
Host smart-a8dc2939-2b00-4fad-a884-86ca190e9073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18212
01855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1821201855
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.399705809
Short name T736
Test name
Test status
Simulation time 4602173702 ps
CPU time 33.35 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 12:58:21 PM PST 23
Peak memory 248652 kb
Host smart-cb472a2b-51c1-402f-8eda-26f38463321a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39970
5809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.399705809
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1696999148
Short name T418
Test name
Test status
Simulation time 729003410 ps
CPU time 62.78 seconds
Started Dec 20 12:57:30 PM PST 23
Finished Dec 20 12:58:55 PM PST 23
Peak memory 256856 kb
Host smart-39b5597c-bdde-4929-876c-8b68371390f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696999148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1696999148
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1617877724
Short name T599
Test name
Test status
Simulation time 107775949185 ps
CPU time 2820.89 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 01:44:57 PM PST 23
Peak memory 321760 kb
Host smart-321ea46f-8de3-471f-8a61-01f8332c79a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617877724 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1617877724
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.135303342
Short name T493
Test name
Test status
Simulation time 13553675841 ps
CPU time 994.84 seconds
Started Dec 20 12:57:27 PM PST 23
Finished Dec 20 01:14:23 PM PST 23
Peak memory 273376 kb
Host smart-b33c2ae2-4c34-4a32-8a4c-9a015384f52b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135303342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.135303342
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2024520638
Short name T727
Test name
Test status
Simulation time 3373625502 ps
CPU time 116.04 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 12:59:51 PM PST 23
Peak memory 256396 kb
Host smart-fae78bda-dd90-45c4-8830-db4c63efa091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20245
20638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2024520638
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.507132093
Short name T658
Test name
Test status
Simulation time 87923197 ps
CPU time 8.75 seconds
Started Dec 20 12:57:50 PM PST 23
Finished Dec 20 12:58:16 PM PST 23
Peak memory 254032 kb
Host smart-b8fd96e5-8f64-4bd6-9e08-4690c3b53188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50713
2093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.507132093
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.113225010
Short name T735
Test name
Test status
Simulation time 61486363693 ps
CPU time 1251.29 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 01:18:51 PM PST 23
Peak memory 283300 kb
Host smart-b19076f9-9727-4dd8-a226-d5448afa27f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113225010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.113225010
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1719627779
Short name T634
Test name
Test status
Simulation time 34859839897 ps
CPU time 1761.99 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:27:17 PM PST 23
Peak memory 282040 kb
Host smart-9e196a97-05d2-418f-8558-eb7d240093b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719627779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1719627779
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2165245406
Short name T607
Test name
Test status
Simulation time 12638112256 ps
CPU time 125.84 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:59:56 PM PST 23
Peak memory 246688 kb
Host smart-ea58a5c6-a233-470c-8dc1-83dc576465cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165245406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2165245406
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3140899
Short name T401
Test name
Test status
Simulation time 691945899 ps
CPU time 34.11 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 12:58:32 PM PST 23
Peak memory 254904 kb
Host smart-b4912836-1a60-4d67-8477-9715bc7f248e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31408
99 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3140899
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3101392694
Short name T72
Test name
Test status
Simulation time 940797833 ps
CPU time 24.92 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 12:58:07 PM PST 23
Peak memory 246988 kb
Host smart-d138d65e-ce34-42f7-a160-b3cc3c53b138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31013
92694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3101392694
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.199842280
Short name T310
Test name
Test status
Simulation time 1066129781 ps
CPU time 31.51 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:58:23 PM PST 23
Peak memory 247004 kb
Host smart-2c1230d6-f76e-4d87-b64c-59ce2b73f2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19984
2280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.199842280
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1277291672
Short name T721
Test name
Test status
Simulation time 184314285 ps
CPU time 15.67 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:58:01 PM PST 23
Peak memory 248704 kb
Host smart-4a5f63da-2aa8-48e5-849a-add409cfe6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12772
91672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1277291672
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1691244085
Short name T618
Test name
Test status
Simulation time 104409474354 ps
CPU time 2792.72 seconds
Started Dec 20 12:57:42 PM PST 23
Finished Dec 20 01:44:36 PM PST 23
Peak memory 289608 kb
Host smart-ec1decee-df98-41bd-91c4-9b8099679526
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691244085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1691244085
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.249592856
Short name T429
Test name
Test status
Simulation time 83797339721 ps
CPU time 2281.09 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 01:35:40 PM PST 23
Peak memory 289812 kb
Host smart-6648268f-f0e0-471f-ad3f-e91811932400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249592856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.249592856
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1137701025
Short name T442
Test name
Test status
Simulation time 738364598 ps
CPU time 7.67 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 12:58:02 PM PST 23
Peak memory 247028 kb
Host smart-97831bdc-6170-4076-8164-68bea944c878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11377
01025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1137701025
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2477041332
Short name T642
Test name
Test status
Simulation time 1612057988 ps
CPU time 45.25 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:58:36 PM PST 23
Peak memory 248312 kb
Host smart-32bbcb55-a076-4e19-998d-f69b98a07bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24770
41332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2477041332
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1151831777
Short name T615
Test name
Test status
Simulation time 189913678430 ps
CPU time 1456.06 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 01:22:11 PM PST 23
Peak memory 289212 kb
Host smart-5d52b455-6e8a-43e7-b194-69f314e6ccb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151831777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1151831777
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.854610956
Short name T488
Test name
Test status
Simulation time 4689374765 ps
CPU time 181.84 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 01:00:48 PM PST 23
Peak memory 246624 kb
Host smart-4f2672e7-757f-48d8-a781-ec41bcd5e647
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854610956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.854610956
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2289597784
Short name T616
Test name
Test status
Simulation time 251954200 ps
CPU time 21.37 seconds
Started Dec 20 12:57:42 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 248768 kb
Host smart-045d323b-9f3c-4e01-85d6-8d9a5269aafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22895
97784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2289597784
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3205466406
Short name T245
Test name
Test status
Simulation time 113099425 ps
CPU time 6.43 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:58:00 PM PST 23
Peak memory 246996 kb
Host smart-ceca6b51-281a-428f-a2db-1f1c1214ab01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32054
66406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3205466406
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1933185720
Short name T520
Test name
Test status
Simulation time 860138706 ps
CPU time 29.19 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 255256 kb
Host smart-e7a4afc3-3573-416d-afa5-ecae30cdcd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19331
85720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1933185720
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3905798581
Short name T485
Test name
Test status
Simulation time 392482991 ps
CPU time 21.34 seconds
Started Dec 20 12:57:25 PM PST 23
Finished Dec 20 12:58:06 PM PST 23
Peak memory 248720 kb
Host smart-75eb179a-c539-4472-8cd0-e6ac9c1341d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39057
98581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3905798581
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4178078641
Short name T681
Test name
Test status
Simulation time 963099038 ps
CPU time 76.6 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 12:59:11 PM PST 23
Peak memory 256760 kb
Host smart-cda2086e-f55e-4a0e-9989-6bd2c09c2dc0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178078641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4178078641
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.1091360147
Short name T547
Test name
Test status
Simulation time 126569711910 ps
CPU time 2828.01 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 01:45:03 PM PST 23
Peak memory 322260 kb
Host smart-45f170fc-ffab-4c6c-a094-0bd861fbde5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091360147 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.1091360147
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2047998194
Short name T145
Test name
Test status
Simulation time 22363009482 ps
CPU time 1356.59 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 01:20:33 PM PST 23
Peak memory 273416 kb
Host smart-303c40f0-e3f3-48c9-8d0c-c7ce66eeb354
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047998194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2047998194
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3379485272
Short name T573
Test name
Test status
Simulation time 2760875507 ps
CPU time 145.43 seconds
Started Dec 20 12:57:57 PM PST 23
Finished Dec 20 01:00:37 PM PST 23
Peak memory 248816 kb
Host smart-f73dff71-a9e4-4ee9-8946-74bacbc4b551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33794
85272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3379485272
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1752105485
Short name T689
Test name
Test status
Simulation time 2837690374 ps
CPU time 9.18 seconds
Started Dec 20 12:57:39 PM PST 23
Finished Dec 20 12:58:10 PM PST 23
Peak memory 251308 kb
Host smart-61d83caf-0478-4190-b539-001c646dc1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17521
05485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1752105485
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3693885364
Short name T341
Test name
Test status
Simulation time 123163051028 ps
CPU time 1769.4 seconds
Started Dec 20 12:58:00 PM PST 23
Finished Dec 20 01:27:44 PM PST 23
Peak memory 273376 kb
Host smart-a00c5f96-01e3-4920-bba8-c47c5719be4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693885364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3693885364
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2439801123
Short name T482
Test name
Test status
Simulation time 214510405968 ps
CPU time 2614.63 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 01:41:26 PM PST 23
Peak memory 289360 kb
Host smart-beea54be-ccbe-49b8-9f7c-56439b933561
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439801123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2439801123
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3900084326
Short name T316
Test name
Test status
Simulation time 36705456552 ps
CPU time 448.73 seconds
Started Dec 20 12:57:35 PM PST 23
Finished Dec 20 01:05:25 PM PST 23
Peak memory 248648 kb
Host smart-209a6e7a-180e-4a93-9003-de3c9d5325fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900084326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3900084326
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2824942196
Short name T283
Test name
Test status
Simulation time 401085704 ps
CPU time 19.97 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 12:58:09 PM PST 23
Peak memory 248716 kb
Host smart-357939ef-a3bb-4ba0-bd5e-15e2bcbe11c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28249
42196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2824942196
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.705262078
Short name T109
Test name
Test status
Simulation time 3242805348 ps
CPU time 46.38 seconds
Started Dec 20 12:57:38 PM PST 23
Finished Dec 20 12:58:46 PM PST 23
Peak memory 254532 kb
Host smart-bcf36cb6-26fc-417c-82ff-e42efa3ce1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70526
2078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.705262078
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1847252523
Short name T600
Test name
Test status
Simulation time 7619278358 ps
CPU time 31.68 seconds
Started Dec 20 12:57:33 PM PST 23
Finished Dec 20 12:58:26 PM PST 23
Peak memory 255580 kb
Host smart-aae1eeae-e231-49c2-9fb7-6c7edd41cf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18472
52523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1847252523
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4008146230
Short name T415
Test name
Test status
Simulation time 1329701725 ps
CPU time 29.98 seconds
Started Dec 20 12:57:28 PM PST 23
Finished Dec 20 12:58:19 PM PST 23
Peak memory 248664 kb
Host smart-18d8a5b0-17d2-47be-bb4c-675cc745169d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40081
46230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4008146230
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1519849178
Short name T73
Test name
Test status
Simulation time 77084929171 ps
CPU time 1805.4 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 01:27:59 PM PST 23
Peak memory 282060 kb
Host smart-1d7d75f2-8153-46b2-ad89-7080ac6dbf37
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519849178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1519849178
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2092566843
Short name T541
Test name
Test status
Simulation time 216613763940 ps
CPU time 6381.33 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 02:44:04 PM PST 23
Peak memory 337372 kb
Host smart-fd90b5d3-8f20-42f5-b227-ee13fdf10797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092566843 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2092566843
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1392338017
Short name T70
Test name
Test status
Simulation time 26482952989 ps
CPU time 957.68 seconds
Started Dec 20 12:57:45 PM PST 23
Finished Dec 20 01:14:03 PM PST 23
Peak memory 272160 kb
Host smart-3c5c6949-76a8-4467-ba77-3b3d23b58b61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392338017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1392338017
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2784169815
Short name T706
Test name
Test status
Simulation time 6561630045 ps
CPU time 98.96 seconds
Started Dec 20 12:57:51 PM PST 23
Finished Dec 20 12:59:47 PM PST 23
Peak memory 256056 kb
Host smart-9255ddad-de0b-476c-b1b2-0c2313be5878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27841
69815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2784169815
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3780004680
Short name T412
Test name
Test status
Simulation time 608677103 ps
CPU time 36.9 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 12:58:32 PM PST 23
Peak memory 248708 kb
Host smart-a5fa470e-f955-4a61-afd0-74734cc2e781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37800
04680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3780004680
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1220552519
Short name T711
Test name
Test status
Simulation time 53410239221 ps
CPU time 994.46 seconds
Started Dec 20 12:57:44 PM PST 23
Finished Dec 20 01:14:39 PM PST 23
Peak memory 285020 kb
Host smart-39b4a7af-95a4-4719-a8e3-5c6f604ff0e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220552519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1220552519
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1444471693
Short name T665
Test name
Test status
Simulation time 15502260891 ps
CPU time 658.27 seconds
Started Dec 20 12:57:53 PM PST 23
Finished Dec 20 01:09:07 PM PST 23
Peak memory 271876 kb
Host smart-50693ddc-6c03-4247-a29b-359c49450d62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444471693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1444471693
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2680128788
Short name T715
Test name
Test status
Simulation time 6752970608 ps
CPU time 163.73 seconds
Started Dec 20 12:57:53 PM PST 23
Finished Dec 20 01:00:52 PM PST 23
Peak memory 247404 kb
Host smart-ff939752-a199-4967-9189-fc41168462f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680128788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2680128788
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3483429052
Short name T385
Test name
Test status
Simulation time 2664822641 ps
CPU time 41.27 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 12:58:39 PM PST 23
Peak memory 248836 kb
Host smart-4428025e-98f5-4291-81d3-f19d027ae23b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34834
29052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3483429052
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1210778411
Short name T380
Test name
Test status
Simulation time 1416286231 ps
CPU time 27.41 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 248468 kb
Host smart-d20466c1-dc24-4ff0-b0e4-ace9d33a5a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12107
78411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1210778411
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2909571130
Short name T3
Test name
Test status
Simulation time 51061078 ps
CPU time 7.32 seconds
Started Dec 20 12:57:56 PM PST 23
Finished Dec 20 12:58:18 PM PST 23
Peak memory 240384 kb
Host smart-9718e062-fe69-4eab-aa46-7d4da84a4aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
71130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2909571130
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1127704016
Short name T667
Test name
Test status
Simulation time 139590508 ps
CPU time 11.53 seconds
Started Dec 20 12:57:40 PM PST 23
Finished Dec 20 12:58:13 PM PST 23
Peak memory 248776 kb
Host smart-e3c9c287-3132-4672-9cee-023b52e2125c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11277
04016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1127704016
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3784793060
Short name T275
Test name
Test status
Simulation time 82573330371 ps
CPU time 2638.3 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 01:41:57 PM PST 23
Peak memory 298448 kb
Host smart-0c89740d-f16d-4d10-b359-61bc16f39503
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784793060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3784793060
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3188938640
Short name T523
Test name
Test status
Simulation time 286235542556 ps
CPU time 5862.29 seconds
Started Dec 20 12:57:46 PM PST 23
Finished Dec 20 02:35:49 PM PST 23
Peak memory 338756 kb
Host smart-00872b28-7a35-4864-8829-fe5827aa8141
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188938640 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3188938640
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.102246920
Short name T127
Test name
Test status
Simulation time 37205922749 ps
CPU time 2060.54 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 01:32:18 PM PST 23
Peak memory 288036 kb
Host smart-e04593ad-8469-4014-8b5e-4b68f4fa5099
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102246920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.102246920
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1114187607
Short name T526
Test name
Test status
Simulation time 4329296058 ps
CPU time 119.16 seconds
Started Dec 20 12:58:06 PM PST 23
Finished Dec 20 01:00:22 PM PST 23
Peak memory 255944 kb
Host smart-5426bdca-81ce-4352-aee5-5ab2ea2e4741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11141
87607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1114187607
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3808074732
Short name T384
Test name
Test status
Simulation time 844016995 ps
CPU time 14.02 seconds
Started Dec 20 12:57:35 PM PST 23
Finished Dec 20 12:58:10 PM PST 23
Peak memory 252464 kb
Host smart-d8a5da51-9ec6-4a27-9a74-96fcba281fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38080
74732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3808074732
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3926068601
Short name T336
Test name
Test status
Simulation time 83292738291 ps
CPU time 1222.47 seconds
Started Dec 20 12:57:56 PM PST 23
Finished Dec 20 01:18:33 PM PST 23
Peak memory 284264 kb
Host smart-e4540977-37e5-4db8-b25c-a72bc458b612
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926068601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3926068601
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1178226440
Short name T576
Test name
Test status
Simulation time 161698195087 ps
CPU time 2130.27 seconds
Started Dec 20 12:57:50 PM PST 23
Finished Dec 20 01:33:38 PM PST 23
Peak memory 272708 kb
Host smart-f49cd517-965d-4a0e-9b4e-7e5fc332ab4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178226440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1178226440
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.985233021
Short name T226
Test name
Test status
Simulation time 3565141141 ps
CPU time 152.08 seconds
Started Dec 20 12:57:39 PM PST 23
Finished Dec 20 01:00:33 PM PST 23
Peak memory 247616 kb
Host smart-c84a9987-d715-49e7-a6aa-eac304f219e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985233021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.985233021
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.731125467
Short name T447
Test name
Test status
Simulation time 508430930 ps
CPU time 8 seconds
Started Dec 20 12:57:48 PM PST 23
Finished Dec 20 12:58:15 PM PST 23
Peak memory 248732 kb
Host smart-5db0e63a-634d-4163-a98a-57f9c765ef6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73112
5467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.731125467
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2227025931
Short name T501
Test name
Test status
Simulation time 409553189 ps
CPU time 19.53 seconds
Started Dec 20 12:57:51 PM PST 23
Finished Dec 20 12:58:27 PM PST 23
Peak memory 246836 kb
Host smart-bd57d1ff-9ea0-4189-b393-4d109eca33d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270
25931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2227025931
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3062696960
Short name T362
Test name
Test status
Simulation time 122672503 ps
CPU time 4.68 seconds
Started Dec 20 12:57:39 PM PST 23
Finished Dec 20 12:58:05 PM PST 23
Peak memory 238812 kb
Host smart-f52cebf2-9086-4d97-a0d8-87886ca1e537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30626
96960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3062696960
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3825396394
Short name T646
Test name
Test status
Simulation time 1288800845 ps
CPU time 22.23 seconds
Started Dec 20 12:57:48 PM PST 23
Finished Dec 20 12:58:29 PM PST 23
Peak memory 248728 kb
Host smart-aa0727af-94bc-4a40-869f-6845921a05ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
96394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3825396394
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2169818346
Short name T594
Test name
Test status
Simulation time 315379403 ps
CPU time 10.53 seconds
Started Dec 20 12:57:57 PM PST 23
Finished Dec 20 12:58:23 PM PST 23
Peak memory 252796 kb
Host smart-0aa54c79-1e47-4a8f-ab6e-be927e286a7b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169818346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2169818346
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2231734762
Short name T609
Test name
Test status
Simulation time 130040265746 ps
CPU time 2915.23 seconds
Started Dec 20 12:57:38 PM PST 23
Finished Dec 20 01:46:36 PM PST 23
Peak memory 314404 kb
Host smart-f99cab39-bebf-4c01-9085-74168ba351af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231734762 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2231734762
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.520775958
Short name T128
Test name
Test status
Simulation time 20606033736 ps
CPU time 1203.6 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 01:18:02 PM PST 23
Peak memory 289524 kb
Host smart-bfff0113-e4b9-4d91-b74a-33a3e183f783
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520775958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.520775958
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.754287771
Short name T452
Test name
Test status
Simulation time 7908548039 ps
CPU time 91.81 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 12:59:30 PM PST 23
Peak memory 248344 kb
Host smart-889facc2-3022-4b4a-af00-af1f6c81e8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75428
7771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.754287771
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3070407402
Short name T581
Test name
Test status
Simulation time 1612306689 ps
CPU time 70.94 seconds
Started Dec 20 12:58:03 PM PST 23
Finished Dec 20 12:59:28 PM PST 23
Peak memory 255108 kb
Host smart-ff097cb9-e431-42e5-8648-694a272ae45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30704
07402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3070407402
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3584914660
Short name T725
Test name
Test status
Simulation time 18143204762 ps
CPU time 1429.76 seconds
Started Dec 20 12:57:40 PM PST 23
Finished Dec 20 01:21:51 PM PST 23
Peak memory 287504 kb
Host smart-b0ed41c9-c7b7-4552-80aa-ca69f31d52fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584914660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3584914660
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3604730662
Short name T413
Test name
Test status
Simulation time 41288288619 ps
CPU time 1343.13 seconds
Started Dec 20 12:57:35 PM PST 23
Finished Dec 20 01:20:19 PM PST 23
Peak memory 272424 kb
Host smart-35d7e07b-3bd0-4561-bc66-aff4f7a73c93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604730662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3604730662
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.577016262
Short name T329
Test name
Test status
Simulation time 7459241486 ps
CPU time 305.27 seconds
Started Dec 20 12:57:47 PM PST 23
Finished Dec 20 01:03:12 PM PST 23
Peak memory 246756 kb
Host smart-a7f56479-8257-4b76-99f7-2259f9a73048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577016262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.577016262
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2013196027
Short name T728
Test name
Test status
Simulation time 3438044297 ps
CPU time 48.4 seconds
Started Dec 20 12:58:01 PM PST 23
Finished Dec 20 12:59:03 PM PST 23
Peak memory 248828 kb
Host smart-d6f37fff-9ee5-41ef-a20d-f781ac8e5d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131
96027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2013196027
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2768914029
Short name T49
Test name
Test status
Simulation time 721069987 ps
CPU time 15.93 seconds
Started Dec 20 12:57:49 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 254024 kb
Host smart-9747ec81-fb8b-4a8a-9a1a-51b3039ec3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27689
14029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2768914029
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3362345340
Short name T139
Test name
Test status
Simulation time 831471267 ps
CPU time 44.73 seconds
Started Dec 20 12:57:51 PM PST 23
Finished Dec 20 12:58:53 PM PST 23
Peak memory 248680 kb
Host smart-3c93c695-f24b-4d38-b345-3144c8ed3b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33623
45340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3362345340
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.836949244
Short name T561
Test name
Test status
Simulation time 860439688 ps
CPU time 50.57 seconds
Started Dec 20 12:57:32 PM PST 23
Finished Dec 20 12:58:44 PM PST 23
Peak memory 256032 kb
Host smart-148a57b9-8c73-4078-bfa2-b17cef09df3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83694
9244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.836949244
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.362414715
Short name T144
Test name
Test status
Simulation time 1032003410 ps
CPU time 60.77 seconds
Started Dec 20 12:57:44 PM PST 23
Finished Dec 20 12:59:05 PM PST 23
Peak memory 248756 kb
Host smart-2c7b21f9-1ad6-4da1-a660-e22fd6be86dc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362414715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.362414715
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.1521826389
Short name T494
Test name
Test status
Simulation time 161018949330 ps
CPU time 4109.66 seconds
Started Dec 20 12:57:38 PM PST 23
Finished Dec 20 02:06:31 PM PST 23
Peak memory 281816 kb
Host smart-92ab9aac-9fa6-42f3-a8bd-b08182f94f60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521826389 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.1521826389
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2830242916
Short name T717
Test name
Test status
Simulation time 27382041879 ps
CPU time 1665.92 seconds
Started Dec 20 12:57:59 PM PST 23
Finished Dec 20 01:25:59 PM PST 23
Peak memory 273352 kb
Host smart-8a0a7017-3b25-4b6d-952f-947cfc44f029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830242916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2830242916
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.312353507
Short name T102
Test name
Test status
Simulation time 378419334 ps
CPU time 20.65 seconds
Started Dec 20 12:58:13 PM PST 23
Finished Dec 20 12:58:52 PM PST 23
Peak memory 255412 kb
Host smart-c0a121c3-921e-4ce9-b2d9-b5f0f5642f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31235
3507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.312353507
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3291249798
Short name T621
Test name
Test status
Simulation time 177082872 ps
CPU time 16.17 seconds
Started Dec 20 12:58:10 PM PST 23
Finished Dec 20 12:58:45 PM PST 23
Peak memory 255248 kb
Host smart-14347cb5-1b1b-4d61-b63e-d71d6aa9f746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32912
49798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3291249798
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4082999271
Short name T315
Test name
Test status
Simulation time 109760513359 ps
CPU time 1655.28 seconds
Started Dec 20 12:58:05 PM PST 23
Finished Dec 20 01:25:56 PM PST 23
Peak memory 272496 kb
Host smart-c399636a-4101-4029-91ea-befeb1f104fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082999271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4082999271
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1297116039
Short name T6
Test name
Test status
Simulation time 53064459007 ps
CPU time 3011.75 seconds
Started Dec 20 12:57:55 PM PST 23
Finished Dec 20 01:48:22 PM PST 23
Peak memory 289680 kb
Host smart-e3dca43c-5f7a-4658-b578-7846c7ba5661
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297116039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1297116039
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.753556204
Short name T333
Test name
Test status
Simulation time 15009445864 ps
CPU time 335.39 seconds
Started Dec 20 12:57:51 PM PST 23
Finished Dec 20 01:03:43 PM PST 23
Peak memory 247612 kb
Host smart-0b02998a-bc1b-4123-80cf-5469773bbc5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753556204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.753556204
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2219330079
Short name T694
Test name
Test status
Simulation time 35797809 ps
CPU time 2.76 seconds
Started Dec 20 12:57:35 PM PST 23
Finished Dec 20 12:57:59 PM PST 23
Peak memory 240572 kb
Host smart-fdc318ee-b66c-408b-ad6a-314230f760ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22193
30079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2219330079
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3332013791
Short name T623
Test name
Test status
Simulation time 1416054237 ps
CPU time 35.12 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 12:59:05 PM PST 23
Peak memory 256100 kb
Host smart-7d437b6c-a27e-4748-8b12-fc64ed699695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320
13791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3332013791
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3195109230
Short name T91
Test name
Test status
Simulation time 2171502716 ps
CPU time 68.58 seconds
Started Dec 20 12:57:52 PM PST 23
Finished Dec 20 12:59:17 PM PST 23
Peak memory 255908 kb
Host smart-4ad0ed22-62eb-411d-a874-81844af8a8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31951
09230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3195109230
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3313996097
Short name T364
Test name
Test status
Simulation time 1382506597 ps
CPU time 31.65 seconds
Started Dec 20 12:58:00 PM PST 23
Finished Dec 20 12:58:45 PM PST 23
Peak memory 248800 kb
Host smart-768c6d9c-cd79-4ac3-afdd-76a38f99aad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33139
96097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3313996097
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2127816979
Short name T219
Test name
Test status
Simulation time 78326352905 ps
CPU time 1396.71 seconds
Started Dec 20 12:58:03 PM PST 23
Finished Dec 20 01:21:34 PM PST 23
Peak memory 286600 kb
Host smart-1e50e294-3eb2-4094-8b19-e17e821bd99d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127816979 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2127816979
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.769258221
Short name T373
Test name
Test status
Simulation time 267495683962 ps
CPU time 1911.33 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 01:30:22 PM PST 23
Peak memory 284572 kb
Host smart-cf9cc63b-1041-4cc7-9784-ff129af166bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769258221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.769258221
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2376351623
Short name T423
Test name
Test status
Simulation time 1204543933 ps
CPU time 36.39 seconds
Started Dec 20 12:57:59 PM PST 23
Finished Dec 20 12:58:49 PM PST 23
Peak memory 248484 kb
Host smart-dd97a1c0-168e-4476-98a1-3f7655c47d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23763
51623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2376351623
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4171568685
Short name T625
Test name
Test status
Simulation time 124633296 ps
CPU time 4.01 seconds
Started Dec 20 12:58:19 PM PST 23
Finished Dec 20 12:58:40 PM PST 23
Peak memory 250596 kb
Host smart-e08315a5-a0da-4279-ba8d-48fa97ff25da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715
68685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4171568685
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.28936843
Short name T126
Test name
Test status
Simulation time 7671863625 ps
CPU time 671.21 seconds
Started Dec 20 12:58:16 PM PST 23
Finished Dec 20 01:09:45 PM PST 23
Peak memory 273292 kb
Host smart-fd60af51-eaaa-4f66-8dd5-dc5bad151fcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28936843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.28936843
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.902869959
Short name T223
Test name
Test status
Simulation time 28238448378 ps
CPU time 311.28 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 01:03:37 PM PST 23
Peak memory 247204 kb
Host smart-2d8a0e7b-397f-49d4-acfd-99dea110b543
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902869959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.902869959
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.935070166
Short name T661
Test name
Test status
Simulation time 555443377 ps
CPU time 22.95 seconds
Started Dec 20 12:58:03 PM PST 23
Finished Dec 20 12:58:41 PM PST 23
Peak memory 248556 kb
Host smart-ff044c6e-1238-4cda-b265-679c978c4231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93507
0166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.935070166
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1008578324
Short name T274
Test name
Test status
Simulation time 299134596 ps
CPU time 30.66 seconds
Started Dec 20 12:58:06 PM PST 23
Finished Dec 20 12:58:53 PM PST 23
Peak memory 248084 kb
Host smart-7ef9dfeb-7fe8-456e-ba07-00f2a6aeea69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10085
78324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1008578324
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.213891631
Short name T103
Test name
Test status
Simulation time 431665000 ps
CPU time 12.71 seconds
Started Dec 20 12:58:16 PM PST 23
Finished Dec 20 12:58:47 PM PST 23
Peak memory 251212 kb
Host smart-06b9ccc3-a833-479f-84be-272073598f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389
1631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.213891631
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.563445999
Short name T42
Test name
Test status
Simulation time 333418902 ps
CPU time 17.47 seconds
Started Dec 20 12:58:05 PM PST 23
Finished Dec 20 12:58:38 PM PST 23
Peak memory 248708 kb
Host smart-dcdf0116-08a0-438b-8789-1c320163d35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56344
5999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.563445999
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.564159126
Short name T664
Test name
Test status
Simulation time 48939141309 ps
CPU time 1675.63 seconds
Started Dec 20 12:58:00 PM PST 23
Finished Dec 20 01:26:09 PM PST 23
Peak memory 273328 kb
Host smart-2f473d92-9e3d-4c58-89ef-32b0272fc575
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564159126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.564159126
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.4033090651
Short name T235
Test name
Test status
Simulation time 22655517 ps
CPU time 2.42 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 12:57:23 PM PST 23
Peak memory 248760 kb
Host smart-153b0982-ae7f-4436-8adf-af14848f3c08
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4033090651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.4033090651
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2055084850
Short name T569
Test name
Test status
Simulation time 104518844758 ps
CPU time 2847.95 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 01:44:24 PM PST 23
Peak memory 289784 kb
Host smart-acb972ee-16aa-4e3b-b23a-4d09eb07d6bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055084850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2055084850
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3096818126
Short name T487
Test name
Test status
Simulation time 487056850 ps
CPU time 11.97 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 12:57:20 PM PST 23
Peak memory 240368 kb
Host smart-87f0b109-ffd3-49a8-9747-7c75d6f8ed42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3096818126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3096818126
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3219070028
Short name T398
Test name
Test status
Simulation time 18426721568 ps
CPU time 238.07 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 01:01:02 PM PST 23
Peak memory 256324 kb
Host smart-f853ab62-fad8-499d-a018-ca506a5bc4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
70028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3219070028
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.134405139
Short name T446
Test name
Test status
Simulation time 791850286 ps
CPU time 45.61 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:58:12 PM PST 23
Peak memory 253580 kb
Host smart-51a3fd69-fa0f-4d1c-aad4-62bc64b86fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13440
5139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.134405139
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2228419511
Short name T345
Test name
Test status
Simulation time 32881028681 ps
CPU time 1731.88 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 01:25:57 PM PST 23
Peak memory 272756 kb
Host smart-a3976739-6256-4a10-8a73-2a70e8916f4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228419511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2228419511
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1042379323
Short name T21
Test name
Test status
Simulation time 535919923110 ps
CPU time 2027.85 seconds
Started Dec 20 12:57:00 PM PST 23
Finished Dec 20 01:31:02 PM PST 23
Peak memory 284068 kb
Host smart-304fd36d-b0ef-4257-aecf-8cde2e9d8d3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042379323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1042379323
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2792609123
Short name T506
Test name
Test status
Simulation time 10571429390 ps
CPU time 446.44 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 01:04:24 PM PST 23
Peak memory 248756 kb
Host smart-07334877-68e5-4e82-988f-a310e756a9f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792609123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2792609123
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1081343772
Short name T455
Test name
Test status
Simulation time 339795050 ps
CPU time 28.36 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:58:07 PM PST 23
Peak memory 248664 kb
Host smart-4b596b0b-4266-410c-bea4-bcd40a73b004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10813
43772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1081343772
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1791386576
Short name T718
Test name
Test status
Simulation time 402571535 ps
CPU time 14.36 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 12:57:26 PM PST 23
Peak memory 248364 kb
Host smart-7a4cc3a4-5105-49e0-be30-7559c9b08d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
86576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1791386576
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3489846424
Short name T47
Test name
Test status
Simulation time 1401655878 ps
CPU time 33.23 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:39 PM PST 23
Peak memory 276988 kb
Host smart-30ca348a-6b76-4458-a988-6359d4b035ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3489846424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3489846424
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.495639294
Short name T290
Test name
Test status
Simulation time 238073823 ps
CPU time 14.64 seconds
Started Dec 20 12:56:50 PM PST 23
Finished Dec 20 12:57:11 PM PST 23
Peak memory 249272 kb
Host smart-3934dbba-8202-4af0-a161-b3b2bc5b0a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49563
9294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.495639294
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2274583461
Short name T622
Test name
Test status
Simulation time 1066269432 ps
CPU time 28.05 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:57:30 PM PST 23
Peak memory 248664 kb
Host smart-a22e246d-7510-4ae9-8def-3b4866851a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
83461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2274583461
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.524645506
Short name T143
Test name
Test status
Simulation time 77427015024 ps
CPU time 3878.44 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 02:02:01 PM PST 23
Peak memory 333632 kb
Host smart-9d14bab5-944f-4b1b-897d-0b03abf14572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524645506 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.524645506
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.130127343
Short name T698
Test name
Test status
Simulation time 182634806829 ps
CPU time 2245.88 seconds
Started Dec 20 12:58:20 PM PST 23
Finished Dec 20 01:36:03 PM PST 23
Peak memory 289152 kb
Host smart-3b89ce50-9507-429b-8fda-7085fa0a3a0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130127343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.130127343
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2922307249
Short name T654
Test name
Test status
Simulation time 23228551450 ps
CPU time 205.21 seconds
Started Dec 20 12:58:37 PM PST 23
Finished Dec 20 01:02:19 PM PST 23
Peak memory 256992 kb
Host smart-21646d32-12f2-4831-b068-2ee0a0c81d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29223
07249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2922307249
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3697499725
Short name T51
Test name
Test status
Simulation time 581793765 ps
CPU time 35.8 seconds
Started Dec 20 12:58:31 PM PST 23
Finished Dec 20 12:59:25 PM PST 23
Peak memory 248444 kb
Host smart-04ba1f17-0fa1-48e9-9edb-6ac6c8f56632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36974
99725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3697499725
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.4035399067
Short name T348
Test name
Test status
Simulation time 30977187386 ps
CPU time 1394.37 seconds
Started Dec 20 12:58:26 PM PST 23
Finished Dec 20 01:21:58 PM PST 23
Peak memory 280888 kb
Host smart-a60bbf76-7362-47b5-9307-6c94734bc114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035399067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.4035399067
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1637300107
Short name T276
Test name
Test status
Simulation time 80320470931 ps
CPU time 1045.67 seconds
Started Dec 20 12:58:19 PM PST 23
Finished Dec 20 01:16:02 PM PST 23
Peak memory 265148 kb
Host smart-4732546a-7433-48e3-82b2-1231d7e333a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637300107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1637300107
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.215814472
Short name T271
Test name
Test status
Simulation time 19211106168 ps
CPU time 382.63 seconds
Started Dec 20 12:58:32 PM PST 23
Finished Dec 20 01:05:13 PM PST 23
Peak memory 246664 kb
Host smart-0c41f94a-83db-42b4-853f-02d12168e650
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215814472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.215814472
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4220972162
Short name T438
Test name
Test status
Simulation time 719891573 ps
CPU time 44.47 seconds
Started Dec 20 12:58:28 PM PST 23
Finished Dec 20 12:59:31 PM PST 23
Peak memory 248696 kb
Host smart-d7b0f707-1098-44bd-8702-6ad447921bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42209
72162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4220972162
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1581731217
Short name T116
Test name
Test status
Simulation time 571106612 ps
CPU time 20.47 seconds
Started Dec 20 12:58:20 PM PST 23
Finished Dec 20 12:58:57 PM PST 23
Peak memory 248284 kb
Host smart-c7585187-db10-4227-aa4a-b951cd979452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15817
31217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1581731217
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2312338964
Short name T508
Test name
Test status
Simulation time 177804619 ps
CPU time 17.03 seconds
Started Dec 20 12:58:15 PM PST 23
Finished Dec 20 12:58:51 PM PST 23
Peak memory 248752 kb
Host smart-09648fc8-2d9b-4429-ba62-197b11f08c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23123
38964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2312338964
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4019098225
Short name T368
Test name
Test status
Simulation time 733152136 ps
CPU time 39.01 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 12:59:05 PM PST 23
Peak memory 256876 kb
Host smart-215e246b-e15e-4bc4-927e-01cd879a6332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40190
98225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4019098225
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2743090580
Short name T531
Test name
Test status
Simulation time 42629178010 ps
CPU time 2307.18 seconds
Started Dec 20 12:58:36 PM PST 23
Finished Dec 20 01:37:21 PM PST 23
Peak memory 289204 kb
Host smart-3852c1f1-ea09-4af3-93e9-82e509cef950
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743090580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2743090580
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2695314421
Short name T704
Test name
Test status
Simulation time 111530279840 ps
CPU time 3265.36 seconds
Started Dec 20 12:57:43 PM PST 23
Finished Dec 20 01:52:29 PM PST 23
Peak memory 297580 kb
Host smart-f625ca25-987a-4602-b6c8-810729681b3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695314421 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2695314421
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2589242504
Short name T118
Test name
Test status
Simulation time 67151487165 ps
CPU time 2181.89 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 01:34:21 PM PST 23
Peak memory 289416 kb
Host smart-2f1df305-6788-42a2-b29d-4b8d68a59b9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589242504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2589242504
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3352277061
Short name T454
Test name
Test status
Simulation time 6451439396 ps
CPU time 126.17 seconds
Started Dec 20 12:58:35 PM PST 23
Finished Dec 20 01:00:59 PM PST 23
Peak memory 256884 kb
Host smart-62e4e54e-b665-4886-972c-d8d0e515d7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33522
77061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3352277061
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.276129094
Short name T710
Test name
Test status
Simulation time 994592901 ps
CPU time 61.54 seconds
Started Dec 20 12:57:57 PM PST 23
Finished Dec 20 12:59:14 PM PST 23
Peak memory 255192 kb
Host smart-32106ff6-df37-4061-888c-c81150dbcac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27612
9094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.276129094
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3249499017
Short name T343
Test name
Test status
Simulation time 51317626808 ps
CPU time 2473.31 seconds
Started Dec 20 12:58:34 PM PST 23
Finished Dec 20 01:40:05 PM PST 23
Peak memory 284172 kb
Host smart-252f228a-991c-454b-a841-30b0ff3e42f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249499017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3249499017
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.714539936
Short name T546
Test name
Test status
Simulation time 76654786048 ps
CPU time 1014.73 seconds
Started Dec 20 12:57:37 PM PST 23
Finished Dec 20 01:14:54 PM PST 23
Peak memory 272660 kb
Host smart-7af90976-ca5c-444b-8d7a-1f58934d6430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714539936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.714539936
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3633469415
Short name T668
Test name
Test status
Simulation time 7350864437 ps
CPU time 283.18 seconds
Started Dec 20 12:58:19 PM PST 23
Finished Dec 20 01:03:19 PM PST 23
Peak memory 247560 kb
Host smart-b4f4b452-550d-49cf-9978-555e7164f17e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633469415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3633469415
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3596079610
Short name T388
Test name
Test status
Simulation time 1024707020 ps
CPU time 12.25 seconds
Started Dec 20 12:58:36 PM PST 23
Finished Dec 20 12:59:06 PM PST 23
Peak memory 252292 kb
Host smart-fa8b122b-5fcb-4eb2-b50d-f7ba86c9cd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35960
79610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3596079610
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2130227831
Short name T641
Test name
Test status
Simulation time 646748514 ps
CPU time 38.52 seconds
Started Dec 20 12:58:40 PM PST 23
Finished Dec 20 12:59:36 PM PST 23
Peak memory 248780 kb
Host smart-ebfa01f7-3843-4267-8534-b43a9f8dd8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21302
27831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2130227831
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3253308641
Short name T575
Test name
Test status
Simulation time 1122692359 ps
CPU time 16.87 seconds
Started Dec 20 12:57:36 PM PST 23
Finished Dec 20 12:58:14 PM PST 23
Peak memory 255488 kb
Host smart-00dc50da-21a9-46f5-a345-239f1438e164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32533
08641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3253308641
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1378055359
Short name T720
Test name
Test status
Simulation time 129124877 ps
CPU time 10.98 seconds
Started Dec 20 12:58:23 PM PST 23
Finished Dec 20 12:58:52 PM PST 23
Peak memory 248824 kb
Host smart-204c4025-8d45-49ee-83b3-a987005b5780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13780
55359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1378055359
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1359842702
Short name T119
Test name
Test status
Simulation time 46563681292 ps
CPU time 2386.09 seconds
Started Dec 20 12:57:53 PM PST 23
Finished Dec 20 01:37:55 PM PST 23
Peak memory 288644 kb
Host smart-c1874a84-fe39-4882-a5bc-14267bcd0f27
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359842702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1359842702
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1406101175
Short name T67
Test name
Test status
Simulation time 96579760872 ps
CPU time 4639.05 seconds
Started Dec 20 12:57:57 PM PST 23
Finished Dec 20 02:15:31 PM PST 23
Peak memory 355080 kb
Host smart-f1b56f03-80b2-4a51-9477-2924afd3df7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406101175 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1406101175
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3176753211
Short name T20
Test name
Test status
Simulation time 26063275662 ps
CPU time 972.3 seconds
Started Dec 20 12:58:07 PM PST 23
Finished Dec 20 01:14:36 PM PST 23
Peak memory 271300 kb
Host smart-b503ca70-5518-43ef-b192-87bf466782f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176753211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3176753211
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.17926228
Short name T81
Test name
Test status
Simulation time 5155613651 ps
CPU time 97.71 seconds
Started Dec 20 12:58:04 PM PST 23
Finished Dec 20 12:59:56 PM PST 23
Peak memory 257028 kb
Host smart-d6ab5f37-25fc-4332-bf1f-3a587d0a177f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17926
228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.17926228
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1900110864
Short name T400
Test name
Test status
Simulation time 144468384 ps
CPU time 12.07 seconds
Started Dec 20 12:57:54 PM PST 23
Finished Dec 20 12:58:21 PM PST 23
Peak memory 254032 kb
Host smart-d19fa390-3e10-4b3d-a81d-94fc6f3342d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19001
10864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1900110864
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2885860079
Short name T338
Test name
Test status
Simulation time 90814311630 ps
CPU time 1336.13 seconds
Started Dec 20 12:58:17 PM PST 23
Finished Dec 20 01:20:51 PM PST 23
Peak memory 272760 kb
Host smart-7dd2c362-bff3-4340-8142-ec830e6313a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885860079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2885860079
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2169205211
Short name T544
Test name
Test status
Simulation time 354261168257 ps
CPU time 2512.15 seconds
Started Dec 20 12:57:42 PM PST 23
Finished Dec 20 01:39:56 PM PST 23
Peak memory 284532 kb
Host smart-a78b16f6-0e11-4459-9d74-131d8a834cd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169205211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2169205211
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3401851573
Short name T261
Test name
Test status
Simulation time 20196756217 ps
CPU time 364.18 seconds
Started Dec 20 12:58:03 PM PST 23
Finished Dec 20 01:04:22 PM PST 23
Peak memory 247632 kb
Host smart-47517c41-da35-412c-b02f-8506ed289ca1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401851573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3401851573
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2364501342
Short name T603
Test name
Test status
Simulation time 13330597129 ps
CPU time 61.61 seconds
Started Dec 20 12:57:58 PM PST 23
Finished Dec 20 12:59:14 PM PST 23
Peak memory 248868 kb
Host smart-80359ecb-be50-41b9-a585-6a0abb44ccb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
01342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2364501342
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4142128210
Short name T476
Test name
Test status
Simulation time 582539305 ps
CPU time 10.33 seconds
Started Dec 20 12:57:44 PM PST 23
Finished Dec 20 12:58:15 PM PST 23
Peak memory 251192 kb
Host smart-7204e6ec-9cd4-4c58-8f13-9a40ee40bc54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41421
28210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4142128210
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.370614648
Short name T297
Test name
Test status
Simulation time 722330650 ps
CPU time 19.35 seconds
Started Dec 20 12:57:50 PM PST 23
Finished Dec 20 12:58:27 PM PST 23
Peak memory 255288 kb
Host smart-33fb4603-0826-43a7-b5f5-a4194a62264e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37061
4648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.370614648
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1705698887
Short name T552
Test name
Test status
Simulation time 62623989 ps
CPU time 4.54 seconds
Started Dec 20 12:57:56 PM PST 23
Finished Dec 20 12:58:15 PM PST 23
Peak memory 240392 kb
Host smart-4414489b-be07-4dfb-8e98-916c751c2e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17056
98887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1705698887
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2620281242
Short name T542
Test name
Test status
Simulation time 89237551263 ps
CPU time 1228.04 seconds
Started Dec 20 12:57:51 PM PST 23
Finished Dec 20 01:18:36 PM PST 23
Peak memory 288688 kb
Host smart-1169814f-367e-4c58-832e-be9d03829a8e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620281242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2620281242
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.124680419
Short name T519
Test name
Test status
Simulation time 26935655658 ps
CPU time 853.16 seconds
Started Dec 20 12:58:02 PM PST 23
Finished Dec 20 01:12:30 PM PST 23
Peak memory 271216 kb
Host smart-2a3ea283-73b8-4026-b6ae-b2d90f94502a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124680419 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.124680419
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1871519079
Short name T101
Test name
Test status
Simulation time 76019915291 ps
CPU time 683.4 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 01:09:48 PM PST 23
Peak memory 265100 kb
Host smart-d6dae67a-9019-4214-b8fe-d945f8781c39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871519079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1871519079
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1236517120
Short name T247
Test name
Test status
Simulation time 1219474056 ps
CPU time 93.31 seconds
Started Dec 20 12:58:02 PM PST 23
Finished Dec 20 12:59:49 PM PST 23
Peak memory 256948 kb
Host smart-c509fff5-09c3-4079-9237-2d727020e197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12365
17120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1236517120
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.814486514
Short name T250
Test name
Test status
Simulation time 3019440186 ps
CPU time 44.76 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 12:59:15 PM PST 23
Peak memory 255332 kb
Host smart-588a709e-d929-4656-866d-759a27dee3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81448
6514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.814486514
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1091476240
Short name T632
Test name
Test status
Simulation time 12069533951 ps
CPU time 1058.03 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 01:16:03 PM PST 23
Peak memory 285248 kb
Host smart-3b8d75a1-b690-4b4b-8d04-1706f1256065
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091476240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1091476240
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3413835264
Short name T660
Test name
Test status
Simulation time 252962212981 ps
CPU time 1410.83 seconds
Started Dec 20 12:57:56 PM PST 23
Finished Dec 20 01:21:42 PM PST 23
Peak memory 272136 kb
Host smart-18f3eccd-39ab-4069-bc7e-7255215a3177
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413835264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3413835264
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2661151750
Short name T477
Test name
Test status
Simulation time 457086001 ps
CPU time 14.14 seconds
Started Dec 20 12:57:41 PM PST 23
Finished Dec 20 12:58:16 PM PST 23
Peak memory 255312 kb
Host smart-0a15f32a-a93a-4f50-b860-8239ce8c9057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26611
51750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2661151750
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.781855712
Short name T123
Test name
Test status
Simulation time 2517462504 ps
CPU time 40.37 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 12:59:07 PM PST 23
Peak memory 255324 kb
Host smart-b64cde3f-72c8-442d-ba1a-818e3018d2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78185
5712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.781855712
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.610258883
Short name T60
Test name
Test status
Simulation time 902185213 ps
CPU time 50.42 seconds
Started Dec 20 12:57:51 PM PST 23
Finished Dec 20 12:58:58 PM PST 23
Peak memory 247136 kb
Host smart-9e395a70-2d81-4921-bf09-00d6f3b0e98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61025
8883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.610258883
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1786226508
Short name T453
Test name
Test status
Simulation time 1032307084 ps
CPU time 16.07 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 12:58:41 PM PST 23
Peak memory 249060 kb
Host smart-e1f06783-c9a9-4ff7-a684-2b2b468c9c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17862
26508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1786226508
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2443060869
Short name T305
Test name
Test status
Simulation time 14970347803 ps
CPU time 205.66 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 01:01:52 PM PST 23
Peak memory 256992 kb
Host smart-e508c6e2-018b-4173-9aaa-e6b9abdc9317
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443060869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2443060869
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.630785253
Short name T570
Test name
Test status
Simulation time 24940219446 ps
CPU time 750.08 seconds
Started Dec 20 12:58:19 PM PST 23
Finished Dec 20 01:11:06 PM PST 23
Peak memory 283596 kb
Host smart-a647f49d-0113-4174-b6de-8252b0d0df36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630785253 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.630785253
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2823277670
Short name T129
Test name
Test status
Simulation time 84687512409 ps
CPU time 2592.12 seconds
Started Dec 20 12:58:19 PM PST 23
Finished Dec 20 01:41:48 PM PST 23
Peak memory 289740 kb
Host smart-61fc4201-6618-4714-9bf1-b39cb56f9e49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823277670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2823277670
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.493425304
Short name T596
Test name
Test status
Simulation time 10970526468 ps
CPU time 168.25 seconds
Started Dec 20 12:58:17 PM PST 23
Finished Dec 20 01:01:22 PM PST 23
Peak memory 256384 kb
Host smart-412ed710-bbc1-4837-8687-e575515e3214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49342
5304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.493425304
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1506212750
Short name T93
Test name
Test status
Simulation time 131030947 ps
CPU time 5.12 seconds
Started Dec 20 12:58:33 PM PST 23
Finished Dec 20 12:58:56 PM PST 23
Peak memory 238684 kb
Host smart-fb7f6347-d453-4a0b-9124-5209f36221b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15062
12750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1506212750
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1834319303
Short name T248
Test name
Test status
Simulation time 53298721780 ps
CPU time 968.29 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 01:14:39 PM PST 23
Peak memory 272712 kb
Host smart-bc58b79e-ab79-4ed1-8acb-4de59f918a0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834319303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1834319303
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3887446918
Short name T473
Test name
Test status
Simulation time 111302535591 ps
CPU time 1654.85 seconds
Started Dec 20 12:58:09 PM PST 23
Finished Dec 20 01:26:02 PM PST 23
Peak memory 272364 kb
Host smart-967a4738-1392-4166-9bc7-efc5a656acae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887446918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3887446918
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.916704083
Short name T645
Test name
Test status
Simulation time 156785646610 ps
CPU time 649.56 seconds
Started Dec 20 12:58:00 PM PST 23
Finished Dec 20 01:09:04 PM PST 23
Peak memory 246704 kb
Host smart-23314d69-8289-4b40-b176-0a9bcddd197b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916704083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.916704083
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1730575962
Short name T372
Test name
Test status
Simulation time 406530196 ps
CPU time 11.87 seconds
Started Dec 20 12:57:59 PM PST 23
Finished Dec 20 12:58:25 PM PST 23
Peak memory 256908 kb
Host smart-1213cc34-3c2a-4cd7-aef0-5144bfbaab10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17305
75962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1730575962
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2683269952
Short name T504
Test name
Test status
Simulation time 126960035 ps
CPU time 11.67 seconds
Started Dec 20 12:58:17 PM PST 23
Finished Dec 20 12:58:47 PM PST 23
Peak memory 248144 kb
Host smart-445ee1de-c114-4e8f-9ed2-afc1e8575da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
69952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2683269952
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.165304356
Short name T125
Test name
Test status
Simulation time 5265533898 ps
CPU time 53.49 seconds
Started Dec 20 12:58:15 PM PST 23
Finished Dec 20 12:59:27 PM PST 23
Peak memory 255408 kb
Host smart-2fe94979-11d1-488e-a170-9709f13c828f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16530
4356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.165304356
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2307573349
Short name T365
Test name
Test status
Simulation time 655547096 ps
CPU time 21.86 seconds
Started Dec 20 12:58:22 PM PST 23
Finished Dec 20 12:59:01 PM PST 23
Peak memory 248780 kb
Host smart-92342554-9625-41aa-ad23-8183facd47c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23075
73349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2307573349
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3460525702
Short name T416
Test name
Test status
Simulation time 18753562509 ps
CPU time 244.11 seconds
Started Dec 20 12:58:09 PM PST 23
Finished Dec 20 01:02:32 PM PST 23
Peak memory 251172 kb
Host smart-74768c7d-8ec4-482f-b500-f7c0ffeb31d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460525702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3460525702
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2039700361
Short name T69
Test name
Test status
Simulation time 148753547330 ps
CPU time 1697.78 seconds
Started Dec 20 12:58:21 PM PST 23
Finished Dec 20 01:26:56 PM PST 23
Peak memory 283508 kb
Host smart-e2128ec1-52ab-493c-99e1-93f688252f04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039700361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2039700361
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3829624198
Short name T395
Test name
Test status
Simulation time 858918776 ps
CPU time 47.28 seconds
Started Dec 20 12:58:40 PM PST 23
Finished Dec 20 12:59:44 PM PST 23
Peak memory 248380 kb
Host smart-15dcd08c-19a0-465b-b9aa-62ecc707ef21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38296
24198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3829624198
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1697777354
Short name T730
Test name
Test status
Simulation time 17229298734 ps
CPU time 55.27 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 12:59:25 PM PST 23
Peak memory 254552 kb
Host smart-df78ea6d-90c3-4fda-9d12-81f27341069b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16977
77354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1697777354
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4039569983
Short name T347
Test name
Test status
Simulation time 82783315550 ps
CPU time 2169.14 seconds
Started Dec 20 12:58:36 PM PST 23
Finished Dec 20 01:35:03 PM PST 23
Peak memory 289144 kb
Host smart-567b4c40-f2af-434a-9374-e36c2ac49f62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039569983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4039569983
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3015439508
Short name T686
Test name
Test status
Simulation time 256579114571 ps
CPU time 3189.12 seconds
Started Dec 20 12:58:05 PM PST 23
Finished Dec 20 01:51:31 PM PST 23
Peak memory 289612 kb
Host smart-b50e3910-d6ed-4ab4-9e7a-c0b29adca366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015439508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3015439508
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3341486235
Short name T553
Test name
Test status
Simulation time 2867533133 ps
CPU time 43.53 seconds
Started Dec 20 12:58:42 PM PST 23
Finished Dec 20 12:59:43 PM PST 23
Peak memory 255892 kb
Host smart-2bd72dbb-a4c4-4713-aea9-a0e7cfe52140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33414
86235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3341486235
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.174310302
Short name T524
Test name
Test status
Simulation time 1907110239 ps
CPU time 34.02 seconds
Started Dec 20 12:58:25 PM PST 23
Finished Dec 20 12:59:17 PM PST 23
Peak memory 248040 kb
Host smart-06733d5c-76d7-42a3-9f7f-e0d3b0bd15c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17431
0302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.174310302
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.175303003
Short name T650
Test name
Test status
Simulation time 1490111382 ps
CPU time 19.24 seconds
Started Dec 20 12:58:08 PM PST 23
Finished Dec 20 12:58:45 PM PST 23
Peak memory 247168 kb
Host smart-a2f71f15-be19-4bf6-9efc-cc8940aa578b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17530
3003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.175303003
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3991800763
Short name T611
Test name
Test status
Simulation time 677364095 ps
CPU time 14.53 seconds
Started Dec 20 12:58:17 PM PST 23
Finished Dec 20 12:58:49 PM PST 23
Peak memory 248692 kb
Host smart-483eecf9-fd1a-4238-ba1c-8ab071a9eded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
00763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3991800763
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2511225183
Short name T140
Test name
Test status
Simulation time 38834797404 ps
CPU time 1964.91 seconds
Started Dec 20 12:57:39 PM PST 23
Finished Dec 20 01:30:46 PM PST 23
Peak memory 273336 kb
Host smart-65ce9437-85e8-453b-b96a-dcf9fe6803c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511225183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2511225183
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3732829025
Short name T296
Test name
Test status
Simulation time 119271221851 ps
CPU time 2597.01 seconds
Started Dec 20 12:57:35 PM PST 23
Finished Dec 20 01:41:14 PM PST 23
Peak memory 320284 kb
Host smart-0648253d-05d8-4adc-81c9-f14814abf2b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732829025 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3732829025
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1925272358
Short name T713
Test name
Test status
Simulation time 42776830845 ps
CPU time 2288.89 seconds
Started Dec 20 12:57:56 PM PST 23
Finished Dec 20 01:36:20 PM PST 23
Peak memory 283336 kb
Host smart-e2bd6f1d-d961-4560-a982-49cad06289fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925272358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1925272358
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3671462817
Short name T277
Test name
Test status
Simulation time 10464570041 ps
CPU time 273.96 seconds
Started Dec 20 12:58:16 PM PST 23
Finished Dec 20 01:03:08 PM PST 23
Peak memory 250780 kb
Host smart-8b37a796-6f9d-4473-8659-4f0d7426cae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36714
62817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3671462817
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2538036427
Short name T432
Test name
Test status
Simulation time 677058556 ps
CPU time 12.54 seconds
Started Dec 20 12:57:58 PM PST 23
Finished Dec 20 12:58:25 PM PST 23
Peak memory 252812 kb
Host smart-4598756a-eec8-4366-aa81-856404eca460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25380
36427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2538036427
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4244316760
Short name T734
Test name
Test status
Simulation time 33152828036 ps
CPU time 1989.71 seconds
Started Dec 20 12:58:04 PM PST 23
Finished Dec 20 01:31:30 PM PST 23
Peak memory 282092 kb
Host smart-eb664125-1ea7-48d5-879d-868d4a8a0b2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244316760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4244316760
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4279122892
Short name T414
Test name
Test status
Simulation time 20074818372 ps
CPU time 861.93 seconds
Started Dec 20 12:58:02 PM PST 23
Finished Dec 20 01:12:39 PM PST 23
Peak memory 288756 kb
Host smart-3ce740dd-3a0b-4088-903c-c5278d4ed8c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279122892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4279122892
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1247551315
Short name T656
Test name
Test status
Simulation time 38404170004 ps
CPU time 395.78 seconds
Started Dec 20 12:57:51 PM PST 23
Finished Dec 20 01:04:44 PM PST 23
Peak memory 247368 kb
Host smart-75dc5bd7-bfbe-4ae8-9dd2-6d563580eab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247551315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1247551315
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3773916712
Short name T280
Test name
Test status
Simulation time 732333621 ps
CPU time 29.84 seconds
Started Dec 20 12:57:38 PM PST 23
Finished Dec 20 12:58:30 PM PST 23
Peak memory 248712 kb
Host smart-434128f7-8743-4cc1-a8b4-09acabc07a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37739
16712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3773916712
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2511516708
Short name T1
Test name
Test status
Simulation time 161795317 ps
CPU time 16.04 seconds
Started Dec 20 12:58:10 PM PST 23
Finished Dec 20 12:58:45 PM PST 23
Peak memory 255156 kb
Host smart-a19721af-1523-432b-92ff-b1cf20cb9ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25115
16708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2511516708
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.729575179
Short name T729
Test name
Test status
Simulation time 1352867493 ps
CPU time 31.61 seconds
Started Dec 20 12:57:46 PM PST 23
Finished Dec 20 12:58:37 PM PST 23
Peak memory 255560 kb
Host smart-b3e8ce1f-0fa5-45e8-a2a0-c4a176dba89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72957
5179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.729575179
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3974327825
Short name T68
Test name
Test status
Simulation time 335061497647 ps
CPU time 1836.97 seconds
Started Dec 20 12:57:55 PM PST 23
Finished Dec 20 01:28:47 PM PST 23
Peak memory 289192 kb
Host smart-9b7867ef-e6e8-4ed6-adc9-e205bbb3f178
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974327825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3974327825
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.4189946957
Short name T602
Test name
Test status
Simulation time 67358539258 ps
CPU time 1234.67 seconds
Started Dec 20 12:58:03 PM PST 23
Finished Dec 20 01:18:52 PM PST 23
Peak memory 281652 kb
Host smart-45a165af-a307-4630-9cde-ce6c55e645c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189946957 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.4189946957
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.4240214140
Short name T705
Test name
Test status
Simulation time 8151374387 ps
CPU time 978.84 seconds
Started Dec 20 12:58:09 PM PST 23
Finished Dec 20 01:14:47 PM PST 23
Peak memory 283112 kb
Host smart-7bc52169-f0ef-4305-a8f7-33588410515e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240214140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.4240214140
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.4240194642
Short name T458
Test name
Test status
Simulation time 29727430994 ps
CPU time 119.65 seconds
Started Dec 20 12:58:17 PM PST 23
Finished Dec 20 01:00:34 PM PST 23
Peak memory 248684 kb
Host smart-d1d5e304-eb7b-4562-85d3-95e61081136d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42401
94642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4240194642
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4228495141
Short name T657
Test name
Test status
Simulation time 2984749731 ps
CPU time 41.79 seconds
Started Dec 20 12:58:22 PM PST 23
Finished Dec 20 12:59:20 PM PST 23
Peak memory 255684 kb
Host smart-1bd8b5ff-7d0b-4c28-88e2-3a9b52c59852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284
95141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4228495141
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4026481081
Short name T589
Test name
Test status
Simulation time 49964936099 ps
CPU time 2290.54 seconds
Started Dec 20 12:58:07 PM PST 23
Finished Dec 20 01:36:34 PM PST 23
Peak memory 288816 kb
Host smart-b2213d50-98a3-48e6-ae3b-4a79de6b3f21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026481081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4026481081
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.233666887
Short name T459
Test name
Test status
Simulation time 51482355763 ps
CPU time 1454.66 seconds
Started Dec 20 12:58:09 PM PST 23
Finished Dec 20 01:22:43 PM PST 23
Peak memory 268564 kb
Host smart-17f61e98-bf07-4c4a-8310-e3f9224cfdef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233666887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.233666887
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.4172463675
Short name T647
Test name
Test status
Simulation time 2338349977 ps
CPU time 94.48 seconds
Started Dec 20 12:58:13 PM PST 23
Finished Dec 20 01:00:11 PM PST 23
Peak memory 247372 kb
Host smart-f15e2ca8-8fd7-4eae-92ed-a82796303850
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172463675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.4172463675
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1316526578
Short name T560
Test name
Test status
Simulation time 652939390 ps
CPU time 38.69 seconds
Started Dec 20 12:57:57 PM PST 23
Finished Dec 20 12:58:51 PM PST 23
Peak memory 248940 kb
Host smart-fa80ca18-59e5-4df5-b576-21db71c5858a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13165
26578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1316526578
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.4171776221
Short name T445
Test name
Test status
Simulation time 470734501 ps
CPU time 25.29 seconds
Started Dec 20 12:57:50 PM PST 23
Finished Dec 20 12:58:33 PM PST 23
Peak memory 248544 kb
Host smart-9af99ba2-9feb-4e59-b6a6-8545cb25b940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41717
76221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.4171776221
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4007302318
Short name T307
Test name
Test status
Simulation time 215369088 ps
CPU time 11.32 seconds
Started Dec 20 12:57:59 PM PST 23
Finished Dec 20 12:58:25 PM PST 23
Peak memory 254484 kb
Host smart-078501ce-245c-4a7a-9afd-7c39be3de3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40073
02318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4007302318
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.845400393
Short name T608
Test name
Test status
Simulation time 1009680075 ps
CPU time 51.99 seconds
Started Dec 20 12:58:10 PM PST 23
Finished Dec 20 12:59:21 PM PST 23
Peak memory 248580 kb
Host smart-76e3c3f0-fabe-4e08-8a31-c6a5ec10a595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84540
0393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.845400393
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3224645841
Short name T483
Test name
Test status
Simulation time 18891828122 ps
CPU time 847.98 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 01:12:39 PM PST 23
Peak memory 289204 kb
Host smart-e40e3870-e818-45d1-94ad-80b4395c8811
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224645841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3224645841
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.810108277
Short name T568
Test name
Test status
Simulation time 181219492812 ps
CPU time 5198.26 seconds
Started Dec 20 12:58:05 PM PST 23
Finished Dec 20 02:25:00 PM PST 23
Peak memory 322036 kb
Host smart-a831234e-f650-4131-b5f2-a204edcdf42f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810108277 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.810108277
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1963185323
Short name T56
Test name
Test status
Simulation time 2388093878 ps
CPU time 136.12 seconds
Started Dec 20 12:58:22 PM PST 23
Finished Dec 20 01:00:55 PM PST 23
Peak memory 255960 kb
Host smart-4c23d0a6-5736-4560-8f58-85571aec5d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19631
85323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1963185323
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.94261717
Short name T427
Test name
Test status
Simulation time 274391797 ps
CPU time 23.14 seconds
Started Dec 20 12:58:03 PM PST 23
Finished Dec 20 12:58:40 PM PST 23
Peak memory 255184 kb
Host smart-f4518fda-7582-433c-9e3b-962ab3b8af33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94261
717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.94261717
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2346471218
Short name T554
Test name
Test status
Simulation time 281636721669 ps
CPU time 2101.36 seconds
Started Dec 20 12:57:59 PM PST 23
Finished Dec 20 01:33:15 PM PST 23
Peak memory 283964 kb
Host smart-90ca4d44-4285-4aaf-ae5d-56e163859e89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346471218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2346471218
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.400570699
Short name T486
Test name
Test status
Simulation time 158980738998 ps
CPU time 2229.54 seconds
Started Dec 20 12:57:54 PM PST 23
Finished Dec 20 01:35:19 PM PST 23
Peak memory 289592 kb
Host smart-3b300877-084b-456f-ae45-7c5744e95238
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400570699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.400570699
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1057014920
Short name T324
Test name
Test status
Simulation time 42248899560 ps
CPU time 445.76 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 01:05:56 PM PST 23
Peak memory 247296 kb
Host smart-a9b13c89-fd6c-43f7-a307-39c054a4cdb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057014920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1057014920
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.4051147541
Short name T376
Test name
Test status
Simulation time 837454501 ps
CPU time 30.57 seconds
Started Dec 20 12:58:00 PM PST 23
Finished Dec 20 12:58:45 PM PST 23
Peak memory 248792 kb
Host smart-56e10974-078e-41e4-8c22-df8d1a4e57c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
47541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4051147541
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2413291569
Short name T566
Test name
Test status
Simulation time 359975098 ps
CPU time 14.87 seconds
Started Dec 20 12:58:19 PM PST 23
Finished Dec 20 12:58:51 PM PST 23
Peak memory 248216 kb
Host smart-c52b3d2c-8e10-4ea5-a629-c878f2eee4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24132
91569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2413291569
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3001479644
Short name T104
Test name
Test status
Simulation time 850460533 ps
CPU time 24.81 seconds
Started Dec 20 12:58:12 PM PST 23
Finished Dec 20 12:58:55 PM PST 23
Peak memory 246828 kb
Host smart-600c281c-7d40-4984-8b8d-87467c331c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30014
79644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3001479644
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3763817220
Short name T264
Test name
Test status
Simulation time 640018370 ps
CPU time 34.23 seconds
Started Dec 20 12:58:06 PM PST 23
Finished Dec 20 12:58:57 PM PST 23
Peak memory 255532 kb
Host smart-9538b328-92c5-40e6-9035-ed9f04cbf1df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37638
17220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3763817220
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3867425230
Short name T617
Test name
Test status
Simulation time 116551245132 ps
CPU time 1237.07 seconds
Started Dec 20 12:57:57 PM PST 23
Finished Dec 20 01:18:49 PM PST 23
Peak memory 287136 kb
Host smart-b9c2ab4e-3af4-4fe8-9368-eeeff3ee8f50
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867425230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3867425230
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.18094360
Short name T112
Test name
Test status
Simulation time 8635542371 ps
CPU time 575.43 seconds
Started Dec 20 12:58:10 PM PST 23
Finished Dec 20 01:08:04 PM PST 23
Peak memory 273432 kb
Host smart-4d08f950-48f3-4440-99f6-d4148ffdb2db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094360 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.18094360
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.151877587
Short name T43
Test name
Test status
Simulation time 104374803096 ps
CPU time 1490.77 seconds
Started Dec 20 12:58:10 PM PST 23
Finished Dec 20 01:23:20 PM PST 23
Peak memory 273192 kb
Host smart-9a78a38e-8097-47c9-aaf9-3d051fcadbc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151877587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.151877587
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1188056913
Short name T426
Test name
Test status
Simulation time 22773759299 ps
CPU time 146.21 seconds
Started Dec 20 12:58:19 PM PST 23
Finished Dec 20 01:01:03 PM PST 23
Peak memory 249652 kb
Host smart-ad0fa37f-0dfe-4330-985d-45582ba9ffc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11880
56913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1188056913
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2494063622
Short name T497
Test name
Test status
Simulation time 511962733 ps
CPU time 27.68 seconds
Started Dec 20 12:58:03 PM PST 23
Finished Dec 20 12:58:45 PM PST 23
Peak memory 248324 kb
Host smart-f966ac87-3197-4f1f-a630-c7a1f1cfcd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24940
63622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2494063622
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2446025737
Short name T740
Test name
Test status
Simulation time 164257372156 ps
CPU time 2220.15 seconds
Started Dec 20 12:58:13 PM PST 23
Finished Dec 20 01:35:31 PM PST 23
Peak memory 288952 kb
Host smart-3f2b73ec-c016-432c-a2cc-dba68ef94594
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446025737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2446025737
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2081597634
Short name T595
Test name
Test status
Simulation time 224780936826 ps
CPU time 1921.81 seconds
Started Dec 20 12:58:02 PM PST 23
Finished Dec 20 01:30:18 PM PST 23
Peak memory 272208 kb
Host smart-bfce1e46-8375-46e9-9fd9-ac412c248b4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081597634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2081597634
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2979092997
Short name T4
Test name
Test status
Simulation time 28270673677 ps
CPU time 274.78 seconds
Started Dec 20 12:58:16 PM PST 23
Finished Dec 20 01:03:09 PM PST 23
Peak memory 247712 kb
Host smart-7c4d16f0-c7cb-419f-8a9c-d822ec9c2b04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979092997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2979092997
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2269202688
Short name T265
Test name
Test status
Simulation time 6385831374 ps
CPU time 44.39 seconds
Started Dec 20 12:57:57 PM PST 23
Finished Dec 20 12:58:57 PM PST 23
Peak memory 248804 kb
Host smart-a509bd1a-e410-43d8-9112-eb1db082053a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22692
02688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2269202688
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3568551168
Short name T605
Test name
Test status
Simulation time 300697325 ps
CPU time 4.66 seconds
Started Dec 20 12:58:00 PM PST 23
Finished Dec 20 12:58:18 PM PST 23
Peak memory 238620 kb
Host smart-93c977ba-0b7f-48f9-84c5-69db73587085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35685
51168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3568551168
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.512542913
Short name T120
Test name
Test status
Simulation time 3823356225 ps
CPU time 13.61 seconds
Started Dec 20 12:57:54 PM PST 23
Finished Dec 20 12:58:23 PM PST 23
Peak memory 253060 kb
Host smart-a23f3176-e5eb-4aaf-8b39-8682bb4730b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51254
2913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.512542913
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3346220352
Short name T490
Test name
Test status
Simulation time 269902736 ps
CPU time 26.25 seconds
Started Dec 20 12:58:01 PM PST 23
Finished Dec 20 12:58:40 PM PST 23
Peak memory 248752 kb
Host smart-c93ea320-0b7f-4149-b99a-274f9e73a373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33462
20352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3346220352
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2096563731
Short name T722
Test name
Test status
Simulation time 15958978625 ps
CPU time 1095.33 seconds
Started Dec 20 12:57:59 PM PST 23
Finished Dec 20 01:16:30 PM PST 23
Peak memory 288000 kb
Host smart-99d2c958-53c6-424a-872f-d0c4b5ac898e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096563731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2096563731
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2854806936
Short name T131
Test name
Test status
Simulation time 101154748231 ps
CPU time 1464.41 seconds
Started Dec 20 12:58:17 PM PST 23
Finished Dec 20 01:23:03 PM PST 23
Peak memory 284824 kb
Host smart-af366c6f-a77a-4170-93f5-c40e645ae288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854806936 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2854806936
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3548714186
Short name T227
Test name
Test status
Simulation time 15796330 ps
CPU time 2.51 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:57:02 PM PST 23
Peak memory 248956 kb
Host smart-8652e0bd-1115-4598-9fea-b2a55cece5d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3548714186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3548714186
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2091792387
Short name T58
Test name
Test status
Simulation time 31130172384 ps
CPU time 1539.32 seconds
Started Dec 20 12:56:55 PM PST 23
Finished Dec 20 01:22:44 PM PST 23
Peak memory 273288 kb
Host smart-bb5838b1-2f30-49e8-a0e3-be7654aeb3cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091792387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2091792387
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1474026602
Short name T222
Test name
Test status
Simulation time 861427907 ps
CPU time 9.96 seconds
Started Dec 20 12:57:05 PM PST 23
Finished Dec 20 12:57:36 PM PST 23
Peak memory 240464 kb
Host smart-9b569b88-6920-4fb8-8562-71c848460ea2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1474026602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1474026602
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.912583382
Short name T456
Test name
Test status
Simulation time 12890238590 ps
CPU time 155 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 12:59:58 PM PST 23
Peak memory 256964 kb
Host smart-7f3850dc-40d9-4327-81bd-370c4c32612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91258
3382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.912583382
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3766039240
Short name T96
Test name
Test status
Simulation time 2068859222 ps
CPU time 55.63 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 12:58:24 PM PST 23
Peak memory 255024 kb
Host smart-86898463-0cf8-4086-846c-ca7275debf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
39240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3766039240
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3553679959
Short name T466
Test name
Test status
Simulation time 43798521524 ps
CPU time 1552.32 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 01:23:43 PM PST 23
Peak memory 289360 kb
Host smart-b01a2fb5-24f4-4dc2-bcd3-e6a98f83a79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553679959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3553679959
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1467178947
Short name T381
Test name
Test status
Simulation time 107948629934 ps
CPU time 1362.64 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 01:20:01 PM PST 23
Peak memory 264796 kb
Host smart-dcfa37b8-30fa-4c7a-bf74-dcf21b4e3a4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467178947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1467178947
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1264041251
Short name T77
Test name
Test status
Simulation time 5988360388 ps
CPU time 249.96 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 01:01:28 PM PST 23
Peak memory 248756 kb
Host smart-a937c297-24fd-4060-823f-f6581e1375ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264041251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1264041251
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.235165706
Short name T502
Test name
Test status
Simulation time 447636361 ps
CPU time 20.66 seconds
Started Dec 20 12:56:59 PM PST 23
Finished Dec 20 12:57:34 PM PST 23
Peak memory 255440 kb
Host smart-61b384c3-742e-4b08-ad48-6406d102e0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23516
5706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.235165706
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2062091389
Short name T45
Test name
Test status
Simulation time 3567028180 ps
CPU time 54.01 seconds
Started Dec 20 12:57:10 PM PST 23
Finished Dec 20 12:58:20 PM PST 23
Peak memory 255212 kb
Host smart-a5328487-cfbc-4018-8d1c-f32bbb401cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20620
91389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2062091389
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2278252197
Short name T537
Test name
Test status
Simulation time 5799800773 ps
CPU time 33.94 seconds
Started Dec 20 12:56:45 PM PST 23
Finished Dec 20 12:57:24 PM PST 23
Peak memory 247748 kb
Host smart-296929cd-77b7-4b67-8597-5ef403ad2b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22782
52197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2278252197
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3087365664
Short name T2
Test name
Test status
Simulation time 2860954343 ps
CPU time 50.62 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:58:18 PM PST 23
Peak memory 248620 kb
Host smart-a4924eb1-fb64-4b59-82c7-a38b08fc9c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30873
65664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3087365664
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3464387064
Short name T286
Test name
Test status
Simulation time 17381618035 ps
CPU time 1393.9 seconds
Started Dec 20 12:57:09 PM PST 23
Finished Dec 20 01:20:39 PM PST 23
Peak memory 299200 kb
Host smart-1d0fefc0-490a-470a-9177-c3456363bcbb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464387064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3464387064
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2521592933
Short name T243
Test name
Test status
Simulation time 55086899 ps
CPU time 4.23 seconds
Started Dec 20 12:57:09 PM PST 23
Finished Dec 20 12:57:28 PM PST 23
Peak memory 248924 kb
Host smart-53ca662a-a882-43e1-8c51-907fe7bc6609
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2521592933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2521592933
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2519479860
Short name T691
Test name
Test status
Simulation time 40499864869 ps
CPU time 1279.48 seconds
Started Dec 20 12:57:01 PM PST 23
Finished Dec 20 01:18:35 PM PST 23
Peak memory 272580 kb
Host smart-d4e2b01f-9505-4c7d-9cd5-94353d059174
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519479860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2519479860
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2061466111
Short name T579
Test name
Test status
Simulation time 308524942 ps
CPU time 9.05 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 12:57:29 PM PST 23
Peak memory 240476 kb
Host smart-0870659f-98fa-4cbb-be49-2bbda9f63f30
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2061466111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2061466111
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3954209333
Short name T367
Test name
Test status
Simulation time 1672774835 ps
CPU time 137.38 seconds
Started Dec 20 12:56:52 PM PST 23
Finished Dec 20 12:59:17 PM PST 23
Peak memory 256120 kb
Host smart-cfb055bb-74c4-409d-aaec-d3a323a604e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39542
09333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3954209333
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1400850443
Short name T382
Test name
Test status
Simulation time 1558934067 ps
CPU time 6.8 seconds
Started Dec 20 12:57:20 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 240184 kb
Host smart-314d1176-51ad-42e9-81e5-b397ad29fc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14008
50443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1400850443
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3262488992
Short name T437
Test name
Test status
Simulation time 9828484766 ps
CPU time 961.38 seconds
Started Dec 20 12:57:00 PM PST 23
Finished Dec 20 01:13:16 PM PST 23
Peak memory 272648 kb
Host smart-54d0d9f6-a404-4b6b-92ca-321b07dc960e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262488992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3262488992
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3559380608
Short name T515
Test name
Test status
Simulation time 23559696111 ps
CPU time 772.67 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 01:10:16 PM PST 23
Peak memory 272880 kb
Host smart-88fb2c85-ebdb-453a-9e2b-5e1590537c54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559380608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3559380608
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.376227262
Short name T564
Test name
Test status
Simulation time 13367846009 ps
CPU time 462.76 seconds
Started Dec 20 12:56:59 PM PST 23
Finished Dec 20 01:04:56 PM PST 23
Peak memory 247696 kb
Host smart-7bc65828-8d34-43bc-a520-33e4032c563f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376227262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.376227262
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.4258756246
Short name T644
Test name
Test status
Simulation time 642154932 ps
CPU time 35.39 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 12:57:43 PM PST 23
Peak memory 255712 kb
Host smart-be5499ec-834b-458e-b5dc-2d5395ac2745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42587
56246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.4258756246
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3238887470
Short name T383
Test name
Test status
Simulation time 1105708936 ps
CPU time 17.18 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 12:57:41 PM PST 23
Peak memory 254916 kb
Host smart-a14f9851-f272-48cc-bde0-6f20d4ec8c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32388
87470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3238887470
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3493732749
Short name T410
Test name
Test status
Simulation time 994823472 ps
CPU time 56.06 seconds
Started Dec 20 12:56:46 PM PST 23
Finished Dec 20 12:57:47 PM PST 23
Peak memory 255344 kb
Host smart-4164748d-7a44-4de0-a1d2-af77c1fe07c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34937
32749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3493732749
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2641333980
Short name T580
Test name
Test status
Simulation time 835840517 ps
CPU time 29.36 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:58:01 PM PST 23
Peak memory 248572 kb
Host smart-29334169-5a09-4119-bb14-11656157a48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
33980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2641333980
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3571976688
Short name T699
Test name
Test status
Simulation time 21079204578 ps
CPU time 996.27 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 01:13:56 PM PST 23
Peak memory 269900 kb
Host smart-cd7c53d7-c25c-4e96-a876-52cd2c8221ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571976688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3571976688
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3988191350
Short name T124
Test name
Test status
Simulation time 41425675644 ps
CPU time 2406.74 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 01:37:38 PM PST 23
Peak memory 289844 kb
Host smart-a656b313-46d7-4db6-981a-0a1f43fd62d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988191350 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3988191350
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.454807929
Short name T23
Test name
Test status
Simulation time 78785478 ps
CPU time 3.48 seconds
Started Dec 20 12:57:12 PM PST 23
Finished Dec 20 12:57:32 PM PST 23
Peak memory 248956 kb
Host smart-81a8851d-37ad-461b-9ab6-78ebce4266bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=454807929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.454807929
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1378597894
Short name T105
Test name
Test status
Simulation time 28465492046 ps
CPU time 1844.13 seconds
Started Dec 20 12:57:23 PM PST 23
Finished Dec 20 01:28:26 PM PST 23
Peak memory 285328 kb
Host smart-b8d61be3-7856-4352-a00c-2fc16a177c9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378597894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1378597894
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1671494919
Short name T220
Test name
Test status
Simulation time 9270978946 ps
CPU time 37.85 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 12:58:06 PM PST 23
Peak memory 248824 kb
Host smart-33db347f-a6ff-448e-b272-c4aa53f6b235
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1671494919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1671494919
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2654521446
Short name T75
Test name
Test status
Simulation time 417488535 ps
CPU time 17.84 seconds
Started Dec 20 12:57:02 PM PST 23
Finished Dec 20 12:57:36 PM PST 23
Peak memory 256080 kb
Host smart-4f693b40-8bbb-49f5-a08a-5432d1fb9dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26545
21446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2654521446
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.69168262
Short name T443
Test name
Test status
Simulation time 297956027 ps
CPU time 17.86 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 12:57:54 PM PST 23
Peak memory 248240 kb
Host smart-0ce5756b-d641-4d17-9a57-298cef80375d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69168
262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.69168262
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3410901979
Short name T637
Test name
Test status
Simulation time 507493526 ps
CPU time 15.07 seconds
Started Dec 20 12:56:51 PM PST 23
Finished Dec 20 12:57:14 PM PST 23
Peak memory 248752 kb
Host smart-967d239a-c588-40c8-8319-7825122990ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34109
01979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3410901979
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3812294339
Short name T134
Test name
Test status
Simulation time 1296877398 ps
CPU time 34.61 seconds
Started Dec 20 12:57:08 PM PST 23
Finished Dec 20 12:57:58 PM PST 23
Peak memory 254784 kb
Host smart-3c770b06-e242-467a-8c60-d1cde88167a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38122
94339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3812294339
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1934351994
Short name T301
Test name
Test status
Simulation time 498468483 ps
CPU time 31.49 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 12:57:52 PM PST 23
Peak memory 255868 kb
Host smart-38075329-7a39-469e-a15b-2c8ef6368d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
51994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1934351994
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2315905758
Short name T640
Test name
Test status
Simulation time 3041772517 ps
CPU time 43.34 seconds
Started Dec 20 12:57:17 PM PST 23
Finished Dec 20 12:58:18 PM PST 23
Peak memory 248744 kb
Host smart-e537d17a-934d-41c4-a436-4d6ab5442a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23159
05758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2315905758
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3728871084
Short name T130
Test name
Test status
Simulation time 13948994589 ps
CPU time 1131.2 seconds
Started Dec 20 12:57:07 PM PST 23
Finished Dec 20 01:16:14 PM PST 23
Peak memory 282472 kb
Host smart-4277c4b8-5cdc-4e1c-91c0-9a1b292f3dc7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728871084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3728871084
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2135951898
Short name T237
Test name
Test status
Simulation time 117618035 ps
CPU time 3.18 seconds
Started Dec 20 12:57:38 PM PST 23
Finished Dec 20 12:58:03 PM PST 23
Peak memory 248876 kb
Host smart-7cc544f8-fd6f-4233-86e0-5f19cea19577
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2135951898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2135951898
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2355105275
Short name T521
Test name
Test status
Simulation time 68507535726 ps
CPU time 1337.84 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 01:19:51 PM PST 23
Peak memory 287664 kb
Host smart-0be4d495-3880-4cef-8fad-29eb5885ea03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355105275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2355105275
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1914412136
Short name T509
Test name
Test status
Simulation time 829060298 ps
CPU time 12.07 seconds
Started Dec 20 12:57:29 PM PST 23
Finished Dec 20 12:58:02 PM PST 23
Peak memory 240556 kb
Host smart-3520f92e-a88c-4fce-b3b8-e470b0c95f55
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1914412136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1914412136
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1245313875
Short name T360
Test name
Test status
Simulation time 1172706824 ps
CPU time 46.86 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 12:58:20 PM PST 23
Peak memory 255908 kb
Host smart-f4c8d331-75fb-44d3-8ad8-1db9cbdf3186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
13875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1245313875
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3662712723
Short name T572
Test name
Test status
Simulation time 577000238 ps
CPU time 30.99 seconds
Started Dec 20 12:57:14 PM PST 23
Finished Dec 20 12:58:02 PM PST 23
Peak memory 253768 kb
Host smart-edfb3c90-9d88-4102-927b-7dd8a6fd7905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36627
12723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3662712723
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2335692582
Short name T669
Test name
Test status
Simulation time 34381285182 ps
CPU time 919.83 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:12:56 PM PST 23
Peak memory 272992 kb
Host smart-af69463f-2442-42c7-859b-db4780298da5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335692582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2335692582
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.485913229
Short name T79
Test name
Test status
Simulation time 36801132441 ps
CPU time 393.62 seconds
Started Dec 20 12:56:56 PM PST 23
Finished Dec 20 01:03:41 PM PST 23
Peak memory 247560 kb
Host smart-22706ba1-cb36-4d26-9059-7efbd7602735
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485913229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.485913229
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1866404853
Short name T716
Test name
Test status
Simulation time 270504543 ps
CPU time 13.3 seconds
Started Dec 20 12:57:13 PM PST 23
Finished Dec 20 12:57:44 PM PST 23
Peak memory 248756 kb
Host smart-191ac791-af9b-45e0-bf40-87d991190251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664
04853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1866404853
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1618680379
Short name T540
Test name
Test status
Simulation time 1364312451 ps
CPU time 28.98 seconds
Started Dec 20 12:57:16 PM PST 23
Finished Dec 20 12:58:03 PM PST 23
Peak memory 255108 kb
Host smart-5419e4e9-9d7d-4346-ac27-8e3b4e7997b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16186
80379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1618680379
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2228957931
Short name T263
Test name
Test status
Simulation time 2592218085 ps
CPU time 16.17 seconds
Started Dec 20 12:56:54 PM PST 23
Finished Dec 20 12:57:20 PM PST 23
Peak memory 256784 kb
Host smart-4e1842fd-cbea-44f4-930e-d385693d541f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22289
57931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2228957931
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3819751270
Short name T298
Test name
Test status
Simulation time 38239524744 ps
CPU time 1572.77 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 01:23:33 PM PST 23
Peak memory 289604 kb
Host smart-e14d42de-e382-4b1b-9ed1-b7dd8ebcfcdf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819751270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3819751270
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2060128821
Short name T100
Test name
Test status
Simulation time 183819857811 ps
CPU time 3622.21 seconds
Started Dec 20 12:57:04 PM PST 23
Finished Dec 20 01:57:42 PM PST 23
Peak memory 334228 kb
Host smart-de7dd2c9-4e22-4b4d-be48-369e386b9530
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060128821 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2060128821
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1401081932
Short name T240
Test name
Test status
Simulation time 178022165 ps
CPU time 2.32 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:57:49 PM PST 23
Peak memory 248928 kb
Host smart-f704f13d-6bdc-4724-bdac-ac7bfc115219
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1401081932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1401081932
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2929593776
Short name T374
Test name
Test status
Simulation time 414677159211 ps
CPU time 2013.75 seconds
Started Dec 20 12:57:34 PM PST 23
Finished Dec 20 01:31:29 PM PST 23
Peak memory 281408 kb
Host smart-7adfa860-e5f0-468d-91e8-d9cb24b499be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929593776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2929593776
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1614126885
Short name T638
Test name
Test status
Simulation time 1698729737 ps
CPU time 37.22 seconds
Started Dec 20 12:57:31 PM PST 23
Finished Dec 20 12:58:29 PM PST 23
Peak memory 240488 kb
Host smart-176b4be4-9523-4950-a1a7-088cf2c29b2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1614126885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1614126885
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1769330365
Short name T86
Test name
Test status
Simulation time 2888257860 ps
CPU time 156.46 seconds
Started Dec 20 12:57:45 PM PST 23
Finished Dec 20 01:00:42 PM PST 23
Peak memory 256120 kb
Host smart-c82e00cc-401a-431f-8fe6-a0ecde2ca9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17693
30365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1769330365
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.697931883
Short name T633
Test name
Test status
Simulation time 749938781 ps
CPU time 27.51 seconds
Started Dec 20 12:57:26 PM PST 23
Finished Dec 20 12:58:14 PM PST 23
Peak memory 248724 kb
Host smart-6d98617e-ce5a-4efd-9de5-b0161cbe037d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69793
1883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.697931883
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.4024672523
Short name T703
Test name
Test status
Simulation time 13445004738 ps
CPU time 711.32 seconds
Started Dec 20 12:57:19 PM PST 23
Finished Dec 20 01:09:29 PM PST 23
Peak memory 267148 kb
Host smart-af1e2299-f591-4b98-bf7b-20504bc447cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024672523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.4024672523
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1754524167
Short name T135
Test name
Test status
Simulation time 32072036571 ps
CPU time 323.19 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 01:03:06 PM PST 23
Peak memory 248764 kb
Host smart-d7c59ed3-3460-4b39-ae01-d021d679bdfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754524167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1754524167
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.218246829
Short name T392
Test name
Test status
Simulation time 1637362626 ps
CPU time 30.69 seconds
Started Dec 20 12:57:15 PM PST 23
Finished Dec 20 12:58:04 PM PST 23
Peak memory 248752 kb
Host smart-cecbd832-a4bc-4ddd-8d3a-3efb0fa5c8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21824
6829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.218246829
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2773978443
Short name T708
Test name
Test status
Simulation time 99380623 ps
CPU time 13.29 seconds
Started Dec 20 12:57:18 PM PST 23
Finished Dec 20 12:57:50 PM PST 23
Peak memory 254216 kb
Host smart-001cf76a-a71a-497f-a446-4b9935ffd51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27739
78443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2773978443
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1662315292
Short name T726
Test name
Test status
Simulation time 308717859 ps
CPU time 36.94 seconds
Started Dec 20 12:57:24 PM PST 23
Finished Dec 20 12:58:20 PM PST 23
Peak memory 248644 kb
Host smart-a5423ab0-670f-4165-b9bc-b197d60cbf9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16623
15292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1662315292
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4010649848
Short name T422
Test name
Test status
Simulation time 3584256587 ps
CPU time 48.62 seconds
Started Dec 20 12:57:21 PM PST 23
Finished Dec 20 12:58:27 PM PST 23
Peak memory 255520 kb
Host smart-c9b9e62e-b9aa-43ad-8f3d-46ac5e4d9970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40106
49848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4010649848
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.144622586
Short name T36
Test name
Test status
Simulation time 222897094825 ps
CPU time 1624.79 seconds
Started Dec 20 12:57:11 PM PST 23
Finished Dec 20 01:24:33 PM PST 23
Peak memory 289464 kb
Host smart-de825cbd-a31a-46b2-9a78-3c168ad9f0b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144622586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.144622586
Directory /workspace/9.alert_handler_stress_all/latest
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