Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T197,T82
1	1	Covered	T1,T2,T3

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	11028	0	0
DisabledNoTrigBkwd_A	2147483647	842586	0	0
DisabledNoTrigFwd_A	2147483647	1699544259	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11028	0	0
T34	1273358	0	0	0
T38	125763	0	0	0
T39	129699	0	0	0
T50	0	731	0	0
T56	32547	0	0	0
T57	57358	0	0	0
T58	16894	0	0	0
T59	396901	0	0	0
T60	441763	0	0	0
T75	100068	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T82	0	248	0	0
T94	53436	0	0	0
T109	853492	0	0	0
T195	47850	0	0	0
T196	3032	530	0	0
T197	1564	82	0	0
T198	3836	1343	0	0
T199	3291	663	0	0
T200	1016	325	0	0
T201	0	1076	0	0
T202	0	841	0	0
T203	0	245	0	0
T204	0	503	0	0
T205	0	452	0	0
T206	0	764	0	0
T207	0	301	0	0
T208	0	313	0	0
T209	0	658	0	0
T210	0	539	0	0
T211	0	708	0	0
T212	0	431	0	0
T213	0	275	0	0
T214	583952	0	0	0
T215	99732	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	842586	0	0
T1	60818	1	0	0
T2	606686	185	0	0
T3	449667	419	0	0
T4	3886136	11	0	0
T5	939576	2076	0	0
T6	269940	7303	0	0
T7	1496660	4469	0	0
T8	2393180	3	0	0
T14	1030854	4858	0	0
T16	0	1140	0	0
T17	0	364	0	0
T18	62868	2	0	0
T19	1962048	204	0	0
T20	1397632	233	0	0
T31	1274	0	0	0
T43	0	54	0	0
T56	0	13	0	0
T57	0	49	0	0
T58	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1699544259	0	0
T1	243272	145700	0	0
T2	1213372	607784	0	0
T3	599556	309586	0	0
T4	3886136	1891695	0	0
T5	939576	484781	0	0
T7	1496660	751212	0	0
T8	2393180	1834230	0	0
T18	62868	49204	0	0
T19	1962048	1408597	0	0
T20	1397632	719655	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T196,T82,T203
1	1	Covered	T1,T2,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	764383546	1837	0	0
DisabledNoTrigBkwd_A	764383546	267512	0	0
DisabledNoTrigFwd_A	764383546	350940344	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1837	0	0
T34	636679	0	0	0
T56	32547	0	0	0
T57	28679	0	0	0
T58	8447	0	0	0
T75	50034	0	0	0
T82	0	248	0	0
T109	426746	0	0	0
T195	23925	0	0	0
T196	3032	530	0	0
T197	782	0	0	0
T203	0	245	0	0
T210	0	539	0	0
T213	0	275	0	0
T214	291976	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	267512	0	0
T1	60818	1	0	0
T2	303343	41	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	9	0	0
T6	0	2588	0	0
T7	374165	8	0	0
T8	598295	2	0	0
T14	0	19	0	0
T16	0	5	0	0
T18	15717	0	0	0
T19	490512	200	0	0
T20	349408	139	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	350940344	0	0
T1	60818	9818	0	0
T2	303343	14822	0	0
T3	149889	149882	0	0
T4	971534	900477	0	0
T5	234894	233222	0	0
T7	374165	373247	0	0
T8	598295	156816	0	0
T18	15717	15665	0	0
T19	490512	27009	0	0
T20	349408	28493	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T18,T5
1	1	Covered	T2,T5,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T201,T202
1	1	Covered	T2,T5,T19

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	764383546	3020	0	0
DisabledNoTrigBkwd_A	764383546	201096	0	0
DisabledNoTrigFwd_A	764383546	444424883	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	3020	0	0
T34	636679	0	0	0
T57	28679	0	0	0
T58	8447	0	0	0
T75	50034	0	0	0
T76	198975	0	0	0
T77	120817	0	0	0
T109	426746	0	0	0
T195	23925	0	0	0
T197	782	82	0	0
T201	0	1076	0	0
T202	0	841	0	0
T208	0	313	0	0
T211	0	708	0	0
T214	291976	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	201096	0	0
T2	303343	144	0	0
T3	149889	0	0	0
T4	971534	0	0	0
T5	234894	4	0	0
T6	0	2141	0	0
T7	374165	1959	0	0
T8	598295	0	0	0
T14	343618	2524	0	0
T16	0	3	0	0
T17	0	1	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	94	0	0
T43	0	36	0	0
T56	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	444424883	0	0
T1	60818	18826	0	0
T2	303343	3593	0	0
T3	149889	149662	0	0
T4	971534	9881	0	0
T5	234894	233836	0	0
T7	374165	2127	0	0
T8	598295	598203	0	0
T18	15717	15665	0	0
T19	490512	454534	0	0
T20	349408	27233	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T18
1	1	Covered	T2,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T198,T199,T200
1	1	Covered	T2,T3,T4

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	764383546	4297	0	0
DisabledNoTrigBkwd_A	764383546	196862	0	0
DisabledNoTrigFwd_A	764383546	445636711	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	4297	0	0
T38	125763	0	0	0
T39	129699	0	0	0
T50	0	731	0	0
T59	396901	0	0	0
T60	441763	0	0	0
T94	53436	0	0	0
T198	3836	1343	0	0
T199	3291	663	0	0
T200	1016	325	0	0
T204	0	503	0	0
T207	0	301	0	0
T212	0	431	0	0
T215	99732	0	0	0
T216	133276	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	196862	0	0
T4	971534	11	0	0
T5	234894	1013	0	0
T6	134970	2569	0	0
T7	374165	2499	0	0
T8	598295	1	0	0
T14	343618	2315	0	0
T16	0	6	0	0
T17	0	363	0	0
T18	15717	0	0	0
T19	490512	0	0	0
T20	349408	0	0	0
T31	1274	0	0	0
T43	0	18	0	0
T56	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	445636711	0	0
T1	60818	60726	0	0
T2	303343	297362	0	0
T3	149889	9443	0	0
T4	971534	9885	0	0
T5	234894	8969	0	0
T7	374165	2143	0	0
T8	598295	481008	0	0
T18	15717	15665	0	0
T19	490512	463136	0	0
T20	349408	336107	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
55	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T205,T206,T209
1	1	Covered	T2,T3,T18

 LINE       55
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T18,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	764383546	1874	0	0
DisabledNoTrigBkwd_A	764383546	177116	0	0
DisabledNoTrigFwd_A	764383546	458542321	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	1874	0	0
T205	1224	452	0	0
T206	4268	764	0	0
T209	0	658	0	0
T217	943903	0	0	0
T218	22441	0	0	0
T219	36083	0	0	0
T220	227012	0	0	0
T221	455411	0	0	0
T222	163217	0	0	0
T223	171836	0	0	0
T224	78522	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	177116	0	0
T3	149889	419	0	0
T4	971534	0	0	0
T5	234894	1050	0	0
T6	134970	5	0	0
T7	374165	3	0	0
T8	598295	0	0	0
T14	343618	0	0	0
T16	0	1126	0	0
T18	15717	2	0	0
T19	490512	4	0	0
T20	349408	0	0	0
T56	0	3	0	0
T57	0	49	0	0
T58	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	764383546	458542321	0	0
T1	60818	56330	0	0
T2	303343	292007	0	0
T3	149889	599	0	0
T4	971534	971452	0	0
T5	234894	8754	0	0
T7	374165	373695	0	0
T8	598295	598203	0	0
T18	15717	2209	0	0
T19	490512	463918	0	0
T20	349408	327822	0	0